CN103872006A - 级联电路 - Google Patents

级联电路 Download PDF

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CN103872006A
CN103872006A CN201310684492.6A CN201310684492A CN103872006A CN 103872006 A CN103872006 A CN 103872006A CN 201310684492 A CN201310684492 A CN 201310684492A CN 103872006 A CN103872006 A CN 103872006A
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transistor
circuit
cascade
substrate
source electrode
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菲利普·鲁特尔
简·雄斯基
马塞厄斯·罗斯
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Yasuyo Co Ltd
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Koninklijke Philips Electronics NV
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Abstract

一种级联电路结构具有安装在衬底(例如，陶瓷衬底)上的低压MOSFET和耗尽型功率器件，该级联电路结构于是可以设于半导体封装中。这使得能够降低电感，且如果需要则能够使用三端子封装。

Description

级联电路
技术领域
本发明涉及级联半导体器件。具体地，本发明涉及耗尽型晶体管，例如，高电子迁移率晶体管或结型栅场效应晶体管。示例是氮化镓(GaN)晶体管(例如，GaN高电子迁移率晶体管(HEMT))或碳化硅(SiC)场效应晶体管。
背景技术
本发明尤其关注于GaN功率晶体管。由于在GaN晶片的生长期间产生的内建异质结的存在，基础GaN功率半导体是耗尽型(常通型)器件。这在材料中产生薄的高导电性区域，称为二维电子气(“2DEG”)，有效地限定了晶体管沟道。
为了制作常断型GaN器件，需要对2DEG进行干扰以便阻止其导通的手段。尝试在功率半导体的叠层中引入附加层，以便使器件常断(从而可以与MOSFET互换)，但是这种尝试伴随着器件性能代价，例如比常通型器件差的导通电阻。
因此，将高压GaN开关与传统低压硅MOSFET级联是结合硅和GaN功率器件优点的可行选择。
级联开关的优点在于可以使用现有的标准栅极驱动器，因为器件驱动特性主要由硅MOSFET确定。因此，这种器件可以用于直接代替硅MOSFET或IGBT。
图1示出按级联配置将常通型氮化镓晶体管(MGaN)和常断型硅MOSFET晶体管(MSi)功率开关串联连接的公知方法。随着与硅基开关相比具有优越器件特性的新型GaN和SiC功率半导体不断涌现，这种方法对于功率电子应用变得越来越普遍。
在图1的标准级联配置中，只有硅MOSFET MSi受到产生栅极信号VGM的栅极驱动器的主动控制。GaN开关MGaN经由硅MOSFET MSi来间接受控，因为MOSFET的漏-源电压等于GaN的源-栅电压。
在如图1所示的级联电路中，部件间的互连将降低切换速度，而高切换速度是GaN的期望优点之一。这将导致电压过冲，而电压过冲可能影响低压MOSFET的额定电压(且因此影响成本)。
因此，需要建立使级联结构的电感(和寄生电阻)最小化的结构。为了最小化电压过冲和震荡以及保护GaN器件的栅极，能够将附加部件结合到级联电路中也是有利的。例如，曾提出将GaN晶体管用于功率因数校正(PFC)电路中。对于PFC应用(GaN的最初目标市场)，也可以用GaN来制作PFC二极管。集成PFC二极管的方法也具有潜在优势。
图2示出了级联结构的电感。存在一系列的源极、漏极和栅极电感LS、LD和LG以及内部电感Lint1、Lint2和Lint3。Lint1在GaN源极和MOSFET漏极之间，Lint2在封装源极和GaN栅极之间，且Lint3在封装源极和MOSFET源极之间。
当切换低电压MOSFET时，LS和Lint3的电感是关键的，因为在导通时这些电感随着电流快速提升而降低栅极驱动电压，使得得到的电流改变率di/dt由下式确定：
di dt = ( Vdrive - Vgs ) * gfs Cgs * ( Rdriver + Rgate ) + ( Ls + Lint 3 ) * gfs
Cgs、gfs和Rgate是指LVMOS的参数。
在电流截止时，发生相反的情况，这些电感增加栅极电压，因此限制了器件中电流降低的速率。
为了实现快速切换(以di/dt周期计)，最小化LS和Lint3是非常重要的。然而，如果LS和Lint3与应用中的总电感相比太低，则由于级联电路中较低的源极电感引起的高di/dt能够导致相当大的电压过冲。
在级联结构中，存在可以在切换期间影响di/dt的附加因素，即Lint1和Lint3对于GaN器件是否导通/截止的影响。
例如，当级联器件正在导通且电流快速升高时，正电压(等于L*di/dt)将出现在LS、Lint1及Lint3上。在低压MOS上，LS和Lint3将降低低压MOS栅极驱动并最终限制可实现的最大di/dt。对于GaN器件，Lint1和Lint3上的电压将作为负电压作用于GaN器件的栅源电压上，并开始使GaN器件截止，由此限制di/dt并增加功率损耗。
因此，在级联器件中，级联结构中的内部电感大小也是至关重要的。
在上图中，Lint3限制di/dt的效果可以通过将Lint2直接连接到低压MOSFET的源极金属而不是LS来去除。电感LS包含了接合焊盘、内部封装互连以及封装管脚的电感。在这种情况下，最小化Lint1成为至关重要的事情。
上述基础级联电路(即，没有附加部件)的另一问题在于其被设计为三端子电路，以在外部电路中连接到源极、漏极和栅极端子。然而，将该电路封装到三管脚封装(例如，TO220封装)中通常是不可能的。硅MOSFET是垂直器件，所以漏极(在垂直结构的底部)连接到金属引线框并因此连接到TO220的管脚之一。由于MOSFET漏极不是级联电路的输出端子之一，这意味着需要具有4个或更多管脚的封装。
图3示出了按常规方式如何将级联电路安装在5管脚封装中(由于4管脚封装不常见)。
MOSFET10是漏极处于底部且源极(和栅极)处于顶部的垂直器件。MOSFET10安装在封装管芯附接区导体平面上，使得漏极连接到该平面。该导体平面连接到端子之一12。GaN晶体管14具有连接到该导体平面的衬底，且三个端子在顶部。因此，GaN晶体管14的衬底和低压MOSFET10的漏极电连接。
在上述级联电路的情况下，这意味着管芯附接区及其相关端子现连接到内部节点，所以就需要四/五个管脚的变型。MOSFET栅极和源极通过接合线16、18连接到相应的端子，且GaN漏极通过接合线20连接到第三端子。内部接合线连接22将MOSFET源极连接到GaN栅极，且另一接合线24从GaN源极连接到管芯附接导体平面。
除了需要比到该电路的外部连接的数量多的管脚，该封装中的性能受限于内部电感。如果在器件周围添加附加部件，且最小化内部连接的电感，也可以改善该性能。
发明内容
根据本发明，提供了一种如权利要求所述的电路。
在一个方面，本发明提供了一种级联晶体管电路，包括：
第一耗尽型晶体管，其漏极用于连接到高电源线；
第二硅MOSFET，其漏极连接到第一晶体管的源极，其源极用于连接到低电源线；
衬底，第一和第二晶体管安装在该衬底上，该衬底具有提供第一晶体管的源极和第二晶体管的漏极之间的连接的导电轨道。
本发明将级联电路设置在单独的衬底上，这使得可以最小化内部电感。这也使得可以添加能改善最终产品的成本/性能的附加部件。
该电路优选性地形成为封装器件，具有从第一晶体管漏极到第一封装端子的第一连接、从第二晶体管栅极到第二封装端子的第二连接以及从第二晶体管源极到第三封装端子的第三连接，其中封装端子之一包括管芯附接焊盘端子。例如，第二晶体管源极可以连接到该管芯附接焊盘端子。
这使得电路能够设置在三端子封装中，因为管芯附接焊盘(即，封装的引线框/线框端子连接)可以用于外部电路连接之一。例如，衬底组件可以设于3-端子TO220封装中，该封装具有连接到源极而不是漏极的主引线框(连接了热沉的器件接头)。将该接头连接到源极降低了对快速切换器件(例如GaN)而言重要的EMI，并且由于不再需要对热沉的电隔离，也降低了散热的成本。相同的热沉可以连接到多个器件。
这使得第二晶体管可以是漏极处于底部的垂直器件。衬底可以包括陶瓷衬底。
第一晶体管可以包括焊料凸块，并倒装接合到衬底上。第二晶体管可以包括连接到衬底的连接接线柱(clip)。这样，可以对每个晶体管到衬底的连接进行单独优化。
该电路可以包括安装在衬底上的其它部件。这些其它部件可以包括：
电容器、RC缓冲(snubber)电路或二极管，用于限制第一晶体管的漏极处的最大电压；或
二极管，用于功率因数校正。
第一耗尽型晶体管可以包括高电子迁移率晶体管或结型栅场效应晶体管，例如，GaN晶体管。
本发明也提供了一种电路结构，包括：
本发明的级联晶体管电路；以及
栅极驱动电路，具有单一栅极输出线。
设备可以包括：
电源；或
功率因数校正电路；或
逆变电路；或
开关模式功率变换电路。
附图说明
现将参考附图来详细描述本发明的示例，附图中：
图1示出公知级联电路；
图2示出与图1的电路有关的电感；
图3示出封装图1的电路的一种方法；
图4示出本发明的级联电路的第一示例；
图5示出如何将图4的电路连接到三管脚封装的封装端子；以及
图6示出对图4的电路的改型，以便提供功率晶体管的备选安装。
具体实施方式
本发明提供了一种级联电路结构，其中低压MOSFET和耗尽型功率器件安装在衬底(例如，陶瓷衬底)上，该电路结构于是可以设于半导体封装中(或者，单独销售给希望生产自己模块的客户)。以下将仅参照GaN器件，但是相同方法适用于SiC器件或其它耗尽型器件。本发明关注于高电子迁移率晶体管或结型栅场效应晶体管。
图4示出了本发明的电路示例。示出了部件的布局，但是电路对应于图1(尽管如下所述在图4中示出了可选的附加部件)。
该电路具有第一氮化镓或碳化硅场效应晶体管40，具有用于连接到高电源线的漏极D。第二硅MOSFET42的漏极连接到第一晶体管40的源极，且其源极S用于连接到低电源线。
这两个晶体管安装在衬底43上，衬底43可以包括例如陶瓷衬底。
第二晶体管42是漏极在底部的垂直器件。其连接到提供导电轨道的焊盘44，该导电轨道提供第一晶体管40的源极与第二晶体管42的漏极之间的连接。该焊盘处于如Vx所示的内部节点电压。该焊盘包括用于第一晶体管40的源极指46。在相同层中形成漏极指48，漏极指48连接到漏极焊盘50，该漏极焊盘50是用于连接到高压线的第一外部电路端子。
第二晶体管42的源极位于垂直结构的顶部，向下连接到源极焊盘52，该源极焊盘52是用于连接到低压线的第二外部电路端子。将接线柱(clip)54示出为用于该目的。源极焊盘52也通过轨道55连接到第一晶体管40的栅极。
用于第二晶体管的栅极焊盘56提供第三外部端子。
在优选示例中，GaN第一晶体管40通过凸块倒装在陶瓷衬底43上，以便最小化寄生电感和电阻。然而，也可以使用引线接合。
低压硅MOSFET第二晶体管42优选地用铜接线柱54连接到陶瓷衬底，但是也可以是倒装或引线接合的横向器件，或可以是已经封装在低电感封装(例如，直接FET(Direct FET))中。这在接线柱接合在所需封装中不可用的情况下是合适的选择。
GaN第一晶体管的衬底(朝上)可以连接到源极、漏极或浮置，这取决于何种方式会给出最优性能。通常，如果器件是所示的倒装接合，则最实用的选择是将衬底浮置。
对低压MOS晶体管42使用铜接线柱54以及使用倒装接合凸块安装的GaN晶体管40的优选设置显著地降低了寄生电感。
陶瓷衬底43上的轨道44可以设置为针对低电感和电阻进行优化(通过使用宽轨道，并选择使功率轨道的互电感最小化的线路)。图4的示例是描述基本构思的一个简单示例。
使用附加衬底43使得能够向电路添加附加部件。
例如，在级联器件中，希望限制内部节点(Vx)处的最大电压，最小化GaN器件上的栅-源电压应力，以及能够使用具有最低可能VDS规格的硅MOSFET。在高压电路中使用MOSFET意味着MOSFET可能受到会导致早期故障的多种可能电流和电压条件。限制电压Vx作为一种保护机制。
图4示出了在源极端子和内部节点Vx之间连接的附加电容器60。这也可以是RC缓冲器、齐纳二极管(用于钳制最大Vx电压)，或者肖特基二极管，以便最小化低压MOSFET42中的反向恢复损耗。
该构思可以容易地扩展为包括PFC二极管，以便生产集成PFC产品，其中PFC可以是单独的管芯或集成在GaN管芯中。注意，这将需要4管脚封装。进一步的集成可以包括PFC电路的控制IC。
高压(～600V)MOSFET的常见封装是称为TO220的封装，这是三端子封装，其中一个端子连接到作为管芯附接焊盘的线框/引线框焊盘。它也电连接到热沉连接。由于相对低技术PCB材料和制作技术，这种类型的通孔封装是优选的。
当使用垂直功率器件(其中衬底是漏极)时这种封装的缺点在于该封装的暴露接头处于漏极电势。如果功率器件需要散热，则提供所需电隔离增加了整体方案的复杂度(且因此增加了成本)。
对于快速切换瞬变而言，处于漏极电势的暴露接头同样是不需要的EMI的源。由于与当前使用的现有高压MOSFET相比固有地更快速的切换瞬变，所以这个问题在级联器件中更为显著。
从以上描述可知，本发明能够令电路集成到具有暴露的线框/引线框的封装中，同时确保暴露的接头处于源极电势。这消除了在散热时对隔离的需要，并通过显著减小可以发射EMI的漏极区域而显著地降低了EMI。
图5示出了将图4的电路集成到三端子TO220封装70中，其中中心接头连接到管芯附接焊盘区和热沉座72。
从电路衬底的焊盘50、52、56到封装端子76G、76S、76D的连接74理想地具有低电感，例如接线柱连接(clip connection)、带连接(ribbon connection)或多接合线。
图6示出图4的改型，其中对GaN功率晶体管40进行引线接合，而不是倒装接合。在这种情况下，源极接合焊盘80、漏极接合焊盘82和栅极焊盘84在结构的顶部，且接合线连接到衬底上的相应轨道。在所示示例中，第一晶体管40的衬底(朝下)连接到源极电势，即，连接到中间节点Vx。然而，衬底可以浮置、连接到漏极或源极端子(即，硅MOSFET的源极)。
本发明提供了一种级联结构，其可以通过降低寄生电感和添加附加部件来对性能进行优化。
本发明可以用于需要常断型开关的所有功率变换应用中，并使得能够在这种应用中使用常通型GaN或SiC器件。例如，本发明可以用于：
功率因数校正(PFC)电路，例如，用于电网连接的电源中的PFC电路；
高压逆变电路的相位臂，例如电机驱动或光电变换器；
开关模式(例如，软切换)功率变换电路。
根据对附图、公开内容和所附权利要求的研究，本领域普通技术人员在实践所要求保护的发明时，可以理解和实施对于所公开实施例的其他变化。在相互不同的从属权利要求中描述一些措施的事实并不表示不能有利地使用这些措施的组合。权利要求中的任意附图标记不应该解释为限制范围。

Claims (15)

1.一种级联晶体管电路，包括：
第一耗尽型晶体管(40)，其漏极(50)用于连接到高电源线；
第二硅MOSFET(42)，其漏极连接到第一晶体管(40)的源极，其源极用于连接到低电源线；
衬底(43)，第一和第二晶体管(40，42)安装在该衬底(43)上，衬底(43)具有提供第一晶体管的源极与第二晶体管的漏极之间的连接的导电轨道(44)。
2.根据权利要求1所述的级联晶体管电路，形成为封装器件，具有从第一晶体管漏极(50)到第一封装端子的第一连接、从第二晶体管栅极(56)到第二封装端子的第二连接以及从第二晶体管源极(52)到第三封装端子的第三连接，其中封装端子之一包括管芯附接焊盘端子。
3.根据权利要求2所述的级联晶体管电路，其中第二晶体管源极(52)连接到管芯附接焊盘端子。
4.根据权利要求2或3所述的级联晶体管电路，包括三端子封装。
5.根据任一前述权利要求所述的级联晶体管电路，其中第二晶体管(42)是垂直器件。
6.根据权利要求5所述的级联晶体管电路，其中第二晶体管漏极在底部。
7.根据任一前述权利要求所述的级联晶体管电路，其中衬底(43)包括陶瓷衬底。
8.根据任一前述权利要求所述的级联晶体管电路，其中第一晶体管(40)包括焊料凸块，并倒装接合到衬底上。
9.根据任一前述权利要求所述的级联晶体管电路，其中第二晶体管(42)包括连接到衬底的连接接线柱(54)。
10.根据任一前述权利要求所述的级联晶体管电路，包括安装在衬底上的其他部件(60)。
11.根据权利要求10所述的级联晶体管电路，其中所述其他部件包括：
电容器、RC缓冲电路或二极管，用于限制第一晶体管的漏极处的最大电压；或
二极管，用于功率因数校正。
12.根据任一前述权利要求所述的级联晶体管电路，其中第一耗尽型晶体管(40)包括高电子迁移率晶体管或结型栅场效应晶体管。
13.根据权利要求12所述的级联晶体管电路，其中第一耗尽型晶体管(40)包括GaN晶体管。
14.一种电路结构，包括：
根据任一前述权利要求所述的级联晶体管电路；以及
栅极驱动电路，具有单一栅极输出线。
15.一种包括如权利要求14所述的电路结构的设备，其中所述设备包括：
电源；或
功率因数校正电路；或
逆变电路；或
开关模式功率变换电路。
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