CN109326588B - 一种GaN基级联功率器件及其封装方法 - Google Patents
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Abstract
本发明公开了一种GaN基级联功率器件及其封装方法。该GaN基级联功率器件包括大栅宽GaN基功率芯片、硅基功率MOS芯片、TO‑220框架、小铜基板、导电银浆和绝缘胶;大栅宽GaN基功率芯片是横向结构的高耐压、耗尽型GaN基功率芯片,硅基功率MOS芯片是垂直结构的低压、增强型硅基功率MOS芯片。硅基功率MOS芯片通过导电银浆与小铜基板连接,小铜基板通过绝缘胶与TO‑220框架的基岛连接;大栅宽GaN基功率芯片通过绝缘胶固定在TO‑220框架的基岛上;本发明通过引入Cascode方式,将大栅宽GaN基功率芯片与硅基功率MOS芯片结合起来,组合成实用性更广的增强型的GaN基功率器件。
Description
技术领域
本发明属于微电子技术领域,涉及半导体器件,具体的说是一种GaN基级联功率器件及其封 装方法,适用于高压大功率电子器件等应用。
背景技术
随着现代武器装备和航空航天、核能、通信技术、汽车电子、开关电源的发展,对半导体器 件的性能提出了更高的要求。作为宽禁带半导体材料的典型代表,GaN基材料具有禁带宽度大、 电子饱和漂移速度高、临界击穿场强高、热导率高、稳定性好、耐腐蚀、抗辐射等特点,可用于制作高温、高频及大功率电子器件。另外,GaN还具有优良的电子特性,可以和AlGaN形成调制 掺杂的AlGaN/GaN异质结构,该结构在室温下可以获得高于1500cm2/Vs的电子迁移率,以及高达3×107cm/s的峰值电子速度和2×107cm/s的饱和电子速度,并获得比第二代化合物半导体异 质结构更高的二维电子气密度,被誉为是研制微波功率器件的理想材料。因此,基于AlGaN/GaN 异质结的微波功率器件在高频率、高功率的无线通信、雷达等领域具有非常好的应用前景。
氮化镓高电子迁移率晶体管(GaNHEMT)可以分为增强型和耗尽型两种。目前单体增强型 GaNHEMT器件的额定电压最大能达到250V。对于单体增强型GaNHEMT,当其驱动电压达到阀值电 压VTH=1.5V时,器件就会导通,器件完全导通的栅极电压为4.5V~5.5V,由于其最大栅源电压 Vgs为6V,因此增强型GaN器件对驱动设计要求较高。单体耗尽型GaNHEMT的驱动电压范围为 -30~2V,器件完全导通栅极电压为-5V,驱动电压范围较宽。然而,由于耗尽型GaNHEMT为常通 型器件,使用时需要负压关断,有短路直通的潜在危险。
发明内容
本发明的目的在于克服上述已有技术的缺陷,提供一种易于升级换代,重复性好,适用于高 压大功率电子器件,实用性更广的增强型的GaN基级联功率器件及其封装方法。
本发明的目的通过如下技术方实现:
一种GaN基级联功率器件,包括大栅宽GaN基功率芯片、硅基功率MOS芯片、TO-220框架、 小铜基板、导电银浆和绝缘胶;
硅基功率MOS芯片和大栅宽GaN基功率芯片间隔设置在TO‐220框架的基岛上,设置位置 为左右设置,硅基功率MOS芯片左侧,大栅宽GaN基功率芯片在右侧;所述硅基功率MOS芯片 是垂直结构的低压、增强型硅基功率MOS芯片;所述大栅宽GaN基功率芯片是横向结构的高耐 压、耗尽型GaN基功率芯片;
所述硅基功率MOS芯片通过导电银浆与小铜基板连接,小铜基板通过绝缘胶与TO-220框架 的基岛连接;大栅宽GaN基功率芯片通过绝缘胶固定在TO-220框架的基岛上;
硅基功率MOS芯片的栅极用一根38μm铜质内引线连接到TO-220框架的源极;硅基功率MOS 芯片的源极用三根125μm铝质内引线连接到TO-220框架的基岛;硅基功率MOS芯片的漏极通过 导电银浆引出到小铜基板;小铜基板的面积大于硅基功率MOS芯片,小铜基板上有一部分的空位, 从小铜基板的空位处引出三根125μm铝质内引线到大栅宽GaN基功率芯片的源极;
大栅宽GaN基功率芯片的栅极通过三根125μm铝质内引线连接到TO-220框架的基岛上,大 栅宽GaN基功率芯片的漏极用4根125μm铝质内引线引出到TO-220框架的漏极,作为GaN基级 联功率器件的漏极。
为进一步实现本发明目的,优选地,所述GaN基级联功率器件用无卤塑封料对装载在铜质 TO-220框架进行注塑包裹;所述无卤塑封料是长方体,将TO-220框架的基岛和栅极、源极、漏 极包裹在内。
优选地,所述TO-220框架为T-220FL框架,包括大小为6.0mm×8.8mm的长方形基岛、由基 岛延伸出来的引脚S极、位于基岛左下方的引出到塑封体外的引脚G极、位于金属基岛右下方的 引出到塑封体外的引脚D极。
优选地,所述硅基功率MOS芯片为N型的VDMOS结构。
优选地,所述硅基功率MOS芯片的栅极的区域大小为112μm×112μm,源极的区域大小为 857×633μm,漏极的区域大小优选为1160μm×820μm。
优选地,所述大栅宽GaN基功率芯片的大小为5770μm×1900μm,其中大栅宽GaN基功率 芯片的栅极的区域大小为5700μm×250μm,源极的区域大小为5240μm×300μm,漏极D2的区 域大小为5240μm×300μm。
优选地,所述小铜基板的大小为1.5mm×2.5mm。
优选地,所述导电银浆和绝缘胶的厚度均为20μm-40μm。
所述的GaN基级联功率器件的封装方法,包括如下步骤:
1)划片工艺:通过划片机,将一整片的大栅宽GaN基功率芯片晶圆分割成分立的单颗芯片;
2)粘片工艺:先用绝缘胶把小铜基板和大栅宽GaN基功率芯片分别固定到TO-220FL框架基 岛的左右两边;然后再改用导电银浆,把硅基功率MOS芯片固定到小铜基板上;
3)烘烤工序:完成粘片后放进烘箱烘烤,烘箱内抽真空后,充入氮气作为保护气体,确保 烘箱内的氧气含量保持在100ppm以下;烘烤完成后,待烘箱内的温度降低至室温,拿出芯片;
4)压焊工艺:硅基功率MOS芯片的栅极用一根38μm铜质内引线连接到TO-220框架的源极, 硅基功率MOS芯片的源极用三根125μm铝质内引线连接到TO-220框架的基岛;硅基功率MOS 芯片的漏极通过导电银浆引出到小铜基板;从小铜基板的空位处引出三根125μm铝质内引线到 大栅宽GaN基功率芯片的源极S2;大栅宽GaN基功率芯片的栅极G2通过三根125μm铝质内引 线连接到TO-220框架的基岛上,漏极用根125μm铝质内引线引出到TO-220框架的D极;大栅 宽GaN基功率芯片的源极用三根125μm铝质内引线和小铜基板相连接。
优选地,所述封装方法还包括塑封工艺以及冲筋,分离工艺;所述塑封工艺是把芯片所在的 TO-220框架放入注塑机,选用和TO-220框架相适配的塑封料,热熔后注入磨具;固定成型后取 出,放入热老化烘箱进行热老化,充分排出塑封体内的残留水汽;
所述是冲筋,分离工艺是通过分离成型设备,用TO-220FL的磨具把一整排的框架连接的铜 筋冲掉,再分离成单只成品。
与现有技术相比,本发明具有如下优点和技术效果:
1)Cascode的共源共栅结构是本领域常用的结构,本发明将横向结构,高耐压,耗尽型的 大栅宽GaN基功率芯片和垂直结构,低压、增强型的硅基功率MOS芯片结合,在垂直结构的硅基功率MOS芯片下方设置小铜基板,并用绝缘胶将GaN基功率芯片和小铜基板固定在TO220的 基岛上,从而使横向结构的大栅宽GaN基功率芯片和垂直结构的硅基功率MOS芯片的各个电极 可以按照共源共栅的方式连接起来,组合成实用性更广的增强型的GaN基功率器件。
2)本发明使用的原材料是本领域广泛使用的TO-220封装系列(TO-220F,TO-220FL等)、 硅基功率MOS芯片等封装原料,易于升级换代。
3)本发明器件的封装的工艺简单,重复性好,适用于高压大功率电子器件等应用。
附图说明
图1是本发明中的一种级联结构GaN基功率器件及其封装方法的俯视示意图。
图2a~图2e是本发明实例中一种级联结构GaN基功率器件及其封装制备过程示意图。
图3是具体实施例1中的一种级联结构GaN基功率器件的转移曲线图。
图中示出:硅基功率MOS芯片1,大栅宽GaN基功率芯片2,小铜基板3,TO‐220框架4,导电银浆5,绝缘胶6,38μm铜质内引线7,125μm铝质内引线8,无卤塑封料9。
具体实施方式
为更好地理解本发明,以下结合附图和实施例对本发明作进一步说明,但本发明的实施方式 不限于此,需指出的是,以下若有未特别详细说明之过程或工艺参数,均是本领域技术人员可参 照现有技术实现的。
参照图1,一种GaN基级联功率器件,包括:大栅宽GaN基功率芯片2、硅基功率MOS芯片 1、125μm铝质内引线8、38μm铜质内引线7、TO-220框架4、小铜基板3、无卤塑封料9、导 电银浆5和绝缘胶6;其中,TO-220框架4为T-220FL框架,包括大小为6.0mm×8.8mm的长方 形基岛、由基岛延伸出来的引脚S极、位于基岛左下方的引出到塑封体外的引脚G极、位于金属基岛右下方的引出到塑封体外的引脚D极。
硅基功率MOS芯片1是垂直结构的低压、增强型硅基功率MOS芯片,为N型的VDMOS结构,即垂直双扩散金属‐氧化物半导体场效应晶体管。硅基功率MOS芯片是垂直结构,硅基功率 MOS芯片的漏极D1设置在MOS芯片的下表面,源极S1和栅极G1设置在上表面。硅基功率MOS 芯片1的栅极、源极、漏极分别标记为G1、S1、D1。硅基功率MOS芯片的栅极G1的区域大小优 选为112μm×112μm,硅基功率MOS芯片的源极S1的区域大小优选为857×633μm,硅基功率 MOS芯片的漏极D1的区域大小优选为1160μm×820μm。
大栅宽GaN基功率芯片2是横向结构的高耐压、耗尽型GaN基功率芯片,大栅宽GaN基功 率芯片2的栅极、源极、漏极分别标记为G2、S2、D2。大栅宽GaN基功率芯片2的大小优选为 5770μm×1900μm,其中大栅宽GaN基功率芯片的栅极G2的区域大小优选为5700μm×250μm, 大栅宽GaN基功率芯片的源极S2的区域大小优选为5240μm×300μm,大栅宽GaN基功率芯片 的漏极D2的区域大小优选为5240μm×300μm。
小铜基板3的大小为1.5mm×2.5mm。
导电银浆5和绝缘胶6的厚度均优选为20μm-40μm。
硅基功率MOS芯片1和大栅宽GaN基功率芯片2设置在TO‐220框架2的基岛上,设置位 置为左右设置,硅基功率MOS芯片1在左侧,大栅宽GaN基功率芯片2在右侧。在电极方向上,TO‐220框架4的正面从左到右,首先为硅基功率MOS芯片的源极S1,源极S1下面是硅基功率 MOS芯片的栅极G1。硅基功率MOS芯片1的右边留出空隙后,设置大栅宽GaN基功率芯片2。大栅宽GaN基功率芯片2上,从左往右为大栅宽GaN基功率芯片的栅极G2、源极S2、漏极D2;本发明这种设置位置可以合理利用TO‐220框架4的基岛空间,而且有利于后续的布线压焊。
硅基功率MOS芯片1和小铜基板3之间的用导电银浆5固定,TO-220框架4的基岛和小铜 基板3之间用绝缘胶6固定,导电银浆5和绝缘胶6的厚度均为20μm-40μm。硅基功率MOS芯 片1通过导电银浆5与小铜基板3连接,小铜基板3通过绝缘胶6与TO-220框架4的基岛连接。 大栅宽GaN基功率芯片2通过绝缘胶6固定在TO-220框架4的基岛上。也就是大栅宽GaN基功 率芯片2下面是绝缘胶6,绝缘胶6下面是TO-220框架4的基岛。
硅基功率MOS芯片的栅极G1用一根38μm铜质内引线7连接到TO-220框架的源极S。硅基 功率MOS芯片的源极S1预计通过的电流将会达到12安培,一根125μm的铝线所能承载的电流是6安培左右,硅基功率MOS芯片的源极S1用三根125μm铝质内引线8连接到TO-220框架4 的基岛。硅基功率MOS芯片的漏极D1通过导电银浆5引出到小铜基板3。小铜基板3比硅基功 率MOS芯片2的面积要大,小铜基板3上有一部分的空位,再从小铜基板3的空位处引出三根 125μm铝质内引线8到大栅宽GaN基功率芯片2的源极S2。
大栅宽GaN基功率芯片2的栅极G2通过三根125μm铝质内引线8连接到TO-220框架4的 基岛上,大栅宽GaN基功率芯片2的漏极D2用4根125μm铝质内引线8引出到TO-220框架的漏极D极,作为GaN极级联功率器件的漏极。大栅宽GaN基功率芯片的源极S2用三根125μm 铝质内引线8和小铜基板3连接。
连接导线后,GaN基级联功率器件用无卤塑封料9对装载在铜质TO-220框架的半成品进行 注塑包裹。无卤塑封料9是长方体,将TO-220框架4的基岛和栅极G、源极S、漏极D包裹在内。
本发明通过引入Cascode方式,将横向结构,高耐压,耗尽型的大栅宽GaN基功率芯片和 垂直结构,低压、增强型的硅基功率MOS芯片结合,在垂直结构的硅基功率MOS芯片下方设置 小铜基板,并用绝缘胶将GaN基功率芯片和小铜基板固定在TO220的基岛上,从而使横向结构 的大栅宽GaN基功率芯片和垂直结构的硅基功率MOS芯片的各个电极可以按照共源共栅的方式 连接起来,组合成实用性更广的增强型的GaN基功率器件。
为了解决两个芯片的打线较多,若直接硅基功率MOS芯片直接从底部引出到TO‐220基岛会 引起的短路问题,本发明预先把硅基功率MOS芯片的D极通过导电银浆粘到小铜基板,且要求铜基板的大小比硅基功率MOS芯片的底部略大。
如图2a-图2e,一种GaN基级联功率器件的封装方法,包括如下步骤:
步骤一,划片工艺。通过划片机,根据划片槽宽度和芯片厚度选用宽度适合的刀片,将一整 片的大栅宽GaN基功率芯片2晶圆分割成分立的单颗芯片。如果芯片的厚度太大的话,则需要预先用磨片机减薄到适宜的厚度。如选用1mm长度的刀片对大栅宽GaN基功率芯片2进行切割。如 图2a所示。
步骤二,粘片工艺。先用绝缘胶6把小铜基板3和大栅宽GaN基功率芯片2分别固定到 TO-220FL框架4基岛的左右两边。如图2b所示。然后再改用导电银浆5,把硅基功率MOS芯片 1固定到小铜基板3上。硅基功率MOS芯片1在小铜基板3的位置应该偏左,右侧在小铜基板3 预留空间供后续布线压焊。如图2c所示。
步骤三,烘烤工序。完成粘片后放进烘箱。烘烤时间3小时,温度设定为175℃,烘箱内抽 真空后,充入氮气作为保护气体,确保烘箱内的氧气含量保持在100ppm以下。烘烤完成后,需 待箱内的温度降低至接近室温才能拿出来,防止芯片余温过高,过早取出后暴露在空气中将极易 被氧化。
步骤四,压焊工艺。烘烤完成后送入压焊机物料轨道。设定好压力、超声功率、压焊时间等 关键参数,然后让机器依照调试好的图像识别和布线方案进行打线。先打125μm铝质内引线8, 再打38μm铜质内引线7。具体连接方式如下。硅基功率MOS芯片1的栅极G1用一根38μm铜 质内引线7连接到TO-220框架4的S极。硅基功率MOS芯片1的源极S1用三根125μm铝质内 引线8连接到TO-220框架4的基岛。硅基功率MOS芯片的漏极D1通过导电银浆5引出到小铜基板3。小铜基板3比硅基功率MOS芯片2的面积要大,所以小铜基板3上有一部分的空位,再从 小铜基板3的空位处引出三根125μm铝质内引线8到大栅宽GaN基功率芯片2的源极S2。大栅 宽GaN基功率芯片2的栅极G2通过三根125μm铝质内引线8连接到TO-220框架4的基岛上, 漏极D2用4根125μm铝质内引线8引出到TO-220框架4的D极。大栅宽GaN基功率芯片2的 源极S2用三根125μm铝质内引线8和小铜基板3相连接。注意布局布线时候引线的避让,留有足够的安全距离,以免注塑应力后被冲击变形后发生短路。如图2d所示。
步骤五,压焊检测。通过测试设备,测试芯片推力,内引线拉力是否能达到要求的范围。再 拿样品做弹坑试验,把样品加入质量浓度15%的煮至80℃的NaOH溶液中,待大栅宽GaN基功率 芯片2表面的铝层被溶解后,取出冲洗干净,在电子显微镜下观察芯片内部是否有压伤后留下的 焊点最终试验数据表明,大栅宽GaN基功率芯片2的推力测试在200g-300g之间,铝线焊点的拉力测试大约在90到120之间,弹坑试验后电子显微镜显示,打线后大栅宽GaN基功率芯片2内 部无压伤痕迹。
步骤六,塑封工艺。注塑机清模后,把芯片所在的TO-220框架4放入注塑机,选用和TO-220 框架4相适配的塑封料,热熔后注入磨具。固定成型后取出,放入热老化烘箱进行6个小时的热 老化,充分排出塑封体内的残留水汽。如图2e所示。
本发明可以在生产流水线上将得到的一整排的多个TO-220框架通过冲筋,分离工艺分割成 一个个的独立的器件。冲筋,分离工艺是通过分离成型设备,用TO-220FL的磨具把一整排的框 架连接的铜筋冲掉,再分离成单只成品。
成品检测。通过X光分析仪,声扫分析仪,和镭射激光开封机对封装成果进行检测评估。X 光分析仪显示,塑封体内颜色分布均匀,无明显的空洞存在痕迹。声扫分析仪显示,无明显分层 现象。镭射开封机把塑封体去除后,电子显微镜观测正面和侧面,发现焊点没有虚焊,而且内引 线的弧高和间距正常,注塑应力可以通过。
对本实施例制备的级联结构GaN基功率器件的进行IV测试,得到图3的转移曲线。图3中 横坐标为电压,单位为V,纵坐标为电流,单位为A。从图中可见,本实施例制备的样品,阈值电压大于2V,饱和电流大于9A,实现了增强型的GaN基功率器件。
本发明封装成型的GaN基功率器件,通过Cascode结构将高压的耗尽型的大栅宽GaN基功率 芯片与低压的硅基MOSFET结合起来,组合成实用性更广的增强型的GaN晶体管。而且使用的原 材料是当下广泛使用的TO-220封装系列,硅基功率MOS芯片等封装原料,易于升级换代。同时,器件的封装的工艺简单,重复性好,适用于高压大功率电子器件等应用。
上述实施例不构成对本发明的任何限制,显然对于本领域的专业人员来说,在了解了本发明内 容和原理后,能够在不背离本发明的原理和范围的情况下,根据本发明的方法进行形式和细节上 的各种修正和改变,但是这些基于本发明的修正和改变仍在本发明的权利要求保护范围之内。
Claims (9)
1.一种GaN基级联功率器件,其特征在于,包括大栅宽GaN基功率芯片、硅基功率MOS芯片、TO-220框架、小铜基板、导电银浆和绝缘胶;
硅基功率MOS芯片和大栅宽GaN基功率芯片间隔设置在TO-220框架的基岛上,设置位置为左右设置,硅基功率MOS芯片左侧,大栅宽GaN基功率芯片在右侧;所述硅基功率MOS芯片是垂直结构的低压、增强型硅基功率MOS芯片;所述大栅宽GaN基功率芯片是横向结构的高耐压、耗尽型GaN基功率芯片;
所述硅基功率MOS芯片通过导电银浆与小铜基板连接,小铜基板通过绝缘胶与TO-220框架的基岛连接;大栅宽GaN基功率芯片通过绝缘胶固定在TO-220框架的基岛上;
硅基功率MOS芯片的栅极用一根38μm铜质内引线连接到TO-220框架的源极;硅基功率MOS芯片的源极用三根125μm铝质内引线连接到TO-220框架的基岛;硅基功率MOS芯片的漏极通过导电银浆引出到小铜基板;小铜基板的面积大于硅基功率MOS芯片,小铜基板上有一部分的空位,从小铜基板的空位处引出三根125μm铝质内引线到大栅宽GaN基功率芯片的源极;
大栅宽GaN基功率芯片的栅极通过三根125μm铝质内引线连接到TO-220框架的基岛上,大栅宽GaN基功率芯片的漏极用4根125μm铝质内引线引出到TO-220框架的漏极,作为GaN基级联功率器件的漏极;
所述硅基功率MOS芯片为N型的VDMOS结构。
2.根据权利要求1所述的GaN基级联功率器件,其特征在于,所述GaN基级联功率器件用无卤塑封料对装载在铜质TO-220框架进行注塑包裹;所述无卤塑封料是长方体,将TO-220框架的基岛和栅极、源极、漏极包裹在内。
3.根据权利要求1所述的GaN基级联功率器件,其特征在于,所述TO-220框架为T-220FL框架,包括大小为6.0mm×8.8mm的长方形基岛、由基岛延伸出来的引脚S极、位于基岛左下方的引出到塑封体外的引脚G极、位于金属基岛右下方的引出到塑封体外的引脚D极。
4.根据权利要求1所述的GaN基级联功率器件,其特征在于,所述硅基功率MOS芯片的栅极的区域大小为112μm×112μm,源极的区域大小为857×633μm,漏极的区域大小为1160μm×820μm。
5.根据权利要求1所述的GaN基级联功率器件,其特征在于,所述大栅宽GaN基功率芯片的大小为5770μm×1900μm,其中大栅宽GaN基功率芯片的栅极的区域大小为5700μm×250μm,源极的区域大小为5240μm×300μm,漏极的区域大小为5240μm×300μm。
6.根据权利要求1所述的GaN基级联功率器件,其特征在于,所述小铜基板的大小为1.5mm×2.5mm。
7.根据权利要求1所述的GaN基级联功率器件,其特征在于,所述导电银浆和绝缘胶的厚度均为20μm-40μm。
8.权利要求1-7任一项所述的GaN基级联功率器件的封装方法,其特征在于包括如下步骤:
1)划片工艺:通过划片机,将一整片的大栅宽GaN基功率芯片晶圆分割成分立的单颗芯片;
2)粘片工艺:先用绝缘胶把小铜基板和大栅宽GaN基功率芯片分别固定到TO-220FL框架基岛的左右两边;然后再改用导电银浆,把硅基功率MOS芯片固定到小铜基板上;
3)烘烤工序:完成粘片后放进烘箱烘烤,烘箱内抽真空后,充入氮气作为保护气体,确保烘箱内的氧气含量保持在100ppm以下;烘烤完成后,待烘箱内的温度降低至室温,拿出芯片;
4)压焊工艺:硅基功率MOS芯片的栅极用一根38μm铜质内引线连接到TO-220框架的源极,硅基功率MOS芯片的源极用三根125μm铝质内引线连接到TO-220框架的基岛;硅基功率MOS芯片的漏极通过导电银浆引出到小铜基板;从小铜基板的空位处引出三根125μm铝质内引线到大栅宽GaN基功率芯片的源极S2;大栅宽GaN基功率芯片的栅极G2通过三根125μm铝质内引线连接到TO-220框架的基岛上,漏极用根125μm铝质内引线引出到TO-220框架的D极;大栅宽GaN基功率芯片的源极用三根125μm铝质内引线和小铜基板相连接。
9.根据权利要求8所述的GaN基级联功率器件的封装方法,其特征在于,所述封装方法还包括塑封工艺以及冲筋,分离工艺;所述塑封工艺是把芯片所在的TO-220框架放入注塑机,选用和TO-220框架相适配的塑封料,热熔后注入磨具;固定成型后取出,放入热老化烘箱进行热老化,充分排出塑封体内的残留水汽;
所述的冲筋,分离工艺是通过分离成型设备,用TO-220FL的磨具把一整排的框架连接的铜筋冲掉,再分离成单只成品。
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