CN105702638A - 具有减小的形状因子和增强的热耗散的集成功率组件 - Google Patents

具有减小的形状因子和增强的热耗散的集成功率组件 Download PDF

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CN105702638A
CN105702638A CN201510918214.1A CN201510918214A CN105702638A CN 105702638 A CN105702638 A CN 105702638A CN 201510918214 A CN201510918214 A CN 201510918214A CN 105702638 A CN105702638 A CN 105702638A
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semiconductor die
transistor
power
power assembly
lead frame
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曹应山
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Infineon Technologies North America Corp
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Infineon Technologies North America Corp
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Abstract

提供了一种具有减小的形状因子和增强的热耗散的集成功率组件。集成功率组件包括：印刷电路板；第一引线框，其具有在所述印刷电路板上的局部蚀刻段和非蚀刻段；第一半导体裸片，其被配置用于附接至所述第一引线框的所述局部蚀刻段；第二引线框，其具有无腿导电夹；以及第二半导体裸片，其定位在所述第一半导体裸片上方并且通过所述无腿导电夹被耦合至所述第一半导体裸片。

Description

具有减小的形状因子和增强的热耗散的集成功率组件
本申请要求于2014年12月10日提交的序列号为62/090,202的题为“DualGaugeforStackedPowerDevices”的临时专利申请的权益和优先权。在该临时申请中公开的内容由此通过引用的方式全部合并在本申请中。
技术领域
本公开的实施例涉及具有减小的形状因子和增强的热耗散的集成功率组件。
背景技术
诸如降压转换器等的功率转换器经常被用于将高DC电压转换成低DC电压。功率转换器典型地包括以半桥配置连接并且由驱动器集成电路(IC)控制的高压侧开关和低压侧开关。为了改进形状因子、电和热性能以及制造成本，经常期望将功率转换器电路的部件(诸如基于半桥的DC-DC转换器或电压转换器)集成到功率半导体封装中。
在传统的功率半导体封装中，独立的半导体裸片被并排布置并且通过它们各自的导电夹耦合到共享的支撑表面，诸如印刷电路板(PCB)。然而，通过导电夹的半导体裸片和PCB之间的布线可能不期望地增大电阻。此外，横向布置的独立封装的半导体裸片的形状因子需要在PCB上预留出足够大的区域。此外，功率器件在操作期间经常生成大量热，如果热不能充分地从功率器件中耗散，这可能导致它们的温度升高超过适当的温度范围。
因此，在现有技术中，需要提供一种具有减小的形状因子以及增强的热耗散的集成功率组件。
发明内容
本公开涉及一种基本上如关于至少一个附图所示和/或所述的并且如在权利要求中所述的具有减小的形状因子以及增强的热耗散的集成功率组件。
附图说明
图1A示出根据本申请的一个实施方式的功率转换器的示例性电路图。
图1B示出根据本申请的一个实施方式的复合开关的示例性电路图。
图2A示出根据本申请的一个实施方式的功率开关级的示例性集成功率组件的截面图。
图2B示出根据本申请的一个实施方式的功率开关级的示例性集成功率组件的截面图。
图3示出根据本申请的一个实施方式的三相逆变器的立体图。
图4示出根据本申请的一个实施方式的复合开关的集成功率组件的截面图。
具体实施方式
下面的说明包含属于本公开的实施方式的特定信息。本公开的附图和它们的详细说明涉及仅示例性的实施方式。除非相反说明，图中的相似和对应的元件可用相似或对应的附图标记指示。此外，本申请的附图和图示一般不是成比例的并且不旨在与实际的相对尺寸对应。
图1A示出根据本申请的实施方式的示例性功率转换电路的电路示意图。如图1A所示，功率转换电路100包括驱动器集成电路(IC)110和具有高压侧开关120和低压侧开关130的功率开关级102。驱动器IC110被配置成提供作为栅极驱动信号的高压侧驱动信号HO和低压侧驱动信号LO，以驱动功率开关级102的对应的高压侧开关120和低压侧开关130。在功率开关级102中，高压侧开关120和低压侧开关130被耦合在正输入端子VIN(+)和负输入端子VIN(-)之间，作为输出节点的开关节点140位于高压侧开关120和低压侧开关130之间。
如图1A所示，高压侧开关120(例如Q1)包括具有漏极122(例如，D1)、源极124(例如S1)和栅极126(例如G1)的控制晶体管。低压侧开关130(例如Q2)包括具有漏极132(例如，D2)、源极134(例如Ss)和栅极136(例如G2)的同步晶体管(下面称为“sync”)。高压侧开关120的漏极122被耦合至正输入端子VIN(+)，而高压侧开关120的源极124被耦合至开关节点140。高压侧开关120的栅极126被耦合到驱动器IC110，其将高压侧驱动信号HO提供至栅极126。如图1A所示，低压侧开关130的漏极132被耦合至开关节点140，而低压侧开关130的源极134被耦合至负输入端子VIN(-)。低压侧开关130的栅极136被耦合到驱动器IC110，其将低压侧驱动信号LO提供至栅极136。
在一实施方式中，高压侧开关120和低压侧开关130中的至少一个包括IV族半导体器件，诸如硅金属氧化物半导体场效应晶体管(MOSFET)。在另一实施方式中，高压侧开关120和低压侧开关130中的至少一个包括III-V族半导体器件，诸如氮化镓(GaN)器件，可以是GaN高电子迁移率晶体管(HEMT)。在另一实施方式中，高压侧开关120和低压侧开关130可以是其他任意适当的半导体器件，例如双极结型晶体管(BJT)和绝缘栅双极型晶体管(IGBT)。
在一实施方式中，高压侧开关120和低压侧开关130(也被分别成为功率开关120和功率开关130)可以均包括III-V族半导体器件，诸如III-氮化物晶体管。通过在功率开关级102中包括至少一个III-氮化物晶体管，功率转换电路100可以开发高击穿场、高饱和速度、和由III-氮化物材料提供的二维电子气体(2DEG)。可能期望将至少一个III-氮化物晶体管耦合至IV族晶体管(例如硅晶体管)。例如，可能期望针对至少一个III-氮化物晶体管在功率转换电路100中操作为增强型器件。这可以通过将至少一个III-氮化物晶体管(例如耗尽型GaN晶体管)与IV族晶体管共源共栅(cascode)地耦合，以生成增强型复合开关，诸如图1B中的增强型复合开关142。
现在参考图1B，图1B示出根据本申请的一个实施方式的具有与IV族晶体管共源共栅地耦合的III-V族晶体管的复合开关的示例性电路图。增强型复合开关142包括复合源极S1、复合栅极G1和复合漏极D1。增强型复合开关142可以对应于图1A中的高压侧开关120和低压侧开关130中的至少一个。例如，当一个增强型复合开关142可以用作为图1A中的功率转换电路100中的高压侧开关120时，另一增强型复合开关142可以用作为低压侧开关130。由此，增强型复合开关142的复合源极S1、复合栅极G1和复合漏极D1可以分别对应于高压侧开关120的源极124(例如S1)、栅极126(例如G1)和漏极122(例如，D1)。增强型复合开关142的复合源极S1、复合栅极G1和复合漏极D1可以分别对应于低压侧开关130的源极134(例如S2)、栅极136(例如G2)和漏极132(例如，D2)。
如图1B所示，增强型复合开关142包括与IV族晶体管170共源共栅地耦合的III-V族晶体管160。例如，III-V族晶体管160可以是III-氮化物异质结场效应晶体管(HFET)，诸如GaNHEMT。在本实施方式中，III-V族晶体管160是耗尽型晶体管，诸如耗尽型GaN晶体管。IV族晶体管170可以是硅基功率半导体器件，诸如硅功率MOSFET。在本实施方式中，IV族晶体管170是增强型晶体管，诸如增强型硅晶体管。
如图1B所示，III-V族晶体管160(例如Q3)包括漏极162(例如，D3)、源极164(例如S3)和栅极166(例如G3)。IV族晶体管170(例如Q4)包括漏极172(例如，D4)、源极174(例如S4)和栅极176(例如G4)。III-V族晶体管160的漏极162被耦合至复合漏极D1，而III-V族晶体管160的源极164被耦合至开关节点180。III-V族晶体管160的栅极166被耦合至IV族晶体管170的源极174。如图1B所示，IV族晶体管170的漏极172被耦合至开关节点180，而IV族晶体管170的源极174被耦合至复合源极S1。IV族晶体管170的栅极176被耦合至复合栅极G1。
在增强型复合开关142中，IV族晶体管170的漏极172被连接至III-V族晶体管的源极164，使得两个器件在反向电压条件下处于阻断模式。如所配置的，IV族晶体管170可以是低压器件，而III-V族晶体管160可以是高压器件。在增强型复合开关142中，III-V族晶体管160的栅极166被连接至IV族晶体管170的源极174。因此，III-V族晶体管160可以缺失在IV族晶体管170的栅极176上的偏置电压而是关断的，使得增强型复合开关142为常断器件。
根据本申请的实施方式，III-V族晶体管160和IV族晶体管170可以在集成功率组件中的印刷电路板(PCB)上耦合在一起。根据本申请的实施方式，IV族晶体管170位于定位在PCB上的IV族半导体裸片上，III-V族晶体管160位于定位在IV族半导体裸片上的III-V族半导体裸片上。III-V族晶体管160可以被耦合在集成功率组件中的IV族晶体管170，这可以提供减小的形状因子和增强的热耗散。
现在参考图2A，图2A示出根据本申请的一个实施方式的功率开关级的示例性集成功率组件的截面图。如图2A所示，集成功率组件202包括具有功率开关220的半导体裸片204、具有功率开关230的半导体裸片206、具有在基底290上的非蚀刻段250a、250d和局部蚀刻段250b、250c的引线框250、以及具有局部蚀刻导电夹252a和无腿导电夹250b的引线框252。此外，集成功率组件202可以可选地包括模制化合物292。在本实施方式中，功率开关220和230可以分别对应于在图1A中的功率转换电路100中的高压侧开关120和低压侧开关130，并且可以这样连接。
如图2A所示，半导体裸片204包括功率开关220。在一实施方式中，功率开关220可以对应于图1A中的功率转换电路100中的高压侧开关120。功率开关220包括控制晶体管，控制晶体管具有定位在半导体裸片204的顶表面上的功率电极222(例如，漏极电极)以及定位在半导体裸片204的底表面上的功率电极224(例如，源极电极)和控制电极226(例如栅极电极)。功率开关220的控制电极226(例如栅极电极)被电和机械地耦合至局部蚀刻导电夹252a的顶表面，局部蚀刻导电夹252a进而通过引线框250的非蚀刻段250a电耦合至基底290。功率开关220的功率电极224(例如源极电极)被电和机械地耦合至无腿导电夹252b的顶表面，无腿导电夹252b进而通过引线框250的非蚀刻段250d电耦合至基底290。如图2A所示，功率开关220的功率电极222(例如漏极电极)被露出在集成功率组件202的顶表面上。功率电极222可以包括可焊接的前金属，诸如钛、铜、镍或银。由于模制化合物292不覆盖功率电极222的顶表面，功率开关220被配置成固定(焊接)至功率总线，功率总线可以用作使由集成功率组件202在操作期间发出的热耗散的热沉。
如图2A所示，引线框252包括局部蚀刻导电夹252a和无腿导电夹252b。局部蚀刻导电夹252a被电和机械耦合至功率开关220的控制电极226，而无腿导电夹252b被电和机械耦合至功率开关220的功率电极224。局部蚀刻导电夹252a和无腿导电夹252b具有实质上共面的顶表面，并且提供用于半导体裸片204的结构支撑。如图2A所示，局部蚀刻导电夹252a具有非蚀刻部分和局部蚀刻部分，其中非蚀刻部分保持引线框252的整个厚度，局部蚀刻部分具有的厚度是引线框252的整个厚度的一部分。局部蚀刻导电夹252a被配置成在半导体裸片206和引线框252之间提供间隙，使得半导体裸片206上的控制电极226不被电短路至半导体裸片206。无腿导电夹252b与局部蚀刻导电夹252a物理地分离，并且具有大体平坦的主体，该平坦的主体具有实质上均匀的厚度，该厚度是引线框252的整个厚度。
在本实施方式中，局部蚀刻导电夹252a和无腿导电夹252b由相同的材料制成并且具有实质上均匀的成分。在另一实施方式中，局部蚀刻导电夹252a和无腿导电夹252b由不同的材料制成并且具有不同的成分。在本实施方式中，引线框252的局部蚀刻导电夹252a和无腿导电夹252b包括铜。在另一实施方式中，局部蚀刻导电夹252a和无腿导电夹252b可以包括其他适当的导电材料，诸如铝或钨。
如图2A所示，半导体裸片206包括功率开关230。在一实施方式中，功率开关230可以与图1A中的功率转换电路100中的低压侧开关130对应。功率开关230包括同步晶体管，具有位于半导体裸片206的顶表面上的功率电极232(例如，漏极电极)和位于半导体裸片206的底表面上的功率电极234(例如，源极电极)和控制电极236(例如，栅极电极)。
如图2A所示，半导体裸片204被定位在位于半导体裸片206上方的引线框252上。功率开关220的功率电极224(例如源极电极)通过无腿导电夹252b被电耦合至功率开关230的功率电极232(例如，漏极电极)，无腿导电夹252b可以对应于图1A中的开关节点140。功率开关230的控制电极236(例如，栅极电极)和功率电极234(例如，源极电极)分别被电和机械耦合到位于基底290上的引线框250的局部蚀刻段250b和250c。在一实施方式中，基底290可以是电路板，例如印刷电路板(PCB)，或任何其他适当的基底。
如图2A所示，引线框250包括非蚀刻段250a、250d和局部蚀刻段250b、250c。非蚀刻段250a、250d和局部蚀刻段250b、250c是引线框250的不同部分，其中非蚀刻段250a、250d保持引线框250的整个厚度，局部蚀刻段250b、250c被蚀刻，由此具有引线框250的整个厚度的一部分(例如，非蚀刻段250a的厚度的一半或四分之一)。非蚀刻段250a、250d和局部蚀刻段250b、250c被物理地彼此分离。在本实施方式中，非蚀刻段250a、250d和局部蚀刻段250b、250c由相同的材料制成并且具有实质上均匀的成分。在本实施方式中，非蚀刻段250a、250d和局部蚀刻段250b、250c可以包括金属，诸如铜、铝或钨；金属合金，三金属或其它导电材料。在另一实施方式中，非蚀刻段250a、250d和局部蚀刻段250b、250c可由不同的材料制成并且具有不同的成分。在本实施方式中，局部蚀刻段250b、250c具有实质上均匀的厚度，该厚度是引线框250的整个厚度的一部分。在另一实施方式中，局部蚀刻段250b、250c可以具有不同的厚度，
如图2A所示，由于半导体裸片206位于引线框250的与非蚀刻段相对的局部蚀刻段上，集成功率组件202中的半导体裸片206的整体高度可以被减小，使得可以去除在传统的导电夹中使用的腿部。在本实施方式中，无腿导电夹252b具有大体平坦的主体，该平坦的主体不具有腿部。与具有被附接至非蚀刻引线段的半导体裸片和具有腿部的导电夹的传统功率半导体封装相比，本申请的实施方式使用引线框250的非蚀刻段250d和局部蚀刻段250b、250c，使得能够使用无腿导电夹252b将半导体裸片206耦合至基底290。结果，可以减小集成功率组件202的整体高度，这进而减小集成功率组件202的形状因子。在一个实施方式中，半导体裸片204和206可以均具有70μm(即，70*10-6m)的或小于70μm的厚度，集成功率组件202可以具有0.8mm(即，0.8*10-3m)或小于0.8mm的整体高度。此外，通过采用无腿导电夹252b和配置成附接至局部蚀刻段250b、250c的半导体裸片206，无腿导电夹252b的厚度可以被调节成改进高电流和电压处理能力，以在不显著影响集成功率组件202的整体高度的前提下满足特定实施方式的要求。与具有并排布置并且通过它们各自的导电夹耦合至基底290的独立半导体裸片的传统功率半导体封装相比，通过将半导体裸片204堆叠在位于基底上的半导体裸片206之上，集成功率组件202可以有利地具有减小的覆盖区，由此减小集成功率组件202的形状因子。
在一实施方式中，具有呈半桥连接的功率开关220和230的集成功率组件202可以对应于可以用于驱动例如马达的三相逆变器或更一般的多项逆变器的一相。例如，在集成功率组件202中，功率开关220(例如高压侧开关)和功率开关230(例如低压侧开关)被以半桥连接，其可以利用位于功率开关220和230之间的作为输出端子(例如图1A中的开关节点140)的引线框252的无腿导电夹252b被耦合在高压侧功率总线(例如图1A中的正输入端子VIN(+))和低压侧功率总线(例如图1A中的负输入端子VIN(-))之间。
现在参考图2B，图2B示出根据本申请的一个实施方式的示例性集成功率组件的截面图。相同的附图标记表示图2A中的相同的特征，图2B中的集成功率组件202包括具有功率开关220的半导体裸片204、具有功率开关230的半导体裸片206、具有在基底290上的非蚀刻段250a、250b和局部蚀刻段250b、250c上的引线框250、具有局部蚀刻导电夹252a和无腿导电夹252b的引线框252、以及模制化合物292。此外，图2B中的集成功率组件202包括引线框250中的非蚀刻段250e、引线框252中的非蚀刻段252c、和局部蚀刻导电夹254，其中功率开关220的功率电极222(例如，漏极电极)通过局部蚀刻导电夹254、非蚀刻段252c和非蚀刻段250e被耦合至基底290。
如图2B所示，模制化合物292覆盖半导体裸片204、半导体裸片206、具有非蚀刻段250a、250d、250e和局部蚀刻段250b、250c的引线框250、以及具有局部蚀刻导电夹252a、无腿导电夹252b和非蚀刻段252c的引线框252。局部蚀刻导电夹254被电和机械耦合至功率开关220的功率电极222(例如，漏极电极)，并且在集成功率组件202的顶表面处露出。这样，可以使用局部蚀刻导电夹254作为功率总线，以用于将高压侧功率总线电压供给至功率开关220。此外，由于局部蚀刻导电夹254的大的顶表面露出(即，不被模制化合物292覆盖)，所以局部蚀刻导电夹254可以用作热沉，以通过将热例如直接辐射至环境空气来提供增强的热耗散。在另一实施方式中，模制化合物292可以覆盖并且完全埋住半导体裸片204、206、引线框250、252和局部蚀刻导电夹254。
现在参考图3，图3示出根据本申请的实施方式的三相逆变器的立体图。如图3所示，三相逆变器300包括形成在基底390上并且耦合至功率总线394的集成功率组件302u、302v和302w。在一个实施方式中，集成功率组件302u、302v和302w可以分别是可以用于驱动例如马达的三相逆变器300的U相、V相和W相。图3中的集成功率组件302u、302v和302w中的每个均可以与图2A中的集成功率组件202对应。例如，集成功率组件302u、302v和302w中的每个可以包括在集成功率组件(例如图2A中的集成功率组件202)中以半桥连接的高压侧开关(例如，图2A中的功率开关220)和低压侧开关(例如，图2A中的功率开关230)。因此，集成功率组件302u、302v和302w中的每个包括露出在其顶表面处的功率电极，例如图2A中的功率电极222(例如，漏极电极)。功率总线394被配置成固定至集成功率组件302u、302v和302w中的每个中的露出的功率电极(在图3中未明显示出)，并且向其提供高压侧总线电压。此外，由于功率总线394可以用作用于集成功率组件302u、302v和302w的共同热沉，以通过将热例如直接辐射至环境空气来提高热耗散。
现在参考图4，图4示出根据本申请的一个实施方式的复合开关的集成功率组件的截面图。如图4所示，集成功率组件442可以包括复合开关，诸如图1B中的增强型复合开关142，其可以对应于图1A中的高压侧开关120和低压侧开关130中的至少一个。例如，在一个集成功率组件442可以用作高压侧开关120时，另一个集成功率组件442可以用作功率转换电路100中的低压侧开关130。
如图4所示，集成功率组件442包括具有功率开关460的半导体裸片468、具有功率开关470的半导体裸片478、具有在基底490上的非蚀刻段450a、450d、450e和局部蚀刻段450b、450c的引线框450、具有非蚀刻段452a、452c和无腿导电夹452b的引线框452、以及具有局部蚀刻导电夹454a、454b的引线框454。在本实施方式中，功率开关460、470可以分别对应于图1B中所示的III-V族晶体管160和IV族晶体管170，并且可以这样连接。
如图4所示，半导体裸片468包括功率开关460。例如，功率开关460可以是III-氮化物HFET，诸如GaNHEMT。在本实施方式中，功率开关460是耗尽型晶体管，诸如耗尽型GaN晶体管。功率开关470可以是硅基功率半导体器件，诸如硅功率MOSFET。在本实施方式中，功率开关470是增强型晶体管，诸如增强型硅晶体管。
如图4所示，具有功率开关460的半导体裸片468定位于在具有功率开关470的半导体裸片478上方的引线框452的无腿导电夹452b上。功率开关460包括位于半导体裸片468的顶表面上的功率电极462(例如漏极电极)和控制电极466(例如栅极电极)和位于半导体裸片468的底表面上的功率电极464(例如源极电极)。功率开关460的控制电极466(例如栅极电极)通过引线框454的局部蚀刻导电夹454a、引线框452的非蚀刻段452a、以及引线框450的非蚀刻段450a被电耦合至基底490。功率开关460的功率电极462(例如漏极电极)通过引线框454的局部蚀刻导电夹454b、引线框452的非蚀刻段452c、以及引线框450的非蚀刻段450e被电耦合至基底490。功率开关460的功率电极464(例如，源极电极)被电和机械地耦合至引线框452的无腿导电夹452b的顶表面。
如图4所示，引线框452包括非蚀刻段452a、452c和无腿导电夹452b。非蚀刻段452a被耦合在局部蚀刻导电夹454a和非蚀刻段450a之间。非蚀刻段452c被耦合在局部蚀刻导电夹454b和非蚀刻段450e之间。无腿导电夹452b被电和机械地耦合在功率开关460的功率电极464和功率开关470的功率电极472之间。非蚀刻段452a、452c和无腿导电夹452b具有实质上共面的顶表面。无腿导电夹452b为半导体裸片468提供结构支撑。无腿导电夹452b与非蚀刻段452a、452c物理地分离，并且具有实质上的平坦的主体，该平坦的主体具有大体均匀的厚度，该厚度是引线框452的整个厚度。
如图4所示，局部蚀刻导电夹454a、454b均具有非蚀刻部和局部蚀刻部，其中非蚀刻部保持引线框454的整个厚度，并且局部蚀刻部具有作为引线框454的整个厚度的一部分的厚度。局部蚀刻导电夹454a与局部蚀刻导电夹454b物理地分离，其中，局部蚀刻导电夹454a、454b被分别耦合至功率开关460的控制电极466和功率电极462。如图4所示，局部蚀刻导电夹454a、454b均包括露出的顶表面。由于模制化合物492不覆盖局部蚀刻导电夹454a、454b的顶表面，局部蚀刻导电夹454a、454b的露出的大的顶表面可以均用作热沉，以使从集成功率组件442在操作期间产生的热耗散。在另一实施方式中，模制化合物492可以覆盖并且完全埋住半导体裸片468、478和引线框450、452、454。
在本实施方式中，局部蚀刻导电夹454a、454b是由相同材料制成，并且具有实质上均匀的成分。在另一实施方式中，局部蚀刻导电夹454a、454b可以由不同的材料制成，并且具有不同的成分。在本实施方式中，引线框454的局部蚀刻导电夹454a、454b包括铜。在另一实施方式中，局部蚀刻导电夹454a、454b可以包括其他适当的导电材料，诸如铝或钨。在本实施方式中，引线框454的局部蚀刻导电夹454a、454b由与引线框452的非蚀刻段452a、452c和无腿导电夹452b相同的材料制成。在另一实施方式中，引线框454的局部蚀刻导电夹454a、454b和引线框452的非蚀刻段452a、452c和无腿导电夹452b由不同的材料制成，并且具有不同的成分。
如图4所示，半导体裸片478包括功率开关470。例如，功率开关470包括位于半导体裸片478的顶表面的功率电极472(例如，漏极电极)和位于半导体裸片478的底表面上的控制电极476(例如，栅极电极)和功率电极474(例如，源极电极)。功率开关470的功率电极472(例如，漏极电极)被电和机械地耦合至无腿导电夹452b的底表面，其被电和机械地耦合至在其顶表面上的功率开关460的功率电极464(例如源极电极)。可与图1B中的开关节点180对应的无腿导电夹452b通过引线框450的非蚀刻段450d被电耦合至基底490。功率开关470的控制电极476(例如，栅极电极)和功率电极474(例如，源极电极)被分别电和机械地耦合至定位在基底490上的引线框450的局部蚀刻段450b、450c。
如图4所示，引线框450包括位于基底490上的非蚀刻段450a、450d、450e和局部蚀刻段450b、450c。非蚀刻段450a、450d、450e和局部蚀刻段450b、450c是引线框450的不同部分，其中非蚀刻段450a、450d、450e保持引线框450的整个厚度，局部蚀刻段450b、450c被蚀刻，由此具有引线框450的整个厚度的一部分(例如，非蚀刻段450a的厚度的一半或四分之一)。非蚀刻段450a、450d、450e和局部蚀刻段450b、450c彼此物理地分离。在本实施方式中，非蚀刻段450a、450d、450e和局部蚀刻段450b、450c由相同的材料制成，并且具有实质上均匀的成分。在本实施方式中，引线框450的非蚀刻段450a、450d、450e和局部蚀刻段450b、450c可以包括金属，诸如铜、铝、或钨；金属合金，三金属或其它导电材料。在另一实施方式中，非蚀刻段450a、450d、450e和局部蚀刻段450b、450c可由不同的材料制成并且具有不同的成分。在本实施方式中，局部蚀刻段450b、450c具有实质上均匀的厚度，该厚度是引线框450的整个厚度的一部分。在另一实施方式中，局部蚀刻段450b、450c可以具有不同的厚度。
如图4所示，由于半导体裸片478位于引线框450的与非蚀刻段相对的局部蚀刻段上，集成功率组件442中的半导体裸片478的整体高度可以被减小，使得可以去除在传统的导电夹中使用的腿部。在本实施方式中，无腿导电夹452b具有大体平坦的主体，其不具有腿部。与具有被附接至非蚀刻引线段的半导体裸片和具有腿部的导电夹的传统功率半导体封装相比，本申请的实施方式使用引线框450的非蚀刻段450d和局部蚀刻段450b、450c，使得能够使用无腿导电夹452b将半导体裸片478耦合至基底490。结果，可以减小集成功率组件442的整体高度，这进而减小集成功率组件442的形状因子。此外，通过采用无腿导电夹452b和配置成附接至局部蚀刻段450b、450c的半导体裸片478，无腿导电夹452b的厚度可以被调节成改进高电流和电压处理能力，以在不显著影响集成功率组件442的整体高度的前提下满足特定实施方式的要求。与具有并排布置并且通过它们各自的导电夹耦合至基底的独立半导体裸片的传统功率半导体封装相比，通过将半导体裸片268堆叠在位于基底490上的半导体裸片478上方，集成功率组件442可以有利地具有减小的覆盖区，由此减小集成功率组件442的形状因子。
在一实施方式中，功率开关460与集成功率组件442中的功率开关470共源共栅，以形成增强型复合开关，其中功率开关460的控制电极466(例如栅极电极)通过基底490上的导电迹线(图4中未明显示出)被电耦合至功率开关470的功率电极474(例如源极电极)。集成功率组件442可以提供减小的形状因子和增强的热耗散，同时可以实质上避免寄生性电感、热阻抗和装配成本的增大。
从上面的说明明显的是，可以在不背离这些构思的范围的前提下使用各种技术来实施本申请所述的构思。此外，尽管特别参考特定实施方式说明了构思，但是本领域的普通技术人员应当认识到在不背离这些构思的范围的前提下可以对形式和细节进行变化。这样，所述的实施方式应当认为在所有的方面都是图示性的而不是限制性。应当理解的是，本申请不限于上面所述的具体实施方式，而是可以在不背离本公开的范围的前提下能够进行多种重新布置、修改和替换。

Claims (20)

1.一种集成功率组件，包括：
印刷电路板；
第一引线框，具有在所述印刷电路板上的局部蚀刻段和非蚀刻段；
第一半导体裸片，被配置用于附接至所述第一引线框的所述局部蚀刻段；
第二引线框，具有无腿导电夹；
第二半导体裸片，定位在所述第一半导体裸片上方并且通过所述无腿导电夹被耦合至所述第一半导体裸片。
2.根据权利要求1所述的集成功率组件，其中所述第二半导体裸片通过所述第二引线框的局部蚀刻导电夹和所述第一引线框的至少一个所述非蚀刻段被耦合至所述印刷电路板。
3.根据权利要求1所述的集成功率组件，其中所述第一半导体裸片上的漏极电极通过所述无腿导电夹被耦合至所述第二半导体裸片上的源极电极。
4.根据权利要求1所述的集成功率组件，其中所述第一半导体裸片包括第一功率晶体管，所述第一功率晶体管具有在所述第一半导体裸片的底表面处的源极电极和栅极电极以及在所述第一半导体裸片的顶表面上的漏极电极。
5.根据权利要求1所述的集成功率组件，其中所述第二半导体裸片包括第二功率晶体管，所述第二功率晶体管具有在所述第二半导体裸片的底表面处的源极电极和栅极电极以及在所述第二半导体裸片的顶表面上的漏极电极。
6.根据权利要求1所述的集成功率组件，其中所述第二半导体裸片包括第二功率晶体管，所述第二功率晶体管具有在所述第二半导体裸片的底表面处的源极电极以及在所述第二半导体裸片的顶表面上的漏极电极和栅极电极。
7.根据权利要求1所述的集成功率组件，其中所述第一半导体裸片包括第一功率晶体管，并且所述第二半导体裸片包括第二功率晶体管。
8.根据权利要求7所述的集成功率组件，其中所述第一功率晶体管和所述第二功率晶体管中的至少一个包括硅。
9.根据权利要求7所述的集成功率组件，其中所述第一功率晶体管和所述第二功率晶体管中的至少一个包括氮化镓(GaN)。
10.根据权利要求1所述的集成功率组件，其中所述第一半导体裸片包括同步晶体管，并且所述第二半导体裸片包括以半桥耦合至所述同步晶体管的控制晶体管。
11.根据权利要求1所述的集成功率组件，其中所述第一半导体裸片包括IV族晶体管，并且所述第二半导体裸片包括与所述IV族晶体管共源共栅的III-V族晶体管。
12.一种集成功率组件，包括：
印刷电路板；
第一引线框，具有在所述印刷电路板上的局部蚀刻段和非蚀刻段；
第一半导体裸片，具有被配置用于附接至所述第一引线框的所述局部蚀刻段的第一功率开关；
第二引线框，具有无腿导电夹；
第二半导体裸片，具有定位在所述第一半导体裸片上方的第二功率开关，其中所述第二功率开关的源极电极通过所述无腿导电夹被耦合至所述第一功率开关的漏极电极。
13.根据权利要求12所述的集成功率组件，其中所述第二半导体裸片通过所述第二引线框的局部蚀刻导电夹和所述第一引线框的至少一个所述非蚀刻段被耦合至所述印刷电路板。
14.根据权利要求12所述的集成功率组件，其中所述第一功率开关和所述第二功率开关中的至少一个包括硅。
15.根据权利要求12所述的集成功率组件，其中所述第一功率开关和所述第二功率开关中的至少一个包括氮化镓(GaN)。
16.根据权利要求12所述的集成功率组件，所述第一功率开关包括同步晶体管，并且所述第二功率开关包括以半桥耦合至所述同步晶体管的控制晶体管。
17.根据权利要求12所述的集成功率组件，其中所述第一功率开关和所述第二功率开关中的至少一个选自由以下项构成的组：场效应晶体管(FET)、绝缘栅双极型晶体管(IGBT)和高电子迁移率晶体管(HEMT)。
18.根据权利要求12所述的集成功率组件，其中所述第一功率开关和所述第二功率开关中的至少一个包括硅FET或GaNFET。
19.根据权利要求12所述的集成功率组件，其中所述第一引线框的所述局部蚀刻段具有实质上均匀的厚度。
20.根据权利要求12所述的集成功率组件，其中所述无腿导电夹包括铜。
CN201510918214.1A 2014-12-10 2015-12-10 具有减小的形状因子和增强的热耗散的集成功率组件 Pending CN105702638A (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107564882A (zh) * 2016-06-30 2018-01-09 施韦策电子公司 电路板构件和用于制造电路板构件的方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017213759A1 (de) 2017-08-08 2019-02-14 Schweizer Electronic Ag Leiterplattenelement und Verfahren zum Herstellen eines Leiterplattenelements
CN111033988B (zh) * 2017-09-29 2023-04-18 日本电产株式会社 电源模块以及dc-dc转换器
EP3739756A1 (en) * 2019-05-17 2020-11-18 Nexperia B.V. Cascode semiconductor device and method of manufacture
CN110416200B (zh) * 2019-07-02 2020-11-20 珠海格力电器股份有限公司 一种功率模块封装结构及制作方法
US11158567B2 (en) 2019-08-09 2021-10-26 Texas Instruments Incorporated Package with stacked power stage and integrated control die
US11715679B2 (en) 2019-10-09 2023-08-01 Texas Instruments Incorporated Power stage package including flexible circuit and stacked die
US11302615B2 (en) 2019-12-30 2022-04-12 Texas Instruments Incorporated Semiconductor package with isolated heat spreader
EP3982404A1 (en) * 2020-10-07 2022-04-13 Infineon Technologies Austria AG Semiconductor module
US11750089B2 (en) * 2021-10-28 2023-09-05 Alpha And Omega Semiconductor International Lp Power converter for high power density
DE102021213497A1 (de) 2021-11-30 2023-06-01 Zf Friedrichshafen Ag Halbleiterpackage, Halbleitermodul, Stromrichter, elektrischer Achsantrieb sowie Kraftfahrzeug

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120061813A1 (en) * 2010-09-14 2012-03-15 Yueh-Se Ho Package Structure for DC-DC Converter
CN103579154A (zh) * 2012-07-30 2014-02-12 英飞凌科技股份有限公司 包括叠层的电气器件封装以及其制造方法
US20140203419A1 (en) * 2011-01-14 2014-07-24 International Rectifier Corporation Half-Bridge Package with a Conductive Clip
US20140264804A1 (en) * 2013-03-14 2014-09-18 Vishay-Siliconix Stack die package

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7804131B2 (en) * 2006-04-28 2010-09-28 International Rectifier Corporation Multi-chip module
US8450149B2 (en) * 2009-10-16 2013-05-28 Texas Instruments Incorporated Stacked leadframe implementation for DC/DC convertor power module incorporating a stacked controller and stacked leadframe construction methodology
US8120158B2 (en) * 2009-11-10 2012-02-21 Infineon Technologies Ag Laminate electronic device
US8674497B2 (en) * 2011-01-14 2014-03-18 International Business Machines Corporation Stacked half-bridge package with a current carrying layer
US9589929B2 (en) * 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
US9041170B2 (en) * 2013-04-02 2015-05-26 Infineon Technologies Austria Ag Multi-level semiconductor package
US9257424B2 (en) * 2013-11-08 2016-02-09 Infineon Technologies Austria Ag Semiconductor device
US9620475B2 (en) * 2013-12-09 2017-04-11 Infineon Technologies Americas Corp Array based fabrication of power semiconductor package with integrated heat spreader
US20150340305A1 (en) * 2014-05-20 2015-11-26 Freescale Semiconductor, Inc. Stacked die package with redistribution layer
US9520798B2 (en) * 2014-08-26 2016-12-13 General Electric Company Multi-level DC-DC converter with galvanic isolation and adaptive conversion ratio

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120061813A1 (en) * 2010-09-14 2012-03-15 Yueh-Se Ho Package Structure for DC-DC Converter
US20140203419A1 (en) * 2011-01-14 2014-07-24 International Rectifier Corporation Half-Bridge Package with a Conductive Clip
CN103579154A (zh) * 2012-07-30 2014-02-12 英飞凌科技股份有限公司 包括叠层的电气器件封装以及其制造方法
US20140264804A1 (en) * 2013-03-14 2014-09-18 Vishay-Siliconix Stack die package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107564882A (zh) * 2016-06-30 2018-01-09 施韦策电子公司 电路板构件和用于制造电路板构件的方法
CN107564882B (zh) * 2016-06-30 2023-03-24 施韦策电子公司 电路板构件和用于制造电路板构件的方法

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