CN107017172A - 使不同类型的半导体管芯附接到同一导热法兰的多管芯封装 - Google Patents

使不同类型的半导体管芯附接到同一导热法兰的多管芯封装 Download PDF

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CN107017172A
CN107017172A CN201610966548.0A CN201610966548A CN107017172A CN 107017172 A CN107017172 A CN 107017172A CN 201610966548 A CN201610966548 A CN 201610966548A CN 107017172 A CN107017172 A CN 107017172A
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semiconductor element
attached
die
tube core
attachment
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CN107017172B (zh
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B.阿加尔
D.常
A.科姆波施
M.莱费夫尔
张希坤
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Infineon Technologies AG
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Abstract

本发明涉及使不同类型的半导体管芯附接到同一导热法兰的多管芯封装。通过经由第一管芯附接材料将由第一半导体材料制成的第一半导体管芯附接到导热法兰、以及经由第二管芯附接材料将第二半导体管芯附接到与第一半导体管芯所附接的相同的导热法兰，制造多管芯封装。该第二半导体管芯由不同于第一半导体材料的第二半导体材料制成。在第二半导体管芯到法兰的附接期间第一管芯附接材料将第一半导体管芯保持在一定位置。将引线附接到导热法兰或附接到固定于该法兰的绝缘构件。该引线提供对第一和第二半导体管芯的外部电气接入。

Description

使不同类型的半导体管芯附接到同一导热法兰的多管芯封装
技术领域
本申请涉及多管芯封装，特别地涉及使不同类型的半导体管芯附接到同一导热法兰的多管芯封装。
背景技术
许多类型的功率放大器封装包括多于一个半导体管芯。例如，Doherty功率放大器封装包括在同一封装中的主放大器和峰值放大器。对于下一代蜂窝通信系统来说，高速数据率、高容量和绿色能源考虑因数是主要的趋势，这迫使Doherty功率放大器变得更高效且具有更宽带宽。利用目前的LDMOS（横向扩散金属氧化物半导体）技术难以实现这些要求，这归因于LDMOS晶体管在降低器件寄生效应方面的限制。GaN技术是一种替代解决方案，它可以在LDMOS技术所限制的方面提供附加性能。然而，GaN技术是较昂贵的并且不如LDMOS那样线性。照此，需要将不同半导体材料类型的管芯集成在同一功率放大器封装中。
发明内容
根据一种制造多管芯封装的方法的一个实施例，该方法包括：经由第一管芯附接材料将由第一半导体材料制成的第一半导体管芯附接到导热法兰；经由第二管芯附接材料将第二半导体管芯附接到与第一半导体管芯所附接的相同的导热法兰，该第二半导体管芯由不同于第一半导体材料的第二半导体材料制成，并且其中在第二半导体管芯到法兰的附接期间第一管芯附接材料将第一半导体管芯保持在一定位置；以及将引线附接到导热法兰或附接到固定于该法兰的绝缘构件，该引线提供对第一和第二半导体管芯的外部电气接入。
根据一种多管芯封装的一个实施例，该封装包括：导热法兰、经由第一管芯附接材料附接到该导热法兰的由第一半导体材料制成的第一半导体管芯、经由第二管芯附接材料附接到与第一半导体管芯所附接的相同的导热法兰的第二半导体管芯、以及附接到导热法兰或附接到固定于该法兰的绝缘构件的引线。该引线被配置成提供对第一和第二半导体管芯的外部电气接入。该第二半导体管芯由不同于第一半导体材料的第二半导体材料制成。
本领域技术人员在阅读下面的具体实施方式时且在查看附图时将会认识到附加的特征和优点。
附图说明
图中的元件不一定相对于彼此按照比例来绘制。相似的参考数字指定对应的类似部件。各个图示的实施例的特征可以被组合，除非它们彼此排除。在附图中描绘且在随后的具描述中详述实施例。
图1图示制造多管芯封装的方法的一个实施例的流程图。
图2图示多管芯封装的一个实施例的自顶向下俯视图。
图3图示使用多个处理腔室制造多管芯封装的方法的一个实施例的流程图。
图4图示使用单个处理腔室制造多管芯封装的方法的一个实施例的流程图。
图5图示多管芯封装的另一实施例的自顶向下俯视图。
图6图示多管芯封装的又一实施例的自顶向下俯视图。
图7图示使由不同半导体材料制成的管芯在被附接到同一导热法兰之前对准的一个实施例的透视图。
图8图示使由不同半导体材料制成的管芯在被附接到同一导热法兰之前对准的另一实施例的透视图。
具体实施方式
接下来描述使两个或更多半导体管芯附接到同一导热法兰的多管芯封装（其中各管芯由不同半导体材料制成）以及制造该多管芯封装的对应方法的实施例。例如，在GaN和LDMOS技术的情况下，GaN和LDMOS管芯二者被用在同一封装内并且被附接到同一导热法兰。这样的布置比所有GaN解决方案成本更低并且更易于线性化，因为连同一个或多个GaN器件一起使用LDMOS技术。使用Doherty放大器作为一个示例，包括在多管芯封装中的GaN功率放大器管芯可以被用作主放大器，以便利用较高的GaN性能。包括在同一多管芯封装中的LDMOS功率放大器管芯可以被用作峰值放大器，以便提供充分的线性度且不会使整体性能降低。
一般来说，由不同半导体材料（诸如SiGe、Si、例如Si或SiC上的GaN、GaAs、InGaAs等等）制成的两个或更多半导体管芯的任何组合可以被附接到同一封装中的同一导热法兰。在功率放大器设计的情况下，多管芯封装在封装内提供两个或更多放大路径。包括在该封装中的各半导体管芯中的一个或多个可以是没有有源器件的无源半导体管芯，诸如电容器、电阻器或电感器管芯。多管芯封装可以包括：陶瓷窗框或其他类型的电绝缘窗框，被附接到导热法兰以支撑封装的金属引线。在另一种情况下，引线被形成为电路板的一部分并且该电路板被附接到导热法兰。多管芯封装可以具有用于将管芯封闭在开口腔内的盖子。
图1图示制造使两个或更多半导体管芯附接到同一导热法兰的多管芯封装的方法的一个实施例，其中各管芯由不同半导体材料制成，并且图2图示根据图1的方法制造的多管芯封装的一个实施例的自顶向下俯视图。
图1中图示的方法包括经由第一管芯附接材料（图2中看不见）将由第一半导体材料制成的第一半导体管芯200附接到导热法兰202（框100）。该导热法兰202可以包括任何导热（以及可选的导电）材料，诸如Cu、CPC（铜、铜-钼、铜层压结构）、CuMo、CuW、Alu、金刚石散热器、CuMo散热器、Cu复合材料、Al复合材料、金刚石复合材料或任何其他适当的导热材料、以及其任何组合。
该方法还包括经由第二管芯附接材料（图2中看不见）将第二半导体管芯204附接到与第一半导体管芯200所附接的相同的导热法兰202，该第二半导体管芯204由不同于第一半导体材料的第二半导体材料制成（框110）。因为不同半导体材料被用于管芯200、204,所以管芯附接材料可能是相同或不同的。而且归因于所使用的不同半导体材料，管芯200、204可以不同电压偏置。例如，GAN和LDMOS功率晶体管管芯常常使用28V或50V的漏极电压，而GaAs和Si功率晶体管管芯常常使用5V或12V的漏极电压。
在每种情况下，不相似半导体材料的半导体管芯200、204都被附接到同一导热法兰202。而且，在第二半导体管芯204到法兰202的附接期间第一管芯附接材料将第一半导体管芯200保持在一定位置。
在一个实施例中，用于将半导体管芯200、204附接到导热法兰202的管芯附接材料是不同的，以使得在第二半导体管芯204到法兰202的附接期间第一半导体管芯200保持固定地附接到法兰202。
如本文中所使用的术语‘管芯附接温度范围’指代管芯附接材料将半导体管芯联接或固定于导热法兰（即部分或完全固体化）的温度范围。例如，在共晶金属系统（诸如AuSi、AuSn、AgSn、CuSn等等）的情况下，管芯附接温度范围指代共晶金属合金从固态变换到液态的温度范围。在导电胶剂或环氧树脂的情况下，管芯附接温度范围指代材料固化或凝固的温度范围。在焊料或烧结膏的情况下，管芯附接温度范围指代该焊料或烧结膏熔化的温度范围。
用于将每个半导体管芯200、204附接到导热法兰202的管芯附接材料取决于制成每个管芯所用的半导体材料的类型。例如，在Si或GaN管芯的情况下，可以使用下面的管芯附接材料：预涂到管芯背侧的AuSn；AuSn预成型件；焊料膏；焊料预成型件；烧结材料；导电或非导电黏合剂（诸如胶剂或环氧树脂）等等。
在另一实施例中，第一管芯附接材料在第一半导体管芯200到导热法兰202的附接期间部分或完全固体化并且在第二半导体管芯204到法兰202的附接期间保持部分或完全固体化。第一管芯附接材料的至少部分固体化确保在第二半导体管芯204到法兰202的附接期间第一管芯附接材料将第一半导体管芯200保持在一定位置。在又一实施例中，第一管芯附接材料具有表面张力，所述表面张力防止第一半导体管芯200在第二半导体管芯204到导热法兰202的附接期间移动。
图1中图示的方法还包括将引线206附接到导热法兰202（例如在如本文中稍后描述的电路板实施方式的情况下）或者附接到固定于法兰202的绝缘构件208（例如在如图2中示出的分离的金属垫/引线的情况下）（框120）。每个引线206是来自封装的包括金属垫或金属迹线的电气连接。引线206提供对包括在多管芯封装中的半导体管芯200、204的外部电气接入。在图2中示出的多管芯封装的情况下，引线206是分离的金属垫/引线，所述分离的金属垫/引线附接到固定于法兰202的绝缘构件208诸如陶瓷或塑料窗框以确保适当的电气隔离。绝缘构件208在附接到法兰202的管芯200、204周围形成腔210。该腔210可以保持开放或者可以例如填充有环氧树脂或凝胶，这取决于封装的类型。可以提供盖子（未示出）来使管芯200、204封闭，或者该封装可以二次注塑（overmold）以密封管芯200、204。多管芯封装可以包括附接到导热法兰202的附加部件，诸如输入和输出电容器212、214（比如MOSCAPS）、规则（金属板）电容器、集成无源器件、无源电容器管芯等等。可以在管芯附接工艺之前或之后或者作为管芯附接工艺的一部分（这取决于所使用的管芯附接材料）来附接这些附加部件。电导体216（诸如接合引线、带状物等）提供引线206与包括在多管芯封装中的相应半导体管芯200、204及其他部件212、214之间的电气连接。
图2中示出的第一和第二半导体管芯200、204二者可以都是功率晶体管管芯。例如，在Doherty放大器电路的情况下，第一功率晶体管管芯200可以是Doherty放大器电路的主放大器，并且第二功率晶体管管芯204可以是Doherty放大器电路的峰值放大器。在一个实施例中，第一半导体管芯200由GaN制成并且第二晶体管管芯204由Si制成，以便利用较高的GaN性能，同时仍在Doherty放大器电路的宽带操作范围上保持充分的线性度。在其他示例中，第二半导体管芯204可以是例如由GaN、GaAs、SiGe等等制成的功率晶体管管芯（诸如功率放大器管芯），并且第一半导体管芯200可以是逻辑管芯（诸如用于驱动功率晶体管管芯的驱动器管芯）且例如由Si制成。
图3图示图1中示出的制造方法的一个实施例，根据该实施例，第一半导体管芯200在第二半导体管芯204之前被附接到导热法兰202并且在第二半导体管芯204到导热法兰202的附接期间第一管芯附接材料218仍处于固态。导热法兰202被放置在用于将第一半导体管芯200附接到法兰202的第一管芯附接腔室300中。在图3的左手侧中示出第一管芯附接工艺。法兰202在第一腔室300内部由基底302支撑。在某些情况下，基底302是散热器，所述散热器附接到导热法兰202的背对第一半导体管芯200的底侧。在第一半导体管芯200到法兰202的附接期间，散热器302可以被附接到导热法兰202。
第一管芯附接材料218可以是具有管芯附接温度范围的较高熔化背侧金属和/或焊料系统，该管芯附接温度范围确保在第二半导体管芯204的后续管芯附接工艺期间第一半导体管芯200将不会移动，即保持在一定位置。可替代地，第一管芯附接材料218可以是烧结材料，所述烧结材料提供到法兰202的充分热和电连接并且在后续管芯附接工艺期间保持固态。在另一示例中，第一管芯附接材料218可以具有较低的熔点，但是第一管芯附接材料218在第一半导体管芯200到导热法兰202的附接期间部分或完全固体化并且在第二半导体管芯204到法兰202的附接期间保持部分或完全固体化。在又一示例中，第一管芯附接材料218具有表面张力，所述表面张力防止第一半导体管芯202在第二半导体管芯204到导热法兰202的附接期间移动。第一管芯附接材料218的另外其他选项包括胶剂或环氧树脂，只要在后续管芯附接工艺期间胶剂/环氧树脂的完整性和可靠性不受损害。
第一管芯附接材料218可以包括多于一个层或部件，并且可以被涂敷于第一管芯200的背侧、法兰204的顶侧、或者第一管芯200的背侧和法兰202的顶侧二者。如由图3中的步骤（a）所指示的，在第一管芯附接腔室300中经由第一管芯附接材料218将第一半导体管芯200附接到导热法兰202。在第一半导体管芯200已被对准之后，经由第一管芯附接材料218将第一管芯200附接到法兰202。在步骤（a）中可以附接多于一个管芯和无源器件、电容器等，只要所使用的管芯附接材料与步骤（a）的管芯附接工艺的工艺参数（例如温度、压力等等）兼容。
然后将导热法兰202从第一管芯附接腔室300移动到用于将第二半导体管芯204附接到导热法兰202的不同管芯附接腔室304，这由图3中的步骤（b）指示。法兰202在第二腔室304内部由相同或不同的基底302支撑。在某些情况下，第二管芯附接材料220的管芯附接温度范围小于第一管芯附接材料218的管芯附接温度范围，以使得在第二管芯附接工艺期间第一半导体管芯200保持固定地附接到法兰202。第二管芯附接工艺允许在不会使法兰202和先前放置的部件200之间的界面熔融的情况下放置具有较低温管芯附接系统的部件。针对第二管芯附接材料220适当的管芯附接系统包括但不限于：共晶焊料（诸如AuSn）或其他共晶金属系统（诸如AgSn、GuSn等）；具有适当低固化温度的胶剂和环氧树脂等。在其他情况下，第一管芯附接材料218在第一半导体管芯200到导热法兰202的附接期间部分或完全固体化并且在第二半导体管芯204到法兰202的附接期间保持部分或完全固体化，或者第一管芯附接材料218至少具有表面张力，所述表面张力防止第一半导体管芯200在第二半导体管芯204到导热法兰202的附接期间移动。
根据所使用的材料的类型，第二管芯附接材料220可以涂敷于第二管芯204的背侧、法兰202的顶侧、或者第二管芯204的背侧和法兰202的顶侧二者。在第二半导体管芯204已被对准之后，经由第二管芯附接材料220将第二管芯204附接到法兰202，这由图3中的步骤（c）指示。在步骤（c）中可以附接多于一个管芯，只要所使用的管芯附接材料与步骤（c）的管芯附接工艺的工艺参数（例如温度、压力等等）兼容。上文描述的顺序管芯附接工艺可以使用如图3中示出的不同管芯附接腔室300、304。多于两个管芯附接轮回（pass）可以被执行以放置许多不同部件类型。
图4图示图1中示出的制造方法的另一实施例，根据该另一实施例，管芯附接工艺可以如上文结合图3描述的那样是顺序的，但是在单个腔室400中执行，即便不同的管芯附接工艺参数（例如温度、压力等）用于将不同类型的管芯200、204附接到法兰202。返回图2的具有两个不同管芯类型的示例，在图4中的标记为（a）的管芯附接工艺期间第一管芯200被附接到法兰202，并且在图4中的标记为（b）的后续管芯附接工艺期间第二管芯204被附接到法兰202。在该后续管芯附接工艺期间第一管芯附接材料218将第一管芯200保持在一定位置，例如原因在于第一管芯附接材料218具有比第二管芯附接材料220更高的管芯附接温度范围并且因此不会在后续管芯附接工艺期间熔融（熔化）。在其他情况下，第一管芯附接材料218在第一半导体管芯200到导热法兰202的附接期间部分或完全固体化并且在第二半导体管芯204到法兰202的附接期间保持部分或完全固体化，或者第一管芯附接材料218至少具有表面张力，所述表面张力防止第一半导体管芯200在第二半导体管芯204到导热法兰202的附接期间移动。可以在单个腔室400中执行多于两个管芯附接轮回以便如上所述放置许多不同部件类型。
可替代地，作为在单个管芯附接腔室400中执行的共同管芯附接工艺的一部分，第一半导体管芯200和第二半导体管芯204可以被附接到导热法兰202，即同时执行图4中的步骤（a）和步骤（b）。根据该实施例，在同一管芯附接腔室400中将使用不同管芯附接系统的部件同时附接到法兰202。与任何分立的管芯附接工艺类似，所有部件可以被接合在同一工具架上，即使使用不同的管芯附接系统。可以使用导热法兰202上的相同基准点（对准标记）来将所有部件对准，并且参考（0/0）位置可以被设置成使得同时放置所有部件直到所有部件被附接到同一法兰202为止。这样，各种管芯附接系统可以被使用并任意组合。而且，实现高的放置准确度，原因在于法兰202直到所有部件的对准和管芯附接都完成时才会移动。稍后更详细地描述不同管芯对准实施例。
图5图示使由不同半导体材料制成的半导体管芯附接到同一导热法兰的多管芯封装的另一实施例的自顶向下俯视图。图5中示出的实施例与图2中示出的实施例类似。然而，不同在于该封装包括：由第一半导体材料制成且经由第一管芯附接材料218（图5中看不见）附接到导热法兰202的多个半导体管芯200、200’；以及由第二半导体材料制成且经由第二管芯附接材料220（图5中也看不见）附接到法兰202的多个半导体管芯204、204’。例如，在Doherty放大器电路的情况下，可以使用第一半导体材料的两个或更多功率晶体管管芯200、200’来实现主放大器。类似地，可以使用第二半导体材料的两个或更多功率晶体管管芯204、204’来实现峰值放大器。其他类型的功率晶体管电路设计可以在它们的物理实现中利用类似的管芯冗余度。在Si作为半导体材料的情况下，由Si制成且附接到法兰202的半导体管芯中的一些半导体管芯可以是无源电容器管芯，例如如本文中先前描述的输入和/或输出电容器212、214。
图6图示使由不同半导体材料制成的半导体管芯600、602、604附接到同一导热（以及可选的导电）法兰的多管芯封装的又一实施例的侧透视图。图6中示出的实施例与图2中示出的实施例类似。然而，不同在于该封装的引线被实现为作为电路板612诸如PCB（印刷电路板）的一部分形成的金属迹线608、610。例如使用胶剂或焊料（导电或不导电）将电路板612直接附接到金属法兰606。电路板612可以如2015年3月31日提交的美国专利申请No.14/673,928中描述的那样构造，通过参考将所述申请的内容整体合并于本文中。
根据图6中示出的实施例，封装引线608、610作为电路板612的一部分且在没有附加的绝缘构件（诸如陶瓷窗框）的情况下被提供，同时仍具有适当的电隔离。可以通过形成电路板612的封装引线608、610的一部分的各种金属迹线614、616、618以封装级集成各种功率放大器功能，诸如用于Doherty放大器设计的输出匹配、输入匹配、驱动器+输入+输出匹配、等等。此外，在不需要信号路径的附加外部连接器的情况下，作为电路板612的一部分提供多管芯封装的引线608、610。电连接器620（诸如导线接合、带状物等）将金属迹线608、610、614（616、618）中的相应金属迹线电连接到半导体管芯600、602、604的不同端子以形成期望的电路。
如本文中先前所述的那样通过电路板612中的开口622将半导体管芯600、602、604附接到法兰606。一些半导体管芯600、602、604是有源半导体管芯（诸如功率晶体管管芯、功率二极管管芯等等）以及/或者包含无源部件（诸如电容器、电感器和电阻器）。每个有源半导体管芯600、602、604可以是横向或垂直器件、或者例如用于放大的某一其他形式的晶体管。
设置在形成于电路板612中的开口622中并附接到法兰606的一个或多个附加半导体管芯624-644可以是没有有源器件的无源半导体管芯，诸如电容器、电阻器或电感器管芯。在电容器管芯的情况下，电容器端子之一处在电容器管芯的底侧并且被附接到导热法兰606。另一电容器端子被设置在电容器管芯的相对侧，即背对法兰606的一侧。可以利用可选的盖子（未示出）来使多管芯封装封闭，以使得如本文中先前所述的那样该封装是开口腔封装。
根据一个实施例，有源半导体管芯600中的一个有源半导体管芯是Doherty放大器电路的驱动级管芯，有源半导体管芯602中的第二有源半导体管芯是Doherty放大器电路的主（或载波）放大器管芯，并且有源半导体管芯604中的第三有源半导体管芯是Doherty放大器电路的峰值放大器管芯。形成Doherty放大器电路的各个匹配网络（诸如输入和输出匹配网络）的部分的无源半导体管芯624-644也可以被放置在电路板开口622中并且被附接到导热法兰606，如图6中所示。半导体管芯600-604、624-644通过电路板612的金属迹线608、610、614、616、618以及引线接合或其他类型的电导体620进行电互连，以形成诸如Doherty放大器电路、功率放大器电路等等之类的电路。
图7图示使由不同半导体材料制成的管芯700、702在被附接到同一导热（以及可选的导电）法兰704之前对准的一个实施例。根据该实施例，在将例如具有较高管芯附接温度范围的第一半导体管芯700附接到法兰704之前，例如经由模式识别使这些半导体管芯700关于导热法兰704上的多个基准点（对准标记）706对准。基准点706中的一个用作参考位置（x=0，y=0）。然后，在将例如具有较低管芯附接温度范围的第二半导体管芯702附接到法兰704之前，使该第二组半导体管芯702关于法兰704上的与第一组半导体管芯700相同的基准点706对准。在图7中将不同半导体管芯700、702的x-y对准坐标示出为xn、ym。
图8图示使由不同半导体材料制成的管芯800、802在被附接到同一导热（以及可选的导电）法兰804之前对准的另一实施例。根据该实施例，在将例如具有较高管芯附接温度范围的第一半导体管芯800附接到法兰804之前，例如经由模式识别使这些半导体管芯800关于导热法兰804上的多个基准点（对准标记）806对准。然后，在将例如具有较低管芯附接温度范围的第二半导体管芯802附接到法兰804之前，例如经由模式识别使该第二组半导体管芯802关于第一组半导体管芯800上的多个基准点808对准。也就是说，与图7中示出的实施例不同在于：第一组被放置的半导体管芯800被用作用于放置第二组管芯802的对准标记。在图8中将不同半导体管芯800、802的x-y对准坐标示出为xn、ym。
为了便于描述，使用空间上的相对术语（诸如“在…下面”、“在…以下”、“下”、“在…之上“、“上”等等）来解释一个元件相对于第二元件的定位。这些术语旨在包括除了与各图中描绘的那些取向不同的取向之外的器件的不同取向。此外，诸如“第一”、“第二”等等的术语也被用来描述各个元件、区域、区段等等，并且也不旨在进行限制。遍及该说明书，相似的术语指代相似的元件。
如本文中所使用的，术语“具有”、“含有”、“包含”、“包括”等等是开放式术语，其指示所陈述的元件或特征的存在，但是不排除额外的元件或特征。冠词“一”、“一个”以及“该”旨在包括复数以及单数，除非上下文另外清楚指示。
要理解，本文中描述的各种实施例的特征可彼此组合，除非另外具体指出。
尽管在本文中已图示和描述了具体实施例，但是本领域普通技术人员将会认识到，在不偏离本发明范围的情况下，各种各样的替代和/或等同实施方式可代替所示出和描述的具体实施例。本申请旨在覆盖本文中讨论的具体实施例的任何适配或变形。因此，旨在使本发明仅由权利要求以及其等同物限制。

Claims (23)

1.一种制造多管芯封装的方法，包括：
经由第一管芯附接材料将由第一半导体材料制成的第一半导体管芯附接到导热法兰；
经由第二管芯附接材料将第二半导体管芯附接到与第一半导体管芯所附接的相同的导热法兰，该第二半导体管芯由不同于第一半导体材料的第二半导体材料制成，并且其中在第二半导体管芯到法兰的附接期间第一管芯附接材料将第一半导体管芯保持在一定位置；以及
将引线附接到导热法兰或附接到固定于该法兰的绝缘构件，该引线提供对第一和第二半导体管芯的外部电气接入。
2.根据权利要求1所述的方法，其中该第一半导体管芯是Doherty放大器电路的主放大器，并且该第二半导体管芯是Doherty放大器电路的峰值放大器。
3.根据权利要求2所述的方法，其中该第一半导体管芯由GaN制成，并且该第二半导体管芯由Si制成。
4.根据权利要求1所述的方法，其中该第一半导体管芯是功率晶体管管芯，并且该第二半导体管芯是功率晶体管管芯。
5.根据权利要求1所述的方法，其中经由第一管芯附接材料将由第一半导体材料制成的多个半导体管芯附接到导热法兰，并且其中经由第二管芯附接材料将由第二半导体材料制成的多个半导体管芯附接到导热法兰。
6.根据权利要求5所述的方法，其中由第一半导体材料制成的半导体管芯中的一些是功率晶体管管芯，并且其中由第一半导体材料制成的半导体管芯中的另一些是无源电容器管芯。
7.根据权利要求1所述的方法，其中该第一管芯附接材料具有第一管芯附接温度范围，并且其中该第二管芯附接材料具有与第一管芯附接温度范围不同的第二管芯附接温度范围。
8.根据权利要求7所述的方法，其中该第一管芯附接温度范围比第二管芯附接温度范围更大，其中该第一半导体管芯在第二半导体管芯之前被附接到导热法兰，并且其中该第一管芯附接材料在第二半导体管芯到导热法兰的附接期间保持于固态。
9.根据权利要求8所述的方法，还包括：
将导热法兰放置在第一管芯附接腔室中以便将第一半导体管芯附接到导热法兰；以及
将导热法兰从第一管芯附接腔室移动到第二管芯附接腔室以便将第二半导体管芯附接到导热法兰。
10.根据权利要求8所述的方法，还包括：
在将第一半导体管芯附接到导热法兰之前，使第一半导体管芯关于导热法兰上的多个基准点对准；以及
在将第二半导体管芯附接到导热法兰之前，使第二半导体管芯关于与对准第一半导体管芯所关于的基准点相同的基准点对准。
11.根据权利要求8所述的方法，还包括：
在将第一半导体管芯附接到导热法兰之前，使第一半导体管芯关于导热法兰上的多个基准点对准；以及
在将第二半导体管芯附接到导热法兰之前，使第二半导体管芯关于第一半导体管芯上的多个基准点对准。
12.根据权利要求1所述的方法，其中作为在单个管芯附接腔室中执行的共同管芯附接工艺的一部分，将第一半导体管芯和第二半导体管芯附接到导热法兰。
13.根据权利要求12所述的方法，还包括：
在将第一半导体管芯和第二半导体管芯附接到导热法兰之前，使第一半导体管芯和第二半导体管芯关于导热法兰上的多个基准点对准。
14.根据权利要求1所述的方法，其中该第一管芯附接材料在第一半导体管芯到导热法兰的附接期间部分或完全固体化，并且在第二半导体管芯到法兰的附接期间保持部分或完全固体化。
15.根据权利要求1所述的方法，其中该第一管芯附接材料具有表面张力，所述表面张力防止第一半导体管芯在第二半导体管芯到导热法兰的附接期间移动。
16.一种多管芯封装，包括：
导热法兰；
由第一半导体材料制成的第一半导体管芯，经由第一管芯附接材料附接到该导热法兰；
第二半导体管芯，经由第二管芯附接材料附接到与第一半导体管芯所附接的相同的导热法兰；以及
引线，附接到导热法兰或附接到固定于该法兰的绝缘构件，
其中该引线被配置成提供对第一和第二半导体管芯的外部电气接入，
其中该第二半导体管芯由不同于第一半导体材料的第二半导体材料制成。
17.根据权利要求16所述的多管芯封装，其中该第一半导体管芯是Doherty放大器电路的主放大器，并且该第二半导体管芯是Doherty放大器电路的峰值放大器。
18.根据权利要求17所述的多管芯封装，其中该第一半导体管芯由GaN制成，并且该第二半导体管芯由Si制成。
19.根据权利要求16所述的多管芯封装，其中该第一半导体管芯是功率晶体管管芯，并且该第二半导体管芯是功率晶体管管芯。
20.根据权利要求16所述的多管芯封装，其中经由第一管芯附接材料将由第一半导体材料制成的多个半导体管芯附接到导热法兰，并且其中经由第二管芯附接材料将由第二半导体材料制成的多个半导体管芯附接到导热法兰。
21.根据权利要求20所述的多管芯封装，其中由第一半导体材料制成的半导体管芯中的一些是功率晶体管管芯，并且其中由第一半导体材料制成的半导体管芯中的另一些是无源电容器管芯。
22.根据权利要求16所述的多管芯封装，其中该第一管芯附接材料具有第一管芯附接温度范围，并且其中该第二管芯附接材料具有与第一管芯附接温度范围不同的第二管芯附接温度范围。
23.根据权利要求22所述的多管芯封装，其中该第二管芯附接材料包括AuSn、AgSn或GuSn中的一个，并且其中该第一管芯附接温度范围大于第二管芯附接温度范围。
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US20180254253A1 (en) 2018-09-06
US9997476B2 (en) 2018-06-12
US20210233877A1 (en) 2021-07-29
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US11004808B2 (en) 2021-05-11
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