CN110970372A - 包括具有嵌入式半导体管芯的间隔件的半导体器件组件 - Google Patents

包括具有嵌入式半导体管芯的间隔件的半导体器件组件 Download PDF

Info

Publication number
CN110970372A
CN110970372A CN201910865104.1A CN201910865104A CN110970372A CN 110970372 A CN110970372 A CN 110970372A CN 201910865104 A CN201910865104 A CN 201910865104A CN 110970372 A CN110970372 A CN 110970372A
Authority
CN
China
Prior art keywords
semiconductor die
conductive spacer
spacer
metal substrate
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910865104.1A
Other languages
English (en)
Inventor
刘勇
林育圣
陈惠斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Semiconductor Components Industries LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Industries LLC filed Critical Semiconductor Components Industries LLC
Publication of CN110970372A publication Critical patent/CN110970372A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/051Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49531Additional leads the additional leads being a wiring board
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49537Plurality of lead frames mounted in one device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49548Cross section geometry
    • H01L23/49551Cross section geometry characterised by bent parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • H01L23/49844Geometry or layout for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074Stacked arrangements of non-apertured devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175Flow barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32237Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/3318Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3512Cracking

Abstract

本发明涉及包括具有嵌入式半导体管芯的间隔件的半导体器件组件。在一般方面,一种半导体器件组件可以包括半导体管芯,该半导体管芯具有:第一表面,该第一表面包括有源电路;第二表面,该第二表面与第一表面相对;和多个侧表面。多个侧表面中的每个侧表面都可以在半导体管芯的第一表面和半导体管芯的第二表面之间延伸。半导体器件组件还可以包括导电间隔件,该导电间隔件具有限定在其中的腔。半导体管芯可以与导电间隔件电耦接和热耦接,半导体管芯至少部分地嵌入腔中。

Description

包括具有嵌入式半导体管芯的间隔件的半导体器件组件
技术领域
本说明书涉及半导体器件组件。更具体地,本说明书涉及包括具有嵌入式半导体管芯的间隔件的半导体器件组件(例如,半导体器件模块)。
背景技术
半导体器件组件,诸如包括多个半导体管芯的半导体器件模块(例如,多芯片模块),可以包括与半导体管芯耦接(例如,电耦接和/或热耦接)的间隔件(导电间隔件)。用于实现此类间隔件的当前方法可以具有某些缺点。例如,包括在此类组件中的各种材料之间的热膨胀系数(CTE)的不匹配可以在半导体管芯上产生应力,这可以导致半导体管芯断裂和/或损坏。此外,用于将半导体管芯与间隔件耦接的材料(例如,粘合剂材料,诸如焊料、导电粘合剂等)中的空隙可以加剧CTE不匹配问题,并使间隔件和半导体管芯之间的热阻和/或电阻增加。此类增加的热阻和/或电阻可以由于半导体器件组件内生成的热量而导致可靠性问题,和/或可以不利地影响半导体管芯和相关联的半导体器件模块的电气性能。
发明内容
在一般方面,一种半导体器件组件可以包括半导体管芯,该半导体管芯具有:第一表面,该第一表面包括有源电路;第二表面,该第二表面与第一表面相对;和多个侧表面。该多个侧表面中的每个侧表面都可以在半导体管芯的第一表面和半导体管芯的第二表面之间延伸。该半导体器件组件还可以包括导电间隔件,该导电间隔件具有限定在其中的腔。该半导体管芯可以与导电间隔件电耦接和热耦接。该半导体管芯可以至少部分地嵌入腔中。
在另一个一般方面,一种半导体器件组件可以包括:半导体管芯;和导电间隔件,该导电间隔件具有限定在导电间隔件的第一表面中的腔。该半导体管芯可以与导电间隔件电耦接和热耦接。该半导体管芯可以至少部分地嵌入腔中。该半导体器件组件还可以包括第一直接接合金属(DBM)衬底。该第一DBM衬底可以与半导体管芯的表面电耦接。该半导体器件组件还可以包括第二DBM衬底,该第二DBM衬底与导电间隔件的第二表面耦接。导电间隔件的第二表面可以与导电间隔件的第一表面相对。该半导体器件组件还可以再包括低模量封装材料。该低模量封装材料可以设置在导电间隔件和第一DBM衬底之间,并且设置在半导体管芯的表面和第一DBM衬底之间。该半导体器件组件还可以又包括模塑料。该模塑料可以封装半导体管芯、导电间隔件、低模量封装材料、第一DBM衬底和第二DBM衬底。
在另一个一般方面,一种半导体器件组件可以包括第一半导体管芯、第二半导体管芯、第一导电间隔件和第二导电间隔件。该第一导电间隔件可以具有限定在第一导电间隔件的第一表面中的腔。该第一半导体管芯可以与第一导电间隔件电耦接和热耦接。该第一半导体管芯可以至少部分地嵌入第一导电间隔件的腔中。该第二导电间隔件可以具有限定在第二导电间隔件的第一表面中的腔。该第二半导体管芯可以与第二导电间隔件电耦接和热耦接。该第二半导体管芯可以至少部分地嵌入第二导电间隔件的腔中。该半导体器件组件还可以包括第一直接接合金属(DBM)衬底。该第一DBM衬底可以与第一半导体管芯的表面电耦接并且与第二半导体管芯的表面电耦接。该半导体器件组件还可以包括第二DBM衬底,该第二DBM衬底与以下各项电耦接和热耦接:第一导电间隔件的第二表面,第一导电间隔件的第二表面可以与第一导电间隔件的第一表面相对;和第二导电间隔件的第二表面,第二导电间隔件的第二表面可以与第二导电间隔件的第一表面相对。
附图说明
图1是示出具有可以包括在半导体器件组件中的嵌入式半导体管芯的间隔件(例如,导电间隔件)的平面图的示意图。
图2是示出具有可以包括在半导体器件组件中的嵌入式半导体管芯和直接接合金属(DBM)衬底的间隔件的示意性剖视图。
图3是示出具有可以包括在半导体器件组件中的嵌入式半导体管芯和DBM衬底的另一个间隔件的示意性剖视图。
图4是示出具有可以包括在半导体器件组件中的嵌入式半导体管芯、DBM衬底和注入的低模量材料的又一个间隔件的示意性剖视图。
图5是示出具有嵌入式半导体管芯的间隔件的示意性剖视图。
图6A至图6C是示出用于生产冲压焊料预成型件的工艺的示意性剖视图。
图7是示出可以通过图6A至图6C的工艺生产的冲压焊料预成型件的等轴视图。
图8是示出包括具有嵌入式半导体管芯的多个间隔件的半导体器件组件的示意性剖视图。
图9是示出用于生产半导体器件组件的工艺的流程图。
在未必按比例绘制的附图中,相似参考符号可指示不同视图中的相似和/或类似部件(元件、结构等)。附图大体上以举例而非限制的方式示出了本公开中所讨论的各种实施方式。在一个附图中示出的参考符号对于相关视图中的相同和/或相似元件可不重复。在多个图中重复的参考符号可不相对于这些图中的每个图具体地讨论,而是提供用于相关视图之间的上下文。另外,并非附图中的所有相似元件都在示出该元件的多个实例时用参考符号具体引用。
具体实施方式
本公开涉及可以用于实现例如功率半导体器件组件(诸如多芯片模块(MCM))的半导体器件组件的实施方式。此类组件可以用于例如汽车应用、工业应用等。例如,本文所述的实施方式可以在诸如电源转换器、点火电路等的汽车高功率模块(AHPM)中实现。
在本文所述的实施方式中,间隔件(例如,导热和/或导电间隔件)可以包括在半导体器件组件中,其中间隔件具有在其中或在其上形成(限定、设置等)的腔器件。半导体管芯(例如,功率半导体器件)可以至少部分地嵌入(设置等)在腔内。
半导体管芯可以使用导电粘合剂与间隔件(在腔中)耦接。在一些实施方式中,此类导电粘合剂可以包括焊料、焊料预成型件、无焊剂焊料、冲压焊料预成型件、焊膏等中的至少一者。此类实施方式可以提高间隔件和相关联的半导体管芯之间的覆盖率(例如,焊料覆盖率)(例如,可以减少或消除空隙),这可以因此减少组件中的材料之间的热膨胀系数(CTE)不匹配(诸如环氧树脂模塑料和铜间隔件之间的不匹配)的不利影响并防止相关联的可靠性问题(诸如管芯断裂)。此外,此类实施方式可以使间隔件和相关联的半导体管芯之间的热阻和/或电阻减小,这可以提高相关联的组件的散热效率,和/或减少由于电阻引起的加热。
图1是示出具有可以包括在半导体器件组件中的嵌入式半导体管芯的间隔件组件(组件)100的平面图的示意图。如图1所示,组件100包括间隔件(例如,导热和/或导电间隔件)110、粘合剂(例如,导热和/或导电粘合剂)120和半导体管芯(管芯)130。在一些实施方式中,间隔件110可以包括一种或多种金属,诸如铜、铜合金、其他金属合金、焊料形成物等。
图1的间隔件110包括围绕间隔件110的表面的周边延伸的圆周环(也可以称为环)110a。环110a可以限定(围绕等)在间隔件110中或在该间隔件上限定(设置等)的腔。取决于特定实施方式,可以使用冲压工艺、蚀刻工艺和/或任何其他适当的工艺来形成腔(以及相关联的环110a)。如图1所示,粘合剂120和管芯130可以设置在由环110a限定的腔中。在一些实施方式中,管芯130可以至少部分地嵌入腔中且通过粘合剂120与间隔件110耦接(例如,热耦接和/或电耦接)。在一些实施方式中,管芯130可以完全嵌入(例如,基本上完全嵌入)腔中并且通过粘合剂120与间隔件110耦接(例如,热耦接和/或电耦接)。在至少图2至图5中示出此类(部分和完全)嵌入式管芯的示例性实施方式。
在一些实施方式中,粘合剂120可以包括焊料、焊料预成型件、无焊剂焊料、冲压焊料预成型件、焊膏等中的至少一者。取决于特定实施方式,在将管芯130与腔中的间隔件110耦接时,可以使粘合剂120回流一次或多次。在一些实施方式中,粘合剂120的此类回流可以使用甲酸和/或形成气体(例如,氢气和氮气)来执行,这可以使用无焊剂焊料来执行(例如,包括在膏、预成型件、冲压预成型件等中)并且可以防止焊料流动(芯吸等)到管芯130的包括有源电路的表面上并引起电短路。
在一些实施方式中,管芯130可以包括功率半导体器件和/或集成电路。例如,管芯130可以包括功率晶体管、功率二极管、控制电路(例如,用于相关联的MCM)等。此类功率晶体管可以包括金属氧化物半导体场效应晶体管(MOSFET)、绝缘栅双极晶体管(IGBT)等。
在图1中,示出了剖面线S-S。作为一般参考,剖面线S-S提供可以与图2至图5和图8的剖视图相对应的剖面线。也就是说,在图2至图5和图8的视图示出(包括)图1中未示出的附加元件时,剖面线S-S提供了对穿过相应的间隔件组件(例如,具有嵌入式半导体管芯)的示例性截面位置的参考,用于本文所示和所述的各种实施方式。
图2是示出具有可以包括在半导体器件组件中的嵌入式半导体管芯和直接接合金属(DBM)衬底的间隔件组件(组件)200的示意性剖视图。如上所述,对于一些实施方式,图2中所示的组件200的视图可以是沿着穿过组件200的剖面线获得的剖视图,该剖面线与穿过图1中的组件100的剖面线S-S大体相对应。
如图2所示,组件200包括间隔件(例如,导热和/或导电间隔件)210、粘合剂(例如,导热和/或导电粘合剂)220、半导体管芯(管芯)230和直接接合金属(DBM)衬底240(例如,直接接合铜(DBC)衬底、DBM电路板等)。在诸如本文所述的实施方式的一些实施方式中,DBM衬底240可以包括设置在两个金属层241(例如,电路层、印刷电路层等)之间的介电层243。
在一些实施方式中,间隔件210可以包括一种或多种金属,诸如铜、铜合金、其他金属合金、焊料形成物等。与间隔件110一样,图2的间隔件210包括可以围绕间隔件210的表面的周边延伸的圆周环(可以被称为环)210a。环210a可以限定(围绕等)在间隔件210中或在该间隔件上限定(设置等)的腔215。与图1的间隔件110一样,取决于特定实施方式,可以使用冲压工艺、蚀刻工艺和/或任何其他适当的工艺来形成腔215(以及相关联的环210a)。如图2所示,粘合剂220和管芯230可以设置在由环210a限定的腔215中。在诸如组件200的一些实施方式中,管芯230可以部分地嵌入腔中并通过粘合剂220与间隔件210耦接(例如,热耦接和/或电耦接)。也就是说,管芯230的上表面230a可以高于(设置在其上方)间隔件210的上表面(例如,环210a的上表面)。
在一些实施方式中,粘合剂220可以包括焊料、焊料预成型件、无焊剂焊料、冲压焊料预成型件、焊膏等中的至少一者。取决于特定实施方式,在将管芯230与腔215中的间隔件210耦接时,可以使粘合剂(例如,焊料)220回流一次或多次。在一些实施方式中,粘合剂220的此类回流可以使用甲酸和/或形成气体(例如,氢气和氮气)来执行,这可以用于执行无焊剂焊料的回流(例如,包括在膏、预成型件、冲压预成型件等中),这可以防止焊料流动(芯吸等)到管芯230a的包括有源电路的表面上并引起电短路。
在一些实施方式中,管芯230可以包括功率半导体器件和/或集成电路,诸如上面所描述的那些。如图2所示,管芯230包括表面230a(例如,第一表面),该表面可以包括有源电路,诸如功率半导体器件和/或集成电路。管芯230还可以包括第二表面230b(例如,背侧表面),该第二表面可以包括与管芯230的衬底(例如,本体)的接触件。如图2所示,第二表面230b与第一表面230a相对。如图2中进一步所示,管芯230可以包括多个侧表面230c(例如,正方形或矩形半导体管芯的四个侧表面),其中每个侧表面230c都在第一表面230a和第二表面230b之间延伸。
在诸如图2所示的组件200的一些实施方式中,管芯230的第二表面230b可以完全嵌入腔215中(并且完全嵌入粘合剂220中),而侧表面230c可以部分地嵌入腔215中(并且部分地嵌入粘合剂220中)。可以(例如,通过使用特定体积的焊料、焊料预成型件等)控制粘合剂(焊料)220的体积。此外,还可以(连同粘合剂220的体积一起)控制管芯230在腔215中的位置(例如,管芯230相对于间隔件210的位置),以实现图2所示的布置。例如,在一些实施方式中,可以使用对准夹具来控制管芯230相对于间隔件210以及在粘合剂220内的位置。
在组件200中,管芯230(例如,管芯230的有源电路)可以使用导电粘合剂(例如,焊料)225与DBM衬底240电耦接(例如,电耦接到金属层241中的一个金属层)。在一些实施方式中,粘合剂225可以包括焊料凸块、预成型焊料、焊膏、烧结或熔融接合物中的至少一者,并且管芯230可以通过使粘合剂(焊料)225回流来与DBM衬底240耦接。
图3是示出具有可以包括在半导体器件组件中的嵌入式半导体管芯和直接接合金属(DBM)衬底的另一个间隔件组件(组件)300的示意性剖视图。如上所述,对于一些实施方式,图3中所示的组件300的视图可以是沿着穿过组件300的剖面线获得的剖视图,该剖面线与穿过图1中的组件100的剖面线S-S大体相对应。
如图3所示,组件300包括具有腔315的间隔件(例如,导热和/或导电间隔件)310、粘合剂(例如,导热和/或导电粘合剂)320、半导体管芯(管芯)330、直接接合金属(DBM)衬底340(例如,直接接合铜(DBC)衬底、DBM电路板等)以及将管芯330与DBM衬底340电耦接的粘合剂(焊料)325。组件300与图2的组件200类似。因此,为了简洁起见,将不再相对于图3重复组件300的与组件200的那些类似的一些细节。
如图3所示,粘合剂320和管芯330可以设置在腔315中。在图3的示例性实施方式中,与图2的示例性实施方式相比,管芯330完全嵌入(基本上完全嵌入)腔315中并通过粘合剂320与间隔件310耦接(例如,热耦接和/或电耦接)。也就是说,在组件300中,管芯330的上表面(在图3中所示的布置中)可以与间隔件310的上表面共面(基本上共面)。在一些实施方式中,管芯330的上表面可以略微高于(例如,略微在其上方)间隔件310的上表面(例如,几微米),这可防止粘合剂(焊料)320在回流处理期间流到管芯330的上表面上,从而防止在有源电路和间隔件310之间发生短路。在一些实施方式中,可以将膜施加到管芯330的上表面以保护设置在管芯330上的有源电路免受可以在回流处理期间在管芯330的上表面上流动的粘合剂(焊料)320的影响。
与组件200一样,可以控制粘合剂(焊料)320的体积以及腔315中的管芯330相对于间隔件310的位置,以实现图3所示的布置。例如,在一些实施方式中,可以在粘合剂320的回流期间使用对准夹具来控制管芯330相对于间隔件310的位置。
图4是示出具有可以包括在半导体器件组件中的嵌入式半导体管芯和直接接合金属(DBM)衬底的另一个间隔件组件(组件)400的示意性剖视图。如上所述,对于一些实施方式,图4中所示的组件400的视图可以是沿着穿过组件400的剖面线获得的剖视图,该剖面线与穿过图1中的组件100的剖面线S-S大体相对应。
如图4所示,组件400包括具有腔415的间隔件(例如,导热和/或导电间隔件)410、粘合剂(例如,导热和/或导电粘合剂)420、半导体管芯(管芯)430、直接接合金属(DBM)衬底440(例如,直接接合铜(DBC)衬底、DBM电路板等)以及将管芯430与DBM衬底440电耦接的粘合剂(焊料)425。组件400与图2的组件200和图3的组件300类似。因此,为了简洁起见,将不再相对于图4重复组件400的与组件200和300的那些类似的一些细节。
如图4所示,粘合剂420和管芯430可以设置在腔415中。在图4的示例性实施方式中,与图2和图3的示例性实施方式相比,粘合剂420和管芯430完全嵌入并凹入腔415中。管芯430通过粘合剂420与间隔件410耦接(例如,热耦接和/或电耦接)。也就是说,在组件400中,管芯430的上表面(在图4中所示的布置中)可以设置在间隔件410的上表面(例如,圆周环的限定腔415的上表面)的下方。在一些实施方式中,所使用的粘合剂420的体积可以使得粘合剂420的上表面在管芯430的上表面的下方(如图4所示),例如,以防止粘合剂(焊料)420(在回流期间)流到管芯430的上表面上并且在设置在管芯430上的有源电路与间隔件410之间引起电短路。
如图4所示,组件400还可以包括低模量封装材料(诸如凝胶、环氧树脂、树脂、环氧树脂材料等)450。在一些实施方式中,低模量材料450可以是有机硅基凝胶材料、或其他非导电低模量凝胶或其他材料。在一些实施方式中,低模量封装材料450可以具有小于管芯430的模量的模量,和/或小于用于对组件400进行模塑的模塑料(例如,诸如图8所示的模塑料860)的模量。
如图4所示,封装材料450可以设置在间隔件410和DBM衬底440之间、粘合剂420和DBM衬底440之间、以及管芯430和DBM衬底440之间。在一些实施方式中,可以将封装材料450注入组件400中。在一些实施方式中,封装材料450可以减少(例如,吸收)管芯430上由于例如在相关联的半导体器件组件中的材料之间(例如,在间隔件410与环氧树脂模塑料之间)的CTE不匹配导致的应力,这可以减少或消除管芯430的断裂(例如,棘轮断裂)。
图5是示出具有嵌入式半导体管芯的间隔件组件(组件)500的示意性剖视图。如上所述,对于一些实施方式,图5中所示的组件500的视图可以是沿着穿过组件500的剖面线获得的剖视图,该剖面线与穿过图1中的组件100的剖面线S-S大体相对应。
如图5所示,组件500包括间隔件510、粘合剂(例如,焊料)部分520和半导体管芯(管芯)530。与组件200、300和400相比,腔515由粘合剂部分520限定(形成在其中、设置在其中等)。如图5所示,粘合剂部分520可以包括设置在间隔件510上的第一粘合剂层520a和设置在第一粘合剂层520a上的第二粘合剂层520b。在一些实施方式中,粘合剂层520a和520b可以各自包括不同的粘合剂,诸如具有不同熔点的焊料合金。在一些实施方式中,粘合剂层520a和520b可以各自使用焊料、焊料预成型件、无焊剂焊料、冲压焊料预成型件、焊膏等中的至少一者来实现。例如,在示例性实施方式中,图5中的粘合剂层520a可以包括焊膏,并且粘合剂层520b可以包括冲压焊料预成型件。
在粘合剂层520a和520b的回流之后,管芯530可以(经由组件500的粘合剂部分520)与间隔件510电耦接和/或热耦接。此外,在图5的示例性实施方式中,管芯530部分地嵌入腔515中(与组件200的腔215中的管芯230类似)。在一些实施方式中,组件500的元件的其他布置是可能的,诸如管芯530相对于间隔件510和/或腔515(由粘合剂部分520限定)的不同布置。与本文所述的其他实施方式一样,在用于生产组件500的工艺中,可以(例如,在粘合剂层520a和/或520b的回流期间)使用对准夹具来控制管芯530相对于间隔件510的位置以及在粘合剂部分520内的位置。
还如图5所示,组件500中的焊料部分520的圆周环可以具有厚度T1。在一些实施方式中,可以确定厚度T1以控制包括在粘合剂部分520中的粘合剂(焊料)的体积,使得存在足够体积的粘合剂(焊料)来防止管芯530和粘合剂部分520之间的覆盖率和/或空隙不充分,例如以防止由于包括在包括组件500的半导体器件组件中的材料的CTE不匹配而导致的管芯530的断裂。
图6A至图6C是示出用于生产可以包括在图5的间隔件组件中的冲压焊料预成型件的工艺的示意性剖视图。例如,在一些实施方式中,图6A至图6C中所示的工艺可以用于形成图5的焊料预成型件520b。因此,出于说明的目的并且以举例的方式,进一步参考图5的焊料预成型件(例如,冲压焊料预成型件)520b描述了图6A至图6C的工艺。而且,与上面关于图2至图5所述类似,对于一些实施方式,图6A至图6C的工艺的视图可以是沿着穿过焊料预成型件520b(和冲压工具)的剖面线获得的剖视图,该剖面线与穿过图1中的组件100(例如,间隔件110)的剖面线S-S大体相对应。
如图6A所示,可以将焊料预成型件520b(例如,呈平面焊料预成型件的形式)放置在冲压工具的第一部分605a上,在一些实施方式中,该第一部分可以被称为冲压模具。如图6B所示,可以将冲压工具的第二部分605b在焊料预成型件520b和冲压工具的第一部分605a上向下压(如图6B中的箭头所示)。如图6C所示,在将冲压工具的第二部分605b压到焊料预成型件520b和冲压工具的第一部分605a上之后,以图5和图6C所示的布置冲压出焊料预成型件520b以限定腔515。
图7是示出冲压焊料预成型件520b的示例性实施方式的透视图的图(例如,该冲压焊料预成型件可以通过图6A至图6C的工艺来生产)。如图7所示,冲压焊料预成型件520b包括围绕(限定等)腔515的圆周环510a(例如,如图5和图6C所示)。在一些实施方式中,包括在间隔件组件(诸如组件500(或其他组件))中的焊料预成型件(例如,冲压焊料预成型件)可以采用不同的形式,或者可以使用不同的工艺来形成。例如,最初可以例如使用焊料预成型件浇铸或模具来形成具有诸如冲压焊料预成型件520b的配置的配置的焊料预成型件(无需冲压)。
图8是示出包括具有嵌入式半导体管芯的多个间隔件的半导体器件组件(器件)800的示意性剖视图。在一些实施方式中,器件800可以包括间隔件组件,诸如本文所述的间隔件组件100、200、300、400和500。以举例的方式示出器件800的特定布置,并且其他间隔件组件、或者器件800的元件的布置是可能的,诸如与横向布置的间隔件组件(如图8所示)相比的垂直堆叠的间隔件组件(例如,具有中间DBM衬底)。
在图8所示的示例性实施方式中,器件800包括第一间隔件组件810a(例如,包括第一嵌入式半导体管芯和第一导电间隔件)和第二间隔件组件810b(例如,包括第二嵌入式半导体管芯和第二导电间隔件)。在图8所示的视图中,间隔件组件810a和810b的嵌入式半导体管芯是不可见的,因为在该示例中,半导体管芯完全嵌入其对应的间隔件(导电间隔件)中,诸如在图3和图4的示例性实施方式中。在一些实施方式中,间隔件组件(诸如图2或图5中所示的那些间隔件组件)(或其他间隔件组件)可以包括在器件800中(或包括在其他半导体器件组件中),例如,替代(或补充)间隔件组件810a和810b。
如图8所示,器件800还包括第一DBM衬底840a和第二DBM衬底840b。在器件800中,第一间隔件组件810a的半导体管芯可以使用导电粘合剂(例如,焊料连接件)825a与DBM衬底840a电耦接(和热耦接),该导电粘合剂根据特定实施方式可以包括焊料凸块、预成型焊料、焊膏、烧结或熔融接合物中的至少一者。如图8中进一步所示,在器件800中,第二间隔件组件810b的半导体管芯可以使用导电粘合剂(例如,焊料连接件)825b与DBM衬底840a电耦接(和热耦接),该导电粘合剂根据特定实施方式可以包括焊料凸块、预成型焊料、焊膏、烧结或熔融接合物中的至少一者。此外,在器件800中,第一间隔件组件810a的间隔件可以使用粘合剂(导电粘合剂)820a与DBM衬底840b耦接(例如,电耦接和/或热耦接),这可以使用本文所述的方法来实现。类似地,在器件800中,第二间隔件组件810b的间隔件可以使用粘合剂(导电粘合剂)820b与DBM衬底840b耦接(例如,电耦接和/或热耦接),这可以使用本文所述的方法来实现。
器件800还可以包括低模量封装材料850a(例如,凝胶材料、环氧树脂、树脂和/或底填充材料等),该低模量封装材料可以注入第一间隔件组件810a和DBM衬底840a之间,如图8所示。此外,器件800还可以包括低模量封装材料850b(例如,与封装材料850a相同或不同),该低模量封装材料可以注入第二间隔件组件810b和DBM衬底840a之间,如图8所示。
在一些实施方式中,间隔件组件810a和810b中的一者或两者可以被倒转(例如,相对于它们在图8中示出的布置旋转180度)。例如,在一些实施方式中,第一间隔件组件可以被倒转,并且第一间隔件组件810a的半导体管芯可以与DBM衬底840b耦接(电耦接和/或热耦接),而第一间隔件组件810a的间隔件可以与DBM衬底840a耦接(电耦接和/或热耦接)。在一些实施方式中,第二间隔件组件810b可以类似地被倒转。
如图8所示,器件800还可以包括模塑料860,该模塑料可以封装间隔件组件810a和810b、低模量材料850a和850b、DBM衬底840a和840b、以及器件800的其他元件(诸如本文描述的那些元件)。模塑料860可以使用真空模塑、传递模塑、注塑或任何适当的模塑工艺来形成。在一些实施方式中,模塑料860可以是环氧树脂模塑料。如图8所示,DBM衬底840a的表面和DBM衬底840b的表面可以(例如,使用模塑后研磨工艺)各自通过模塑料860暴露出来。在一些实施方式中,相应的散热器可以与DBM衬底840a和840b的暴露表面耦接,例如,以耗散在器件800的操作期间生成的热量。
图8的器件800还可以包括导电柱(柱)870,该导电柱可以将DBM衬底840a与DBM840b电耦接,和/或可以为DBM衬底840a和840b(在它们之间)提供机械支撑。如图8所示,柱870可以封装在模塑料860中。器件800还可以包括信号端子880,这些信号端子与DBM衬底840a和840b耦接(并且至少部分地封装在模塑料860中)。信号端子可以与例如间隔件组件810a和810b的半导体管芯电耦接,以在器件800的操作期间载送电源电压、输入信号和/或输出信号。
图9是示出用于生产半导体器件组件的工艺900的示例性实施方式的流程图。工艺900可以用于生产半导体器件组件(例如,诸如器件800或其他器件组件),该半导体器件组件包括具有嵌入式半导体管芯的间隔件组件,诸如间隔件组件100、200、300、400和/或500。在一些实施方式中,具有其他配置的具有嵌入式半导体管芯的间隔件组件可以包括在使用方法900生产的器件中。
在方法900中,在框910处,可以在导电间隔件中或在导电间隔件上形成腔。例如,可以在导电间隔件中形成腔诸如腔215、315或415中的一者。例如,如本文所述,可以使用冲压工艺、蚀刻工艺或任何适当的工艺或工艺组合来形成此类腔。在一些实施方式中,可以(例如,使用一个或多个粘合剂层,诸如冲压焊料预成型件520b和粘合剂(焊料)层520a)在导电间隔件上形成腔诸如腔515。
在框920处,可以诸如通过使用一个或多个回流操作以使例如一个或多个导电粘合剂(焊料)层回流来将半导体管芯(例如,至少部分地嵌入腔中)与框910的间隔件耦接。例如,在一些实施方式中,可以将焊膏设置在框910的腔中,并且可以执行第一回流工艺以使焊膏回流并将焊膏均匀地分布在腔中。在该示例中,在第一回流工艺之后(并且一旦回流的焊膏硬化),可以将半导体管芯放置在腔中并且放置在腔中的先前回流的焊料上。然后,可以执行第二回流工艺以将半导体管芯与间隔件诸如在例如图2、图3、图4或图5所示的布置中的一个布置中的间隔件耦接(电耦接和/或热耦接),其中可以使用对准夹具来至少部分地确定半导体管芯在腔中的位置。在一些实施方式中(例如,使用焊料预成型件代替焊膏的实施方式),在框920处,可以使用单个回流工艺来在腔中将半导体管芯与间隔件耦接。在框920处执行的回流工艺的次数将取决于特定实施方式。
在框930处,可以将间隔件与第一DMB衬底(诸如图8中的DMB衬底840b)耦接。例如,可以施加焊料(球、预成型件、膏等)并且可以执行回流工艺。在一些实施方式中,可以在框930处执行其他工艺,诸如烧结或熔融接合。在框940处,可以将半导体管芯与第二DMB衬底(诸如图8中的DMB衬底840a)耦接。例如,可以施加焊料(球、预成型件、膏等)并且可以执行回流工艺。在一些实施方式中,可以在框940处执行其他工艺,诸如烧结或熔融接合。在一些实施方式中,可以使用无焊剂焊料(膏、预成型件等)来执行框920至框940的操作,该无焊剂焊料可以使用甲酸和/或形成气体来回流。
在框950处,可以将低模量封装材料(诸如凝胶、环氧树脂、树脂和/或低模量底填充材料等)(诸如图4和图8中所示的凝胶材料450、850a和850b)注入框920的间隔件组件和框940的第二DMB衬底之间。在框960处,可以执行模塑工艺以使用适当的模塑工艺来将器件组件封装在诸如图8所示的模塑料(例如,模塑料860)中。虽然图9的操作以特定顺序示出,但在一些实施方式中,这些操作可以以其他顺序执行。例如,作为一些示例,可以将框930和框940的顺序颠倒过来,并且/或者可以在工艺900中更早地注入框950中的凝胶材料。而且,在一些实施方式中,工艺900可以包括附加项,诸如:用于生产具有多个间隔件组件的器件的操作,包括具有横向布置的间隔件组件的器件(例如,器件800);或者具有垂直堆叠的间隔件组件的器件,这些器件在间隔件组件之间包括中间DBM衬底。
应当理解,在前面的描述中,当元件诸如层、区域或衬底被提及在另一个元件上,连接到另一个元件,电连接到另一个元件,耦接到另一个元件,或电耦接到另一个元件时,该元件可直接在另一个元件上,连接或耦接到另一个元件,或者可以存在一个或多个中间元件。相反,当元件被提及直接在另一个元件或层上、直接连接到另一个元件或层、或直接耦接到另一个元件或层时,不存在中间元件或层。虽然在整个具体实施方式中可能不会通篇使用术语直接在…上、直接连接到…、或直接耦接到…,但是被示为直接在元件上、直接连接或直接耦接的元件能以此类方式提及。本申请的权利要求书可被修订以叙述在说明书中描述或者在附图中示出的示例性关系。
如在本说明书中所使用的,除非根据上下文明确地指出特定情况,否则单数形式可包括复数形式。除了附图中所示的取向之外,空间相对术语(例如,在…上方、在…上面、在…之上、在…下方、在…下面、在…以下、在…之下、在…顶部、在…底部等)旨在涵盖器件在使用或操作中的不同取向。在一些实施方式中,在…上面和在…下面的相对术语可分别包括竖直地在…上面和竖直地在…下面。在一些实施方式中,术语邻近能包括横向邻近或水平邻近。
一些实施方式可使用各种半导体处理和/或封装技术来实现。一些实施方式可以使用与半导体衬底相关联的各种类型的半导体处理技术来实现,该半导体衬底包括但不限于例如硅(Si)、碳化硅(SiC)、砷化镓(GaAs)、氮化镓(GaN)等。
虽然所描述的实施方式的某些特征已经如本文所述进行了说明,但是本领域技术人员现在将想到许多修改形式、替代形式、变化形式和等同形式。例如,关于一个实施方式示出的特征在适当的情况下也可以包括在其他实施方式中。例如,图4的低模量封装材料450可以至少包括在组件100、200、300和500中。各种实施方式的其他特征也可以类似地包括在其他实施方式中。因此,应当理解,所附权利要求书旨在涵盖落入实施方式的范围内的所有此类修改形式和变化形式。应当理解,这些修改形式和变化形式仅仅以举例而非限制的方式呈现,并且可以进行形式和细节上的各种变化。除了相互排斥的组合以外,本文所述的装置和/或方法的任何部分可以任意组合进行组合。本文所述的实施方式能包括所描述的不同实施方式的功能、部件和/或特征的各种组合和/或子组合。

Claims (12)

1.一种半导体器件组件,包括:
半导体管芯,所述半导体管芯具有:
第一表面,所述第一表面包括有源电路;
第二表面,所述第二表面与所述第一表面相对;以及
多个侧表面,所述多个侧表面各自在所述半导体管芯的所述第一表面和所述半导体管芯的所述第二表面之间延伸;以及
导电间隔件,所述导电间隔件具有限定在其中的腔,所述半导体管芯与所述导电间隔件电耦接和热耦接,所述半导体管芯至少部分地嵌入所述腔中。
2.根据权利要求1所述的半导体器件组件,其中,所述半导体管芯通过设置在所述腔中的粘合剂材料与所述导电间隔件热耦接和电耦接。
3.根据权利要求1所述的半导体器件组件,其中,所述半导体管芯的所述第二表面完全嵌入所述导电间隔件的所述腔中,并且所述半导体管芯的所述多个侧表面至少部分地嵌入所述导电间隔件的所述腔中。
4.根据权利要求1所述的半导体器件组件,还包括:
直接接合金属衬底,所述直接接合金属衬底与所述半导体管芯的所述第一表面电耦接;
低模量封装材料,所述低模量封装材料被设置在所述导电间隔件和所述直接接合金属衬底之间,并且被设置在所述半导体管芯的所述第一表面和所述直接接合金属衬底之间;以及
模塑料,所述模塑料封装所述半导体管芯、所述导电间隔件、所述低模量封装材料和所述直接接合金属衬底,
所述直接接合金属衬底的表面通过所述模塑料暴露出来。
5.根据权利要求4所述的半导体器件组件,其中,所述直接接合金属衬底是第一直接接合金属衬底,并且所述腔被设置在所述导电间隔件的第一表面中,所述半导体器件组件还包括:
第二直接接合金属衬底,所述第二直接接合金属衬底与所述导电间隔件的第二表面耦接,所述导电间隔件的所述第二表面与所述导电间隔件的所述第一表面相对。
6.根据权利要求1所述的半导体器件组件,其中,所述导电间隔件的表面包括圆周环,所述圆周环限定所述腔。
7.根据权利要求1所述的半导体器件组件,其中,所述导电间隔件包括铜间隔件,并且所述腔机械地冲压在所述铜间隔件的表面中。
8.根据权利要求1所述的半导体器件组件,其中,所述导电间隔件包括:
铜间隔件部分;以及
腔部分,所述腔部分设置在所述铜间隔件部分上,所述腔部分包括焊膏或冲压焊料预成型件中的至少一者。
9.一种半导体器件组件,包括:
半导体管芯;
导电间隔件,所述导电间隔件具有限定在所述导电间隔件的第一表面中的腔,所述半导体管芯与所述导电间隔件电耦接和热耦接,所述半导体管芯至少部分地嵌入所述腔中;
第一直接接合金属衬底,所述第一直接接合金属衬底与所述半导体管芯的表面电耦接;
第二直接接合金属衬底,所述第二直接接合金属衬底与所述导电间隔件的第二表面耦接,所述导电间隔件的所述第二表面与所述导电间隔件的所述第一表面相对;
低模量封装材料,所述低模量封装材料被设置在所述导电间隔件和所述第一直接接合金属衬底之间,并且被设置在所述半导体管芯的所述表面和所述第一直接接合金属衬底之间;以及
模塑料,所述模塑料封装所述半导体管芯、所述导电间隔件、所述低模量封装材料、所述第一直接接合金属衬底和所述第二直接接合金属衬底。
10.根据权利要求9所述的半导体器件组件,其中:
所述低模量封装材料是有机硅基凝胶材料;并且
所述半导体管芯通过设置在所述腔中的无焊剂焊料材料与所述导电间隔件热耦接和电耦接。
11.一种半导体器件组件,包括:
第一半导体管芯;
第二半导体管芯;
第一导电间隔件,所述第一导电间隔件具有限定在所述第一导电间隔件的第一表面中的腔,所述第一半导体管芯与所述第一导电间隔件电耦接和热耦接,所述第一半导体管芯至少部分地嵌入所述第一导电间隔件的所述腔中;
第二导电间隔件,所述第二导电间隔件具有限定在所述第二导电间隔件的第一表面中的腔,所述第二半导体管芯与所述第二导电间隔件电耦接和热耦接,所述第二半导体管芯至少部分地嵌入所述第二导电间隔件的所述腔中;
第一直接接合金属衬底,所述第一直接接合金属衬底与所述第一半导体管芯的表面电耦接并且与所述第二半导体管芯的表面电耦接;以及
第二直接接合金属衬底,所述第二直接接合金属衬底与以下各项电耦接和热耦接:
所述第一导电间隔件的第二表面,所述第一导电间隔件的所述第二表面与所述第一导电间隔件的所述第一表面相对;以及
所述第二导电间隔件的第二表面,所述第二导电间隔件的所述第二表面与所述第二导电间隔件的所述第一表面相对。
12.根据权利要求11所述的半导体器件组件,还包括:
低模量封装材料,所述低模量封装材料:
被设置在所述第一导电间隔件和所述第一直接接合金属衬底之间;
被设置在所述第一半导体管芯的所述表面和所述第一直接接合金属衬底之间;
被设置在所述第二导电间隔件和所述第一直接接合金属衬底之间;以及
被设置在所述第二半导体管芯的所述表面和所述第一直接接合金属衬底之间;以及
模塑料,所述模塑料封装所述第一半导体管芯、所述第二半导体管芯、所述第一导电间隔件、所述第二导电间隔件、所述低模量封装材料、所述第一直接接合金属衬底和所述第二直接接合金属衬底,
所述第一直接接合金属衬底的表面通过所述模塑料暴露出来,并且
所述第二直接接合金属衬底的表面通过所述模塑料暴露出来。
CN201910865104.1A 2018-09-28 2019-09-12 包括具有嵌入式半导体管芯的间隔件的半导体器件组件 Pending CN110970372A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/145,918 US10991670B2 (en) 2018-09-28 2018-09-28 Semiconductor device assemblies including spacer with embedded semiconductor die
US16/145,918 2018-09-28

Publications (1)

Publication Number Publication Date
CN110970372A true CN110970372A (zh) 2020-04-07

Family

ID=69781228

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910865104.1A Pending CN110970372A (zh) 2018-09-28 2019-09-12 包括具有嵌入式半导体管芯的间隔件的半导体器件组件

Country Status (3)

Country Link
US (2) US10991670B2 (zh)
CN (1) CN110970372A (zh)
DE (1) DE102019124682A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10991670B2 (en) * 2018-09-28 2021-04-27 Semiconductor Components Industries, Llc Semiconductor device assemblies including spacer with embedded semiconductor die
US20220189856A1 (en) * 2020-12-11 2022-06-16 Nxp B.V. Die attachment for semiconductor device packaging and method therefor

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543740A (en) 1995-04-10 1996-08-06 Philips Electronics North America Corporation Integrated half-bridge driver circuit
US6323549B1 (en) 1996-08-29 2001-11-27 L. Pierre deRochemont Ceramic composite wiring structures for semiconductor devices and method of manufacture
JP3923258B2 (ja) * 2001-01-17 2007-05-30 松下電器産業株式会社 電力制御系電子回路装置及びその製造方法
KR101075169B1 (ko) 2003-08-27 2011-10-19 페어차일드코리아반도체 주식회사 파워 모듈 플립 칩 패키지
US7068097B2 (en) 2003-12-18 2006-06-27 The Boeing Company High frequency high power H-bridge power amplifier
JP4423462B2 (ja) 2003-12-22 2010-03-03 富士電機システムズ株式会社 半導体パワーモジュール
US7301235B2 (en) 2004-06-03 2007-11-27 International Rectifier Corporation Semiconductor device module with flip chip devices on a common lead frame
US7227198B2 (en) 2004-08-11 2007-06-05 International Rectifier Corporation Half-bridge package
US8018056B2 (en) * 2005-12-21 2011-09-13 International Rectifier Corporation Package for high power density devices
KR100793916B1 (ko) 2006-04-05 2008-01-15 삼성전기주식회사 인쇄회로기판 내장형 커패시터의 제조방법
US7663211B2 (en) 2006-05-19 2010-02-16 Fairchild Semiconductor Corporation Dual side cooling integrated power device package and module with a clip attached to a leadframe in the package and the module and methods of manufacture
KR101489325B1 (ko) 2007-03-12 2015-02-06 페어차일드코리아반도체 주식회사 플립-칩 방식의 적층형 파워 모듈 및 그 파워 모듈의제조방법
DE102007017831B8 (de) 2007-04-16 2016-02-18 Infineon Technologies Ag Halbleitermodul und ein Verfahren zur Herstellung eines Halbleitermoduls
KR101524545B1 (ko) 2008-02-28 2015-06-01 페어차일드코리아반도체 주식회사 전력 소자 패키지 및 그 제조 방법
US8354740B2 (en) 2008-12-01 2013-01-15 Alpha & Omega Semiconductor, Inc. Top-side cooled semiconductor package with stacked interconnection plates and method
US8563360B2 (en) * 2009-06-08 2013-10-22 Alpha And Omega Semiconductor, Inc. Power semiconductor device package and fabrication method
US20110260314A1 (en) 2010-04-27 2011-10-27 Stmicroelectronics S.R.L. Die package and corresponding method for realizing a double side cooling of a die package
JP6256145B2 (ja) * 2014-03-26 2018-01-10 株式会社デンソー 半導体装置及びその製造方法
US10014280B2 (en) * 2016-03-29 2018-07-03 Hong Kong Applied Science And Technology Research Institute Co. Ltd. Three dimensional fully molded power electronics module having a plurality of spacers for high power applications
US10483237B2 (en) * 2016-11-11 2019-11-19 Semiconductor Components Industries, Llc Vertically stacked multichip modules
JP2019067949A (ja) * 2017-10-02 2019-04-25 トヨタ自動車株式会社 半導体装置
US10991670B2 (en) * 2018-09-28 2021-04-27 Semiconductor Components Industries, Llc Semiconductor device assemblies including spacer with embedded semiconductor die

Also Published As

Publication number Publication date
US11594510B2 (en) 2023-02-28
US20200105706A1 (en) 2020-04-02
DE102019124682A1 (de) 2020-04-02
US20210225797A1 (en) 2021-07-22
US10991670B2 (en) 2021-04-27

Similar Documents

Publication Publication Date Title
US10734250B2 (en) Method of manufacturing a package having a power semiconductor chip
US6521982B1 (en) Packaging high power integrated circuit devices
US7605451B2 (en) RF power transistor having an encapsulated chip package
US11075137B2 (en) High power module package structures
US9704819B1 (en) Three dimensional fully molded power electronics module having a plurality of spacers for high power applications
JP5930070B2 (ja) 半導体装置
CN106024643B (zh) 引线框架上的衬底中介层
US8766430B2 (en) Semiconductor modules and methods of formation thereof
US11862542B2 (en) Dual side cooling power module and manufacturing method of the same
US11594510B2 (en) Assembly processes for semiconductor device assemblies including spacer with embedded semiconductor die
EP3739624A1 (en) Semiconductor arrangement with a compressible contact element encapsulated between two carriers and corresponding manufacturing method
JP2009070934A (ja) パワー半導体モジュール及びその製法
US10790242B2 (en) Method of manufacturing a semiconductor device
US20160021780A1 (en) Carrier, Semiconductor Module and Fabrication Method Thereof
US9263421B2 (en) Semiconductor device having multiple chips mounted to a carrier
CN217822782U (zh) 一种用于功率氮化镓hemt器件的4引脚to-247封装结构
US11177224B2 (en) Method of manufacturing semiconductor device
CN110444520B (zh) 具有电绝缘散热体的功率器件模组及其制备方法
US20210320054A1 (en) Heatsink for thermal response control for integrated circuits
KR20230159286A (ko) 압축성 접착제를 사용한 반도체 디바이스 배열
CN112420629A (zh) 功率半导体封装体和用于制造功率半导体封装体的方法
CN116895630A (zh) 电子器件组件和用于制造电子器件组件的方法
JP2021057543A (ja) 半導体モジュール及び半導体モジュールの製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination