CN112420629A - 功率半导体封装体和用于制造功率半导体封装体的方法 - Google Patents
功率半导体封装体和用于制造功率半导体封装体的方法 Download PDFInfo
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Abstract
一种功率半导体封装体包括:功率半导体芯片;电连接器,其布置在所述功率半导体芯片的第一侧处并包括耦合到所述功率半导体芯片的功率电极的第一表面;包封体,其至少部分地包封所述功率半导体芯片和所述电连接器,以及电绝缘层,其布置在所述电连接器的与所述第一表面相反的第二表面处,其中,所述包封体的部分和所述电绝缘层的部分形成所述功率半导体封装体的共面表面。
Description
技术领域
本公开总体上涉及一种功率半导体封装体和一种用于制造功率半导体封装体的方法。
背景技术
半导体装置制造商不断努力改进半导体封装体的制造技术以及半导体封装体的电、热和机械性能。功率半导体封装体的许多制造技术都需要从中间产品去除材料,例如通过烧蚀、蚀刻、研磨、锯切等。这种去除过程可能是耗时的或资源密集的,因此可能增加功率半导体封装体的制造成本。用于制造功率半导体封装体的改进的方法和改进的功率半导体封装体可以帮助克服这些和其它问题。
发明内容
多个方面涉及一种功率半导体封装体,包括:功率半导体芯片;电连接器,其布置在所述功率半导体芯片的第一侧处并包括耦合到所述功率半导体芯片的功率电极的第一表面;包封体,其至少部分地包封所述功率半导体芯片和所述电连接器;以及电绝缘层,其布置在所述电连接器的与所述第一表面相反的第二表面处,其中,所述包封体的部分和所述电绝缘层的部分形成所述功率半导体封装体的共面表面。
多个方面涉及一种用于制造功率半导体封装体的方法,所述方法包括:提供功率半导体芯片;将电连接器布置在所述功率半导体芯片的第一侧处并将所述电连接器的第一表面耦合到所述功率半导体芯片的第一侧上的功率电极;将电绝缘层布置在所述电连接器的与所述第一表面相反的第二表面处;用包封体至少部分地包封所述功率半导体芯片和所述电连接器;以及薄化所述包封体和所述电绝缘层,使得在薄化之后,所述包封体的部分和所述电绝缘层的部分形成所述功率半导体封装体的共面表面。
多个方面涉及一种用于制造功率半导体封装体的方法,所述方法包括:提供功率半导体芯片;将电连接器布置在所述功率半导体芯片之上并将所述电连接器的第一表面耦合到所述功率半导体芯片的功率电极;用包封体至少部分地包封所述功率半导体芯片和所述电连接器,使得所述电连接器的与所述第一表面相反的第二表面至少部分地暴露;以及将电绝缘层布置在所述电连接器的暴露部分之上,使得所述包封体的部分和所述电绝缘层的部分形成所述功率半导体封装体的共面表面。
附图说明
附图示出了示例并且与说明书一起用于解释本公开的原理。本公开的其它示例和许多预期的优点将容易理解,这是因为通过参考下面的详细描述,它们变得更好理解。附图的元件不一定相对于彼此成比例。相同的附图标记表示相应的类似部分。
图1示出了功率半导体封装体的侧视图,其中,包封体的部分和电绝缘层的部分形成共面表面。
图2A和2B示出了另一功率半导体封装体的侧视图和顶视图,其中,包封体的部分和电绝缘层的部分形成共面表面。
图3A至3H示出了根据一种制造方法的处于制造的各个阶段的功率半导体封装体的侧视图。
图4示出了处于制造阶段的功率半导体封装体的侧视图,其中,电绝缘层作为预成型件施加。
图5A和图5B示出了根据另一制造方法的处于制造的不同阶段的功率半导体封装体的侧视图。
图6示出了用于制造功率半导体封装体的一种方法的流程图,该方法包括薄化包封体和电绝缘层。
图7示出了用于制造功率半导体封装体的另一方法的流程图。
具体实施方式
在下面,可参考所正描述的附图的取向使用诸如“顶”、“底”、“左”、“右”、“上”、“下”等方向性术语。因为本公开的构件可以以许多不同的取向定位,所以方向性术语用于说明性目的,而绝不是限制性的。
此外,虽然可能仅针对多个实施方式中的一个来公开一个示例的特定特征或方面,但是对于任何给定的或特定的应用,如果需要和有利,这种特征或方面可以与其它实施方式的一个或多个其它特征或方面组合,除非另有特别说明或除非在技术上受到限制。此外,就在具体实施方式部分或权利要求中使用的术语“包含”、“具有”、“带有”或它们的其它变体而言,这些术语旨在以类似于术语“包括”的方式是开放式包括的含义。可以使用术语“耦合”和“连接”及其派生词。应当理解,这些术语可以用来表示两个元件相互协作或相互作用,而不管它们是直接物理接触或电接触,还是它们不是彼此直接接触;可以在“接合的”、“附连的”或“连接的”元件之间设置居间元件或居间层。然而,“接合的”、“附连的”或“连接的”元件也可能彼此直接接触。
下面进一步描述的半导体芯片可以是不同类型的,可以通过不同的技术制造,并且可以例如包括AC/DC或DC/DC转换器电路、功率MOS晶体管、功率肖特基二极管、JFET(结型栅极场效应晶体管,Junction Gate Field Effect Transistor)、功率双极晶体管、逻辑集成电路、功率集成电路、带有集成无源元件的芯片等。示例还可使用包括晶体管结构的半导体芯片,其中,至少一个电接触焊盘布置在半导体芯片的第一侧,至少一个其它电接触焊盘布置在半导体芯片的与第一侧相反的第二侧。
半导体芯片可以由特定的半导体材料、例如Si、SiC、SiGe、GaAs、GaN或任何其它半导体材料制造。
图1示出了功率半导体封装体100,其包括功率半导体芯片110、电连接器120、包封体130和电绝缘层140。电连接器120布置在功率半导体芯片110的第一侧111处并且包括电耦合到功率半导体芯片110的功率电极的第一表面121。包封体130至少部分地包封功率半导体芯片110和电连接器120。电绝缘层140布置在电连接器120的与第一表面121相反的第二表面122处,使得包封体130的部分和电绝缘层140的部分形成功率半导体封装体100的共面表面101。
功率半导体芯片110可以布置在载体上,例如布置在裸片焊盘上,使得功率半导体芯片110的与第一侧111相反的第二侧112面向载体。载体可以至少部分地从包封体130暴露,例如在功率半导体封装体100的与共面表面101相反的一侧暴露。功率半导体芯片110可以包括布置在第二侧112并且电耦合到载体的另一功率电极。
电连接器120可以被配置成能够将功率半导体芯片110的功率电极电耦合到功率半导体封装体100的另一部分,例如电耦合到外部接触部或另一个功率半导体芯片。电连接器120可以例如通过焊接或烧结耦合到功率电极。电连接器120可以包括或由如Al、Cu或Fe的金属组成,或者它可以包括或由金属合金组成。电连接器120的第二表面122可以基本上是平坦的。根据一个示例,电连接器120可以是接触夹。
包封体130可以包括或由电绝缘材料、例如聚合物组成。根据一个示例,包封体130是模制体。模制体可以例如通过注射成型来制造。根据一个示例,包封体130可以部分地包封电绝缘层140。
包封体130特别是在共面表面101处可包括在功率半导体封装体100的制造期间在包封体130上执行的研磨过程的痕迹。例如,与其它表面相比,包封体130在共面表面101上可具有更大的表面粗糙度。作为另一示例,包封体130可以包括位于共面表面101上的源自研磨过程的划痕,但是它在其它表面(未经受研磨)上可能不包括此类划痕。此外,包封体130特别是在共面表面101处可被电绝缘层材料的研磨颗粒污染。
电绝缘层140可以包括或由任何合适的电绝缘材料、例如硅树脂组成。电绝缘层140可以例如包括或由热界面材料(TIM)组成。电绝缘层140可以包括或由与包封体130的材料或材料组分不同的材料或材料组分组成。
电绝缘层140可以被配置成能够使电连接器120与例如可以布置在共面表面101处的散热器绝缘。如图1所示,电绝缘层140可以覆盖电连接器120的整个第二表面122。替代性地,电绝缘层140可以仅覆盖第二表面122的一部分,而其余部分可以由包封体130覆盖。
电绝缘层140可以具有任何合适的厚度,例如20μm至100μm的范围内、例如约50μm的厚度。
电绝缘层140可以直接布置在电连接器120的第二表面122上。然而,根据一个示例,也可以在电连接器120与电绝缘层140之间布置居间元件。这样的居间元件可以例如包括或由钝化层组成。
电绝缘层140可以包括研磨过程的痕迹,类似于如上所提及的包封体130。这样的痕迹可以例如包括划痕或被包封体材料的研磨颗粒污染的污染物。
电绝缘层140和包封体130可以直接彼此邻接。特别地,在共面表面101上,电绝缘层140与包封体130之间可以没有间隙。
图2A示出了另一功率半导体封装200,除下面提到的差异之外,其可以与功率半导体封装体100相似或相同。
功率半导体封装体200包括载体210和第一外部接触部220。功率半导体芯片110布置在载体210上并与其电耦合。第一外部接触部220侧向布置在载体210旁边,并且电连接器120将功率半导体芯片110电耦合到第一外部接触部220。
根据一个示例,电连接器120和第一外部接触部220是两个不同的部件(这种情况在图2A中示出)。这两个部件可以例如通过焊接连接,或者它们可以烧结在彼此上。根据另一个示例,电连接器120和第一外部接触部220是共同的部件,这意味着电连接器120包括延伸出包封体130并形成第一外部接触部220的远端。
功率半导体封装体200还可以包括第二外部接触部211。第二外部接触部211可以例如是载体210的一部分。第一和第二外部接触部220、211可以基本上是共面的,并且可以例如布置在功率半导体封装体200的相反侧处。此外,外部接触部220、211可以延伸超过包封体130的轮廓(如图2A所示)。然而,外部接触部220、211也可能不延伸超过包封体130的轮廓(在这种情况下,功率半导体封装体200可以称为无引线封装体)。
根据一个示例,载体210和/或第一外部接触部220是引线框架的一部分。根据另一示例,载体210是直接铝接合(DAB)、直接铜接合(DCB)、活性金属钎焊等类型的载体。
图2B示出了功率半导体封装体200的共面表面101的俯视图。电绝缘层140可以布置在共面表面101的任何合适的位置处,例如如图2B所示的中间。电绝缘层140可以在所有四周被包封体130包围,或者它可以延伸到功率半导体封装体200的一个或多个边缘。
共面表面101的任何合适的百分比,例如20%以上、40%以上、60%以上或80%以上可以由电绝缘层140组成。根据一个示例,也有可能几乎所有或甚至整个共面表面101都由电绝缘层140组成。
根据一个示例,功率半导体封装体200包括多于一个的电绝缘层140。这些多于一个的电绝缘层140可以例如并排布置在共面表面101上。例如,功率半导体封装体200可以包括多于一个的功率半导体芯片110和电连接器120,并且每个电绝缘层140可以分别布置在这些电连接器120中的相应的一个上。
在下面的图3A至3H中,示出了根据用于制造功率半导体封装体的方法的一个示例的各个制造阶段的功率半导体封装体200。功率半导体封装体100可以例如以类似方式制造。
如图3A所示,可以提供载体210和第一外部接触部。载体210和/或第一外部接触部220可以是引线框架的一部分。根据一个示例,在载体210和/或第一外部接触部220仍然是引线框架条的一部分的情况下,提供载体210和/或第一外部接触部220。载体210和/或第一外部接触部220可以布置在临时载体、例如粘附带上。
如图3B所示,功率半导体芯片110可以布置在载体210上。这可以包括使用拾取-放置过程。将功率半导体芯片110布置在载体210上还可以包括将功率半导体芯片110电耦合和机械耦合到载体210。这可以例如通过焊接或烧结进行。
如图3C所示,电连接器120可以布置在功率半导体芯片110上。电连接器120还可以布置在第一外部接触部220上。将电连接器120布置在功率半导体芯片110上并且可能也布置在第一外部接触部220上可以包括使用拾取-放置过程。此外,电连接器120还可以通过例如焊接或烧结电耦合和机械耦合到功率半导体芯片110并且还可能电耦合和机械耦合到第一外部接触部220。
根据一个示例,在功率半导体芯片已经焊接或烧结到载体210上之后,将电连接器120焊接或烧结到功率半导体芯片110(和第一外部接触部220)上。根据另一个示例,所有接合部同时焊接或烧结。
如图3D所示,电绝缘材料310沉积在电连接器120上,特别是沉积在第二表面122上。电绝缘材料310可以例如以流体形式分配在电连接器120上。此外,模版320和/或刮板330可以用于以预限定的方式将电绝缘材料310分配在电连接器120的第二表面122上。
如图3E所示,固化过程可以用于固化电绝缘材料310。例如,电绝缘材料310可以包括助熔剂,并且固化过程可以用于去除助熔剂。电绝缘材料310可以例如通过在炉子340中施加热量来固化。在炉子340中的固化可以使用任何合适的固化温度、例如不超过约250℃、不超过约200℃或不超过约150℃的固化温度进行。固化过程可以例如持续时间不超过几分钟、不超过2分钟、不超过1分钟或不超过30秒。
固化过程可使得(可能被硬化的)电绝缘层140的形成。
如图3F所示,可以制造包封体130。这特别可以在电绝缘材料310已经固化并且电绝缘层140已经形成之后进行。
制造包封体130可以包括在载体210、第一外部接触部220、功率半导体芯片110和电连接器120之上模制。制造包封体130还可以包括在电绝缘层140之上模制。模制可以使用合适的模制工具来进行以获得包封体130。
根据一个示例,可以进行模制而使得包封体130完全覆盖电绝缘层140(特别地,使得包封体130还覆盖电绝缘层140的背离电连接器120的表面,参看图3F)。根据另一个示例,可以进行模制,使得包封体130不覆盖电绝缘层140的背离电连接器120的表面。
根据一个示例,另一固化过程可以用于固化包封体130。
如图3G所示,研磨过程可以用于研磨功率半导体封装体的第一侧350。可以例如使用研磨轮360进行研磨。可以通过研磨过程将电绝缘层140从包封体130暴露。
根据一个示例,电绝缘层140可在研磨过程前具有80μm或更大、100μm或更大或120μm或更大的厚度。在研磨过程之后,电绝缘层140可以例如具有30μm或更大、40μm或更大或50μm或更大的厚度。
如图3G所示的研磨过程有利地不需要研磨电连接器120。电连接器120可例如包括或由金属或金属合金组成,因此可比电绝缘层140更坚固。因此,研磨电连接器120会增加研磨轮360的磨损和裂开。这进而又会增加功率半导体模块的制造成本。
图3H示出了在图3G的研磨过程之后的功率半导体模块200。由于研磨功率半导体封装体200的第一侧350,电绝缘层140和包封体130形成共面表面101。
如图3D所示,沉积电绝缘材料310可以包括分配过程。然而,沉积电绝缘材料310也可采用其它方法。图4示出了另一种沉积方法,该方法包括将电绝缘材料310以预成型件的形式布置在电连接器120上,所述预成型件是固体或半固体块。之后,可以如图3E至3H所述地处理功率半导体封装体。
图5A和5B示出了制造功率半导体封装体的另一方法,所述方法可以代替结合图3D到3F所示的过程使用。
在图3D至3F中,示出了在制造包封体130之前制造电绝缘层140。根据图5A和5B的方法包括在制造电绝缘层140之前制造包封体130。
图5A示出了模制过程,其中,模制工具包括覆盖电连接器120的第二表面122的盖510。因此,在模制过程之后,第二表面122从包封体130暴露。
图5B示出了将电绝缘层140布置在电连接器120的暴露的第二表面122之上。因为根据图5A和5B的方法不是必须包括研磨功率半导体封装体的第一侧350,所以电绝缘层140和包封体130不是必须形成共面表面。
图6是用于制造功率半导体封装体的方法600的流程图。方法600可以例如用于制造功率半导体封装体100和200。
方法600包括:在步骤601,提供功率半导体芯片;在步骤602,将电连接器布置在功率半导体芯片的第一侧处并将电连接器的第一表面耦合到功率半导体芯片的第一侧上的功率电极;在步骤603,将电绝缘层布置在电连接器的与第一表面相反的第二表面处;在步骤604,用包封体至少部分地包封功率半导体芯片和电连接器;以及在步骤605,薄化包封体和电绝缘层,使得在薄化后,包封体的部分和电绝缘层的部分形成功率半导体封装体的共面表面。
根据方法600的一个示例,所述薄化可以包括研磨、蚀刻、锯切或烧蚀工艺中的一种或它们的组合。此外,可以使用印刷工艺或通过沉积预成型件将电绝缘层布置在电连接器的第二表面处。此外,所述包封可以包括模制过程。
方法600可以可选地包括在用包封体包封之前固化电绝缘层。方法600还可以可选地包括在薄化之后将散热器布置在共面表面处。
图7是用于制造功率半导体封装体的方法700的流程图。方法700可以例如用于制造功率半导体封装体100和200。
方法700包括:在步骤701,提供功率半导体芯片;在步骤702,将电连接器布置在功率半导体芯片之上并将电连接器的第一表面耦合到功率半导体芯片的功率电极;在步骤703,用包封体至少部分地包封功率半导体芯片和电连接器,使得电连接器的与第一表面相反的第二表面至少部分地暴露;以及在步骤704,将电绝缘层布置在电连接器的暴露部分之上,使得包封体的部分和电绝缘层的部分形成功率半导体封装体的共面表面。
根据方法700的一个示例,使用印刷工艺或通过沉积预成型件将电绝缘层布置在电连接器的暴露部分之上。
示例
在下面,使用特殊的示例进一步描述功率半导体封装体和用于制造功率半导体封装体的方法。
示例1是一种功率半导体封装体,包括:功率半导体芯片、布置在所述功率半导体芯片的第一侧处并包括耦合到所述功率半导体芯片的功率电极的第一表面的电连接器、至少部分地包封所述功率半导体芯片和所述电连接器的包封体以及布置在所述电连接器的与所述第一表面相反的第二表面处的电绝缘层,其中,所述包封体的部分和所述电绝缘层的部分形成所述功率半导体封装体的共面表面。
示例2是示例1的功率半导体封装体,其中,所述包封体和所述电绝缘层包括位于半导体封装体的共面表面处的研磨痕迹。
示例3是示例1或2的功率半导体封装体,其中,所述电绝缘层包括热界面材料,所述共面表面被配置成能够耦合到散热器。
示例4是前述示例中任一个的功率半导体封装体,其中,所述功率半导体封装体还包括:裸片载体,其中,所述功率半导体芯片布置在所述裸片载体上,所述裸片载体在所述功率半导体封装体的与所述共面表面相反的一侧从所述包封体暴露。
示例5是前述示例中任一个的功率半导体封装体,其中,所述共面表面中的所述包封体的所述部分被所述绝缘层材料的研磨颗粒污染,和/或所述绝缘层被所述包封体材料的研磨颗粒污染。
示例6是前述示例中任一个的功率半导体封装体,其中,所述电连接器包括金属夹。
示例7是一种用于制造功率半导体封装体的方法,所述方法包括:提供功率半导体芯片;将电连接器布置在所述功率半导体芯片的第一侧处并将所述电连接器的第一表面耦合到所述功率半导体芯片的第一侧上的功率电极;将电绝缘层布置在所述电连接器的与所述第一表面相反的第二表面处;用包封体至少部分地包封所述功率半导体芯片和所述电连接器;以及薄化所述包封体和所述电绝缘层,使得在薄化后,所述包封体的部分和所述电绝缘层的部分形成所述功率半导体封装体的共面表面。
示例8是示例7的方法,其中,所述薄化包括研磨、蚀刻、锯切和烧蚀工艺中的一种或它们的组合。
示例9是示例7或8的方法,其中,使用印刷工艺或通过沉积预成型件将所述电绝缘层布置在所述电连接器的第二表面处。
示例10是示例7至9中任一个的方法,其中,所述方法还包括:在用所述包封体包封之前,固化所述电绝缘层。
示例11是示例7至示例10中任一个的方法,其中,所述包封包括模制过程。
示例12是示例7至11中任一个的方法,其中,所述方法还包括:在所述薄化之后,将散热器布置在所述共面表面处。
示例13是一种用于制造功率半导体封装体的方法,所述方法包括:提供功率半导体芯片;将电连接器布置在功率半导体芯片之上并将所述电连接器的第一表面耦合到所述功率半导体芯片的功率电极;用包封体至少部分地包封所述功率半导体芯片和所述电连接器,使得所述电连接器的与所述第一表面相反的第二表面至少部分地暴露;以及将电绝缘层布置在所述电连接器的暴露部分之上,使得所述包封体的部分和所述电绝缘层的部分形成所述功率半导体封装体的共面表面。
示例14是示例13的方法,其中,使用印刷工艺或通过沉积预成型件将所述电绝缘层布置在所述电连接器的暴露部分之上。
示例15是示例13或14的方法,其中,所述包封包括模制过程。
示例16是示例13至15中任一个的方法,其中,所述方法还包括:固化所述电绝缘层。
虽然已经参照一个或多个实施方式说明和描述了本公开,但是在不脱离所附权利要求的精神和范围的情况下,可以对所说明的示例进行改变和/或修改。特别是关于由上述构件或结构(组件、装置、电路、系统等)执行的各种功能,除非另外指出,否则用于描述这些构件的术语(包括对“手段”的引述)意欲对应于执行所描述的构件的指定功能的任何构件或结构(例如,功能上等同),即使在结构上不等同于本文所示的本公开的示例性实施方式中执行所述功能的所公开的结构。
Claims (16)
1.一种功率半导体封装体(100、200),包括:
功率半导体芯片(110),
电连接器(120),其布置在所述功率半导体芯片(110)的第一侧(111)处并包括耦合到所述功率半导体芯片(110)的功率电极的第一表面(121),
包封体(130),其至少部分地包封所述功率半导体芯片(110)和所述电连接器(120),以及
电绝缘层(140),其布置在所述电连接器(120)的与所述第一表面(121)相反的第二表面(122)处,
其中,所述包封体(130)的部分和所述电绝缘层(140)的部分形成所述功率半导体封装体(100、200)的共面表面(101)。
2.根据权利要求1所述的功率半导体封装体(100、200),其中,所述包封体(130)和所述电绝缘层(140)包括在所述半导体封装体(100、200)的共面表面(101)处的研磨痕迹。
3.根据权利要求1或2所述的功率半导体封装体(100、200),其中,所述电绝缘层(140)包括热界面材料,所述共面表面(101)被配置成能够耦合到散热器。
4.根据前述权利要求中任一项所述的功率半导体封装体(100、200),其中,所述功率半导体封装体(100、200)还包括:
裸片载体(210),其中,所述功率半导体芯片(110)布置在所述裸片载体(210)上,所述裸片载体(210)在所述功率半导体封装体(100、200)的与所述共面表面(101)相反的一侧从所述包封体(130)暴露。
5.根据前述权利要求中任一项所述的功率半导体封装体(100、200),其中,所述共面表面(101)中的所述包封体(130)的所述部分被所述绝缘层材料的研磨颗粒污染,和/或所述绝缘层(140)被所述包封体材料的研磨颗粒污染。
6.根据前述权利要求中任一项所述的功率半导体封装体(100、200),其中,所述电连接器(120)包括金属夹。
7.一种用于制造功率半导体封装体的方法(600),所述方法包括:
提供(601)功率半导体芯片,
将电连接器布置(602)在所述功率半导体芯片的第一侧处并将所述电连接器的第一表面耦合到所述功率半导体芯片的第一侧上的功率电极,
将电绝缘层布置(603)在所述电连接器的与所述第一表面相反的第二表面处,
用包封体至少部分地包封(604)所述功率半导体芯片和所述电连接器,以及
薄化(605)所述包封体和所述电绝缘层,使得在薄化之后,所述包封体的部分和所述电绝缘层的部分形成所述功率半导体封装体的共面表面。
8.根据权利要求7所述的方法(600),其中,所述薄化(605)包括研磨、蚀刻、锯切和烧蚀工艺中的一种或它们的组合。
9.根据权利要求7或8所述的方法(600),其中,使用印刷工艺或通过沉积预成型件将所述电绝缘层布置在所述电连接器的第二表面处。
10.根据权利要求7至9中任一项所述的方法(600),其中,所述方法(600)还包括:
在用所述包封体包封之前,固化所述电绝缘层。
11.根据权利要求7至10中任一项所述的方法(600),其中,所述包封(604)包括模制过程。
12.根据权利要求7至11中任一项所述的方法(600),其中,所述方法(600)还包括:
在所述薄化(605)之后,将散热器布置在所述共面表面上。
13.一种用于制造功率半导体封装体的方法(700),所述方法包括:
提供(701)功率半导体芯片,
将电连接器布置(702)在所述功率半导体芯片之上并将所述电连接器的第一表面耦合到所述功率半导体芯片的功率电极,
用包封体至少部分地包封(703)所述功率半导体芯片和所述电连接器,使得所述电连接器的与所述第一表面相反的第二表面至少部分地暴露,以及
将电绝缘层布置(704)在所述电连接器的暴露部分之上,使得所述包封体的部分和所述电绝缘层的部分形成所述功率半导体封装体的共面表面。
14.根据权利要求13所述的方法(700),其中,使用印刷工艺或通过沉积预成型件将所述电绝缘层布置在所述电连接器的暴露部分之上。
15.根据权利要求13或14所述的方法(700),其中,所述包封(703)包括模制过程。
16.根据权利要求13至15中任一项所述的方法(700),其中,所述方法(700)还包括:
固化所述电绝缘层。
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