FR3053833B1 - Circuit integre comprenant une puce formee d'un transistor a haute tension et comprenant une puce formee d'un transistor a basse tension - Google Patents

Circuit integre comprenant une puce formee d'un transistor a haute tension et comprenant une puce formee d'un transistor a basse tension Download PDF

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Publication number
FR3053833B1
FR3053833B1 FR1656572A FR1656572A FR3053833B1 FR 3053833 B1 FR3053833 B1 FR 3053833B1 FR 1656572 A FR1656572 A FR 1656572A FR 1656572 A FR1656572 A FR 1656572A FR 3053833 B1 FR3053833 B1 FR 3053833B1
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FR
France
Prior art keywords
voltage transistor
chip
integrated circuit
high voltage
low voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1656572A
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English (en)
Other versions
FR3053833A1 (fr
Inventor
Eric Moreau
Thierry Sutto
Laurent Guillot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics France SAS
Original Assignee
Exagan SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Exagan SAS filed Critical Exagan SAS
Priority to FR1656572A priority Critical patent/FR3053833B1/fr
Priority to CN201780031115.9A priority patent/CN109314107B/zh
Priority to PCT/FR2017/051316 priority patent/WO2017203187A1/fr
Priority to PCT/FR2017/051315 priority patent/WO2017203186A1/fr
Priority to US16/304,643 priority patent/US10777513B2/en
Priority to EP17730872.3A priority patent/EP3465755A1/fr
Publication of FR3053833A1 publication Critical patent/FR3053833A1/fr
Application granted granted Critical
Publication of FR3053833B1 publication Critical patent/FR3053833B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention porte sur un circuit intégré (3) comprenant un boîtier (4) et une pluralité de broches de connexion, une première puce (1) comprenant un transistor à haute tension en mode déplétion et une deuxième puce (2) comprenant un transistor à basse tension en mode enrichissement, la première et la seconde puce comportant respectivement des plots de contact de grille (13, 23), de drain (11, 21) et de source (12, 22) ; le plot de contact de source (12) du transistor à haute tension étant relié électriquement au plot de contact de drain (21) du transistor à basse tension pour former ainsi un nœud milieu du circuit, le circuit intégré étant caractérisé en ce qu'il comprend une broche de point milieu (35) électriquement reliée au nœud milieu du circuit.
FR1656572A 2016-05-26 2016-07-08 Circuit integre comprenant une puce formee d'un transistor a haute tension et comprenant une puce formee d'un transistor a basse tension Active FR3053833B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
FR1656572A FR3053833B1 (fr) 2016-07-08 2016-07-08 Circuit integre comprenant une puce formee d'un transistor a haute tension et comprenant une puce formee d'un transistor a basse tension
CN201780031115.9A CN109314107B (zh) 2016-05-26 2017-05-26 包括由高压晶体管形成的芯片并且包括由低压晶体管形成的芯片的集成电路
PCT/FR2017/051316 WO2017203187A1 (fr) 2016-05-26 2017-05-26 Circuit intégré comprenant une pluralité de puces formées d'un transistor à haute tension et comprenant une puce formée d'un transistor à basse tension
PCT/FR2017/051315 WO2017203186A1 (fr) 2016-05-26 2017-05-26 Circuit intégré comprenant une puce formée d'un transistor à haute tension et comprenant une puce formée d'un transistor à basse tension
US16/304,643 US10777513B2 (en) 2016-05-26 2017-05-26 Integrated circuit comprising a chip formed by a high-voltage transistor and comprising a chip formed by a low-voltage transistor
EP17730872.3A EP3465755A1 (fr) 2016-05-26 2017-05-26 Circuit intégré comprenant une puce formée d'un transistor à haute tension et comprenant une puce formée d'un transistor à basse tension

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1656572 2016-07-08
FR1656572A FR3053833B1 (fr) 2016-07-08 2016-07-08 Circuit integre comprenant une puce formee d'un transistor a haute tension et comprenant une puce formee d'un transistor a basse tension

Publications (2)

Publication Number Publication Date
FR3053833A1 FR3053833A1 (fr) 2018-01-12
FR3053833B1 true FR3053833B1 (fr) 2018-11-16

Family

ID=56842939

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1656572A Active FR3053833B1 (fr) 2016-05-26 2016-07-08 Circuit integre comprenant une puce formee d'un transistor a haute tension et comprenant une puce formee d'un transistor a basse tension

Country Status (1)

Country Link
FR (1) FR3053833B1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11695326B2 (en) 2018-05-22 2023-07-04 Stmicroelectronics International N.V. Half-bridge electronic device comprising two systems for optimizing dead-time between the switching operations of a high level switch and of a low level switch

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8138529B2 (en) * 2009-11-02 2012-03-20 Transphorm Inc. Package configurations for low EMI circuits
US8624662B2 (en) * 2010-02-05 2014-01-07 Transphorm Inc. Semiconductor electronic components and circuits
US9171837B2 (en) * 2012-12-17 2015-10-27 Nxp B.V. Cascode circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11695326B2 (en) 2018-05-22 2023-07-04 Stmicroelectronics International N.V. Half-bridge electronic device comprising two systems for optimizing dead-time between the switching operations of a high level switch and of a low level switch

Also Published As

Publication number Publication date
FR3053833A1 (fr) 2018-01-12

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