CN105874599A - 金属薄膜电阻器及工艺 - Google Patents

金属薄膜电阻器及工艺 Download PDF

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CN105874599A
CN105874599A CN201480071999.7A CN201480071999A CN105874599A CN 105874599 A CN105874599 A CN 105874599A CN 201480071999 A CN201480071999 A CN 201480071999A CN 105874599 A CN105874599 A CN 105874599A
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stop layer
etching stop
resistor
hole
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A·阿里
E·比奇
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

在所描述的示例中，集成电路(100)被形成为具有金属薄膜电阻器(112)和上面的刻蚀停止层(202)。在一种示例工艺中，利用添加一个光刻步骤，在集成电路(100)中形成金属薄膜电阻器(112)。

Description

金属薄膜电阻器及工艺
背景技术
本申请通常涉及集成电路，并且具体地涉及在集成电路中形成互连层中的金属薄膜电阻器。
金属薄膜电阻器是众所周知的，并且可以使用各种电阻性金属形成。镍铬合金(NiCr)和铬硅合金(CrSi)经常被使用。在集成电路制造流程的后端(BEOL)中形成这些类型的薄膜电阻器。BEOL电阻器具有比在生成线的前端(FEOL)中形成的电阻器(通常，多晶硅、氧化硅或N势阱)更少的寄生电容，因为它们被形成在距基板的更大距离处。BEOL电阻由于较低电容被优选用于高频率RF应用。
在集成电路制造流程的BEOL中集成金属薄膜电阻器增加成本和周期时间。图1中示出常规金属薄膜电阻器。金属薄膜电阻器112被形成在第三电介质层110上。第三电介质层被形成在刻蚀停止层108上，刻蚀停止层108在较低互连引线104上。较低互连引线104被嵌入在第二电介质层106中。较低互连引线104可以是通过触点101连接至下层集成电路100中的二极管的第一层级互连，或可以通过通孔101被连接至互连的下层级。
金属薄膜电阻器112的区域通过第一电阻器光致抗蚀剂图案限定。第二电阻器光致抗蚀剂图案用于限定通孔连接焊盘(via landing pad)114，该通孔连接焊盘114形成用于金属薄膜电阻器112中的每个端部的电触点。通孔连接焊盘114在刻蚀电阻器通孔120和电阻器通孔122期间保护薄膜金属薄膜电阻器不受损坏，该损坏可以导致高通孔电阻。第三电阻器光致抗蚀剂图案用于形成针对通孔120和通孔122的开口，以电连接至通孔连接焊盘114。
三种附加光刻步骤加上用于形成通孔连接焊盘114和用于形成电阻器通孔120和电阻器通孔122的附加工艺步骤，给制造流程增加了大量费用和周期时间。
发明内容
在所描述的示例中，集成电路被形成为具有金属薄膜电阻器和在上面的刻蚀停止层。在上面的刻蚀停止层消除了经由连接焊盘形成电阻器的需求，并且消除了经由图案化和刻蚀步骤分离电阻器的需求。在一种示例工艺中，利用添加一个光刻步骤，在集成电路中形成金属薄膜电阻器。
附图说明
图1(现有技术)是一种常规金属薄膜电阻器的横截面。
图2是金属薄膜电阻器的一种实施方式的横截面。
图3A至3E是例示根据实施方式形成的集成电阻器的制造中的步骤。
具体实施方式
图2是例示根据实施方式形成的金属薄膜电阻器。图2中的金属薄膜电阻器的实施方式不同于图1中的先前所描述的传统金属薄膜电阻器。在图2中通孔刻蚀停止层202在金属薄膜电阻器112上，并且没有通孔连接焊盘114保护金属薄膜电阻器112的端部。
较低层级互连104(在金属薄膜电阻器112下)被形成在电介质层106中。电介质层106和较低层级互连104被设置在电介质层102上，电介质层102在部分处理的集成电路100上。可以通过触点或通过互连的一个或更多个层级处理部分处理的集成电路。在较低层级互连104下的、通过电介质层102的触点/通孔101可以是用于基板的触点，或者可以是用于较低层级互连的通孔。刻蚀停止层108可以在较低层级互连104和电介质层106上。电介质110的薄层在刻蚀停止层108上。金属薄膜电阻器112被形成在电介质层110上。刻蚀停止层202覆盖金属薄膜电阻器112的上表面，并且在使用电阻器光致抗蚀剂图案刻蚀金属薄膜电阻器112之前进行刻蚀。厚电介质层116(层间电介质层或ILD)被形成在电介质层110上和刻蚀停止层202上。较高层级互连几何结构124被形成在ILD层116上。通孔118形成较高层级互连几何结构124和较低层级互连几何结构104之间的电连接。通孔120和通孔122形成较高层级互连几何结构和金属薄膜电阻器112的端部之间的电连接。金属薄膜电阻器112的顶部上的刻蚀停止层202使电阻器通孔120和电阻器通孔122与互连通孔118同时形成，而不会由于通孔过刻蚀而对金属薄膜电阻器造成损坏。
图3A至图3E例示一种使用一个附加光致抗蚀剂图案化步骤在集成电路中集成金属薄膜电阻器的方法。该工艺流程显著地降低了图1中的常规的三种光致抗刻蚀图案化工艺上的花费和周期时间。
非双嵌入式工艺流程被用于例示该方法。该方法容易适应于双嵌入式互连工艺流程。
图3A示出具有在集成电路100上的第一电介质层102的集成电路100。被嵌入在第二电介质层106中的较低互连几何结构104被形成在电介质层102上。较低互连几何结构104可以是铝、铝铜合金、加钛铝合金、或加氮化钛铝合金。较低互连几何结构还可以是使用双嵌入式工艺形成的铜。第一电介质层102和第二电介质层106可以是诸如使用等离子体激发化学气相沉积(PECVD)或等离子体激发TEOS沉积(PETEOS)沉积的二氧化硅等的电介质，或者可以是低k电介质。
然后，如图3B所示，可以沉积刻蚀停止层108，其后可以沉积薄电介质层110。刻蚀停止层108可以是诸如具有大约20nm至200nm范围内的厚度的SiN、SiON、SiC、或AI2O3等的电介质。电介质层110可以是诸如具有大约50nm至300nm之间的厚度的PECVD氧化物的电介质材料。然后，沉积诸如具有在大约1.5nm至40nm范围内的厚度的镍铬合金(NiCr)或铬硅合金(CrSi)等的电阻器材料310。可以使用诸如溅射等的物理气相沉积(PVD)来沉积电阻器材料310。然后，电阻器材料310被覆盖(cap)有刻蚀停止层312。刻蚀停止材料是诸如具有大约20nm至200nm范围内的厚度的SiN、SiON、SiC、或AI2O3等的电介质材料。在一个示例实施方式中，100nm SiN刻蚀停止层被沉积在3.5nm的CrSi上。然后，电阻器光致抗刻蚀图案314被形成在刻蚀停止层312上。
如图3C所示，刻蚀停止层312和电阻器材料310被刻蚀，以形成由刻蚀停止层几何结构202覆盖的电阻器几何结构112。然后，去除电阻器光致抗刻蚀图案314。在一个实施方式中，使用等离子体刻蚀将刻蚀停止层312和电阻器层310刻蚀。将可以是诸如PECVD二氧化硅或低k电介质等的IMD层116沉积和平坦化。然后，在ILD层116上形成具有用于互连通孔318及电阻器通孔320和电阻器通孔322的开口的通孔光致抗刻蚀图案316。
在图3D中，使用等离子体刻蚀将通孔318、通孔320和通孔322刻蚀，该等离子刻蚀利用对刻蚀停止层108和112的高选择性刻蚀二氧化硅。刻蚀电阻器通孔320和电阻器通孔322，且停止在刻蚀停止层202上。刻蚀互连通孔318，且停止在刻蚀停止层108上。在一种示例工艺流程中，IMD 116是二氧化硅，以及刻蚀停止层108和202是氮化硅。在通孔刻蚀的第一步骤中，利用对氮化硅的高选择性刻蚀二氧化硅。
参照图3E，改变通孔刻蚀化学物质，以将刻蚀停止层108和刻蚀停止层202刻蚀。从互连通孔318的底部将刻蚀停止层108刻蚀，以及从电阻器通孔320和322的底部将刻蚀停止层202刻蚀。因为刻蚀停止层108和刻蚀停止层202是薄的(在大约20nm至200nm的范围内)，所以仅需要短的通孔过刻蚀时间，以确保清除通孔318、通孔320和通孔322的底部。因为通孔过刻蚀时间是短的，所以在具有少量损坏的情况下，通孔刻蚀停止在薄膜金属电阻器112上。这确保通孔120和通孔122(图2)与金属薄膜电阻器112的端部之间的良好的电连接。然后，去除通孔光致抗刻蚀图案316。
然后，在集成电路上执行额外的处理，以利用诸如CVD-W或铜等的导电材料填充通孔318、通孔320和通孔322，以形成图2中的通孔插塞(via plug)118、通孔插塞120和通孔插塞122，以及在通孔插塞118、通孔插塞120和通孔插塞122上形成较高层级互连几何结构124。较高层级互连可以是诸如使用PVD沉积的硅铝合金、铜铝合金等的金属，或可以是使用电镀沉积的铜。
因此，在一种示例工艺中，通过仅添加一个额外的光致抗刻蚀图案，将金属薄膜电阻器添加至集成电路制造流程。
在权利要求范围内，可以在所描述的实施方式中进行修改，并且其它实施方式是可能的。

Claims (10)

1.一种集成电路，所述集成电路包括：
第一刻蚀停止层，所述第一刻蚀停止层被形成在较低层级互连几何结构上；
第一电介质层，所述第一电介质层在所述第一刻蚀停止层上方；
金属薄膜电阻器，所述金属薄膜电阻器在所述第一电介质层上方；
第二刻蚀停止层，所述第二刻蚀停止层在所述金属薄膜电阻器上方；
金属间电介质层，所述金属间电介质层在所述第一电介质层上方，并且在所述第二刻蚀停止层上方；
第一电阻器通孔，所述第一电阻器通孔将第一较高层级互连几何结构连接至所述金属薄膜电阻器的第一端部，所述第一电阻器通孔刻蚀通过所述ILD层；
第二电阻器通孔，所述第二电阻器通孔将第二较高层级互连几何结构连接至所述金属薄膜电阻器的第二端部，所述第二电阻器通孔刻蚀通过所述ILD层；以及
互连通孔，所述互连通孔通过所述ILD层、所述第一电介质层、和所述第一刻蚀停止层，将第三较高层级互连几何结构连接至所述较低互连几何结构。
2.根据权利要求1所述的集成电路，其中，所述金属薄膜电阻器几何结构是具有大约1.5nm至40nm的范围中的厚度的CrSi或NiCr。
3.根据权利要求1所述的集成电路，其中，所述金属薄膜电阻器几何结构是具有大约3.5nm的厚度的CrSi。
4.根据权利要求1所述的集成电路，其中，所述第一刻蚀停止层是从由具有大约20nm至200nm的范围中的厚度的SiN、SiON、SiC和Al2O3组成的组中选择的电介质，以及其中，所述第二刻蚀停止层是从由具有大约20nm至200nm的范围中的厚度的SiN、SiON、SiC和Al2O3组成的组中选择的电介质。
5.根据权利要求1所述的集成电路，其中，所述第一刻蚀停止层是具有大约20nm至200nm的范围中的厚度的SiN，以及其中，所述第二刻蚀停止层是具有大约20nm至200nm的范围中的厚度的SiN。
6.一种形成集成电路的方法，所述方法包括：
在较低互连几何结构上沉积第一刻蚀停止层；
在所述第一刻蚀停止层上沉积第一电介质层；
在所述第一电介质层上沉积金属薄膜电阻器材料；
在所述金属薄膜电阻器材料上沉积第二刻蚀停止层；
在所述第二刻蚀停止层上形成具有电阻器光致抗刻蚀几何结构的电阻器光致抗刻蚀图案；
刻蚀所述第二刻蚀停止层；
刻蚀所述金属薄膜电阻器材料，以形成金属薄膜电阻器；
去除所述电阻器光致抗刻蚀图案；
在所述第一电介质层上和所述第二刻蚀停止层上沉积金属间电介质层，即IMD层；
在所述IMD层上形成通孔光致抗刻蚀图案，其中具有：至少一个互连通孔开口、在所述金属薄膜电阻器的第一端部上的第一电阻器通孔开口、和在所述金属薄膜电阻器的第二端部上的第二电阻器通孔开口；
在所述互连通孔开口中刻蚀所述IMD电介质和刻蚀所述第一电介质层，且在所述第一刻蚀停止层上停止；以及在所述第一电阻器通孔开口中和在所述第二电阻器通孔开口中刻蚀所述IMD电介质，且在所述第二刻蚀停止层上停止，其中，所述刻蚀是第一等离子体刻蚀，其利用对所述第一刻蚀停止层的高选择性和对所述第二刻蚀停止层的高选择性；以及
在所述互连通孔开口中刻蚀所述第一刻蚀停止层，且停止在所述较低互连几何结构上，以及在所述第一电阻器通孔开口中和所述第二电阻器通孔开口中刻蚀所述第二刻蚀停止层，且在所述薄膜电阻器上停止，其中，所述刻蚀是第二等离子体刻蚀，其刻蚀所述第一刻蚀停止层和所述第二刻蚀停止层。
7.根据权利要求6所述的方法，其中，所述金属薄膜电阻器材料是具有1.5nm至40nm的范围中的厚度的NiCr或CrSi。
8.根据权利要求6所述的方法，其中，所述电阻器材料是具有大约3.5nm的厚度的CrSi。
9.根据权利要求6所述的方法，其中，所述第一刻蚀停止层是从由具有大约20nm至200nm的范围中的厚度的SiN、SiON、SiC和Al2O3组成的组中选择的电介质，以及其中，所述第二刻蚀停止层是从由具有大约20nm至200nm的范围中的厚度的SiN、SiON、SiC和Al2O3组成的组中选择的电介质。
10.根据权利要求6所述的方法，其中，所述第一刻蚀停止层是具有大约20nm至200nm的范围中的厚度的SiN，以及其中，所述第二刻蚀停止层是具有大约20nm至200nm的范围中的厚度的SiN。
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