CN105702658B - 半导体封装件及其制法 - Google Patents

半导体封装件及其制法 Download PDF

Info

Publication number
CN105702658B
CN105702658B CN201410679766.7A CN201410679766A CN105702658B CN 105702658 B CN105702658 B CN 105702658B CN 201410679766 A CN201410679766 A CN 201410679766A CN 105702658 B CN105702658 B CN 105702658B
Authority
CN
China
Prior art keywords
semiconductor package
electronic component
package part
layer
preparation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410679766.7A
Other languages
English (en)
Other versions
CN105702658A (zh
Inventor
蒋静雯
邱承浩
吴政洁
陈光欣
陈贤文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN105702658A publication Critical patent/CN105702658A/zh
Application granted granted Critical
Publication of CN105702658B publication Critical patent/CN105702658B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82031—Reshaping, e.g. forming vias by chemical means, e.g. etching, anodisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/37—Effects of the manufacturing process
    • H01L2924/37001—Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Chemical & Material Sciences (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种半导体封装件及其制法，该半导体封装件包括：绝缘槽体，其具有相对的第一表面与第二表面，且该第一表面上具有开口；绝缘片体，其自该绝缘槽体的第一表面的边缘延伸，且该绝缘片体的厚度小于该绝缘槽体的厚度；电子元件，其设于该开口中，且该电子元件具有相对的作用侧与非作用侧；介电层，其设于该绝缘槽体的第一表面、该绝缘片体与该电子元件的作用侧上、及该开口中；以及线路层，其设于该介电层上并电性连接该电子元件。藉由该绝缘层的设计，能增加该半导体封装件的整体结构的刚性。

Description

半导体封装件及其制法
技术领域
本发明涉及一种半导体封装件，尤指一种具晶圆级线路的半导体封装件及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于晶片封装领域的技术，例如晶片尺寸构装(Chip Scale Package,CSP)、晶片直接贴附封装(Direct Chip Attached,DCA)或多晶片模组封装(Multi－Chip Module,MCM)等覆晶型态的封装模组、或将晶片立体堆迭化整合为三维积体电路(3D IC)晶片堆迭技术等。
图1为现有半导体封装件1的剖面示意图，该半导体封装件1通过于一封装基板18与半导体晶片11的间设置一硅中介板(Through Silicon interposer,TSI)10，该硅中介板10具有导电硅穿孔(Through-silicon via,TSV)100及设于该导电硅穿孔100上的线路重布结构(Redistribution layer,RDL)15，令该线路重布结构15藉由多个导电元件17电性结合间距较大的封装基板18的焊垫180，并形成黏着材12包覆该些导电元件17，而间距较小的半导体晶片11的电极垫110藉由多个焊锡凸块19电性结合该导电硅穿孔100。之后，再形成黏着材12包覆该些焊锡凸块19。
若该半导体晶片11直接结合至该封装基板18上，因半导体晶片11与封装基板18两者的热膨胀系数的差异甚大，所以半导体晶片11外围的焊锡凸块19不易与封装基板18上对应的焊垫180形成良好的接合，致使焊锡凸块19自封装基板18上剥离。另一方面，因半导体晶片11与封装基板18之间的热膨胀系数不匹配(mismatch)，其所产生的热应力(thermalstress)与翘曲(warpage)的现象也日渐严重，致使半导体晶片11与封装基板18之间的电性连接可靠度(reliability)下降，且将造成信赖性测试的失败。
因此，藉由半导体基材制作的硅中介板10的设计，其与该半导体晶片11的材质接近，所以可有效避免上述所产生的问题。
惟，前述现有半导体封装件1的制法中，于制作该硅中介板10时，需形成该导电硅穿孔100，而该导电硅穿孔100的制程需于该硅中介板10上挖孔及金属填孔，致使该导电硅穿孔100的整体制程占整个该硅中介板10的制作成本达约40～50％(以12寸晶圆为例，不含人工成本)，以致于最终产品的成本及价格难以降低。
此外，该硅中介板10的制作技术难度高，致使该半导体封装件1的生产量相对降低，且制作良率降低。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种半导体封装件及其制法，能增加该半导体封装件的整体结构的刚性。
本发明的半导体封装件，包括：绝缘槽体，其具有相对的第一表面与第二表面，且该第一表面上具有开口；绝缘片体，其自该绝缘槽体的第一表面的边缘向外延伸，且该绝缘片体的厚度小于该绝缘槽体的厚度；电子元件，其设于该开口中，且该电子元件具有相对的作用侧与非作用侧；介电层，其形成于该绝缘槽体的第一表面、该绝缘片体与该电子元件的作用侧上、及该开口中；以及线路层，其设于该介电层上并电性连接该电子元件。
前述的半导体封装件中，该绝缘片体为与该绝缘槽体一体成形。
本发明还提供一种半导体封装件的制法，包括：提供一具有凹部的承载件，且该承载件的表面与该凹部的表面上形成有一绝缘层；置放至少一电子元件于该凹部中的绝缘层上；形成介电层于该绝缘层与电子元件上，以令该介电层包覆该电子元件；形成线路层于该介电层上，并与该电子元件电性连接；以及移除该承载件，以外露该绝缘层。
前述的制法中，该承载件为含硅的板体。
前述的制法中，是以湿蚀刻方式移除该承载件，且蚀刻至该绝缘层。
前述的制法中，该承载件具有多个该凹部，以于移除该承载件后，进行切单制程。
前述的半导体封装件及制法中，形成该绝缘层(或绝缘槽体、绝缘片体)的材质为氧化硅或氮化硅。
前述的半导体封装件及制法中，该电子元件以其非作用侧藉由结合层结合至该凹部(或该开口)中。
前述的半导体封装件及制法中，于移除该承载件后，移除该绝缘槽体的第二表面的部分材质与该结合层，使该电子元件的非作用侧外露于该绝缘槽体的第二表面。
前述的半导体封装件及制法中，该介电层的材质不同于该绝缘层的材质。
前述的半导体封装件及制法中，复包括于移除该承载件后，移除该绝缘片体的部分材质，使该线路层外露于该绝缘片体。
前述的半导体封装件及制法中，复包括形成线路重布结构于该介电层与该线路层上，且该线路重布结构电性连接该线路层。又包括于移除该承载件后，结合封装基板至该线路重布结构上，且该线路重布结构电性连接该封装基板。
另外，前述的半导体封装件及制法中，复包括于移除该承载件后，结合封装基板至该线路层上，且该线路层电性连接该封装基板。
由上可知，本发明的半导体封装件及其制法，藉由该绝缘层的设计，能增加该半导体封装件的整体结构的刚性，不仅能降低该介电层的厚度，并可避免于制程中因升温或降温而发生热翘曲的现象。
此外，本发明因无需制作现有硅中介板的方式，所以不仅能大幅降低该半导体封装件的制作成本，且能简化制程，使该半导体封装件的生产量提高及提高制作良率。
附图说明
图1为现有半导体封装件的剖面示意图；
图2A至2H为本发明的半导体封装件的制法的第一实施例的剖面示意图；其中，图2B’及2B”为图2B的其它实施例，图2G’及2G”为图2G的其它实施例，图2H’及2H”为图2H的其它实施例；以及
图3A至3B为本发明的半导体封装件的制法的第二实施例的剖面示意图。
主要组件符号说明
1、2、2’、2”、3 半导体封装件
10 硅中介板
100 导电硅穿孔
11 半导体晶片
110、210 电极垫
12 黏着材
15、25 线路重布结构
17、27 导电元件
18、28 封装基板
180 焊垫
19 焊锡凸块
20 承载件
200 凹部
21、21’ 电子元件
21a 作用侧
21b 非作用侧
211 结合层
212 结合材
212a、212b 晶片
22 绝缘层
23 介电层
230 盲孔
24、34 线路层
240 导电盲孔
250 介电部
251 线路部
26 绝缘保护层
260 开孔
32 绝缘槽体
32a 第一表面
32b、32b’ 第二表面
320 开口
340 导电体
37 导电凸块
42 绝缘片体
S 切割路径
T、t、m、h、L 厚度
d 深度。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”及“一”等的用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至2H为本发明的半导体封装件2的制法的第一实施例的剖面示意图。
如图2A所示，提供一具有多个凹部200的承载件20，且该承载件20的表面与该凹部200的表面上形成有一绝缘层22。
于本实施例中，该承载件20为含硅的板体，且形成该绝缘层22的材质为氧化硅(SiO2)或氮化硅(SixNy)。
此外，该凹部200的深度d至多为该承载件20的厚度T的一半。
如图2B所示，置放多个电子元件21于该凹部200中的绝缘层22上。
于本实施例中，该电子元件21具有相对的作用侧21a与非作用侧21b，该作用侧21a具有多个电极垫210，且该非作用侧21b藉由一结合层211将该电子元件21结合至该绝缘层22上，并使该电子元件21未凸伸出该凹部200。其中，该电子元件21的厚度t为10至300微米(um)，较佳为20至150微米，而该结合层211的厚度m为5至25微米。
此外，于其它实施例中，如图2B’所示，该电子元件21亦可凸伸出该凹部200。
又，该结合层211为如晶片绝缘层(die attach film，简称DAF)，其可先形成于该电子元件21的非作用侧21b，再将该电子元件21置放于该凹部200中；或者，该结合层211亦可先形成于该凹部200中(如图2B”所示的点胶方式)，再将该电子元件21结合至该凹部200中的结合层211上。
另外，该电子元件21为主动元件、被动元件或其组合者，且该主动元件例如为半导体晶片，而该被动元件例如为电阻、电容及电感。于此，该电子元件21为如单一晶片结构的主动元件，且于一凹部200中置放两个电子元件21，但不限于置放两个电子元件21。
于其它实施例中，如图2B”所示，该电子元件21’亦可为如多晶片模组的主动元件，例如，先将两晶片212a,212b以结合材212(如环氧树脂)相结合成一模组，再将该模组置放于该凹部200中。
如图2C所示，接续图2B的制程，形成一介电层23于该绝缘层22与电子元件21上，且形成多个盲孔230于该介电层23中，以令该些电极垫210外露于该些盲孔230。
于本实施例中，该介电层23填入该凹部200中，以令该介电层23包覆该电子元件21。
再者，形成该介电层23的材质为感光材、聚酰亚胺(Polyimide，简称PI)、聚对二唑苯(Polybenzoxazole，简称PBO)或苯环丁烯(Benzocyclclobutene，简称BCB)，所以形成该介电层23的材质不同于该绝缘层22的材质。
又，可藉由化学(如蚀刻)或物理(如激光开孔)方式形成该些盲孔230。
如图2D所示，形成一线路层24于该介电层23上，且形成导电盲孔240于该盲孔230中，使该线路层24藉由该些导电盲孔240电性连接该电子元件21的电极垫210。
于本实施例中，该线路层24为晶圆级线路，而非封装基板级线路，其中，该封装基板级线路的最小的线宽与线距为12μm，而半导体制程能制作出3μm以下的线宽与线距的晶圆级线路。
如图2E所示，进行线路重布层(Redistribution layer，简称RDL)制程，即形成一线路重布结构25于该介电层23与该线路层24上，且该线路重布结构25电性连接该线路层24。
于本实施例中，该线路重布结构25包含相迭的介电部250、线路部251及绝缘保护层26，且该绝缘保护层26形成有多个开孔260，令该线路部251外露于各该开孔260，以供结合如焊球的导电元件27。
如图2F所示，移除该承载件20，以外露该绝缘层22。
于本实施例中，以湿蚀刻方式移除该承载件20，且该绝缘层22可作为止蚀层，所以蚀刻至该绝缘层22，其中，蚀刻液可为氢氧化四甲基铵(TMAH)或氢氧化钾(KOH)蚀刻液。
如图2G所示，沿如图2F所示的切割路径S进行切单制程，以形成本发明的其中一种半导体封装件2的实施例。
于本实施例中，该绝缘层22定义有一绝缘槽体32与一绝缘片体42，该绝缘槽体32具有相对的第一表面32a与第二表面32b，该第一表面32a具有已设置该电子元件21的一开口320，且该绝缘片体42自该绝缘槽体32的第一表面32a的边缘延伸，而该绝缘片体42的厚度h小于该绝缘槽体32的厚度L。
此外，也可如图2G’所示，于进行切单制程后，移除该绝缘槽体32的第二表面32b的部分材质与该结合层211，使该电子元件21的非作用侧21b外露于该绝缘槽体32的第二表面32b’。
又，若接续图2B’的制程，将得到如图2G”所示的半导体封装件2”。
如图2H所示，接续图2G的制程，藉由该些导电元件27结合一封装基板28至该线路重布结构25上，且该线路重布结构25的线路部251电性连接该封装基板28。
此外，如图2H’所示，其为接续图2D所示的制程，于形成该线路层24后，未形成介电部250与线路部251，而形成该绝缘保护层26于该线路层24上，且该绝缘保护层26形成有外露该线路层24的多个开孔260，以形成该些导电元件27于该线路层24的外露处上，再进行切单制程，之后藉由该些导电元件27结合该封装基板28至该线路层24上，且该线路层24电性连接该封装基板28。
又，如图2H”所示，其为接续图2B”的制程。
图3A至3B为本发明的半导体封装件3的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于该绝缘片体的制程，其它步骤的制程大致相同，所以不再赘述相同处。
如图3A所示，于制作该线路层24时，于该绝缘片体42上形成部分线路层34，且该线路层34于该介电层23中形成有导电体340，以于移除该承载件20后，移除该绝缘片体42的部分材质，使该线路层34的导电体340外露于该绝缘片体42。
如图3B所示，形成多个导电凸块37于该导电体340的外露处上，以供结合如半导体晶片的电子装置(图略)。
本发明的制法中，由于该介电层23的材质为感光材、PI、PBO或BCB，所以通常需有一定的厚度以具较佳的机械性质(如结构强度)而足以包覆该电子元件21,21’，且该介电层23与该封装基板28的CTE值差异过大，以致于在接合该封装基板28并进行其它高温制程时，容易因CTE不匹配而造成翘曲(warpage)的问题。
因此，本发明藉由该绝缘层22的设计以得到较强的结构，使本发明的半导体封装件2,2’,2”,3不仅能降低该介电层23的厚度，并可避免于制程中因升温或降温而发生热翘曲的现象。
此外，本发明的制法因无需制作现有硅中介板，所以不仅能大幅降低该半导体封装件2,2’,2”,3的制作成本，且能简化制程，使该半导体封装件的生产量提高及提高制作良率。
又，本发明的半导体封装件2,2’,2”,3因无现有硅中介板，所以相较于现有具硅中介板的封装件，本发明的半导体封装件2,2’,2”,3能使最终产品的整体厚度较薄。
另外，本发明的半导体封装件2,2’,2”,3的电子元件21,21’无需经由现有硅中介板做讯号转接传输，所以该电子元件21,21’的传输速度更快。
本发明提供一种半导体封装件2,2’,2”,3，包括：一绝缘槽体32、一绝缘片体42、至少一电子元件21,21’、一介电层23、以及设于该介电层23上的一线路层24,34。
所述的绝缘槽体32具有相对的第一表面32a与第二表面32b，且该第一表面32a上具有开口320。
所述的绝缘片体42自该绝缘槽体32的第一表面32a的边缘向外延伸，且该绝缘片体42的厚度h小于该绝缘槽体32的厚度L。
所述的电子元件21,21’为主动元件、被动元件或其组合者，其设于该开口320中，且该电子元件21,21’具有相对的作用侧21a与非作用侧21b。
所述的介电层23设于该绝缘槽体32的第一表面32a、该绝缘片体42与该电子元件21,21’的作用侧21a上、及该开口320中，且该介电层23的材质不同于该绝缘槽体32的材质与该绝缘片体42的材质。
所述的线路层24,34具有位于该介电层23中的多个导电盲孔240，以藉其电性连接该电子元件21,21’。
于一实施例中，该绝缘片体42与该绝缘槽体32一体成形。
于一实施例中，该电子元件21,21’的非作用侧21b藉由结合层211结合至该开口320上。
于一实施例中，该电子元件21的非作用侧21b外露于该绝缘槽体32的第二表面32b’。
于一实施例中，该线路层34具有穿过该介电层23的导电体340，且该导电体340外露于该绝缘片体42。
于一实施例中，所述的半导体封装件2,2’,2”,3还包括一线路重布结构25，设于该介电层23与该线路层24,34上并电性连接该线路层24,34，且又包括一设于该线路重布结构25上并电性连接该线路重布结构25的封装基板28。
于一实施例中，所述的半导体封装件2,2’,2”,3复包括一设于该线路层24上并电性连接该线路层24,34的封装基板28。
综上所述，本发明的半导体封装件及其制法，主要藉由该绝缘层的设计，能增加该半导体封装件的整体结构的刚性，不仅能降低该介电层的厚度，并可避免于制程中因升温或降温而发生热翘曲的现象。
此外，无需制作现有硅中介板的方式，不仅能大幅降低该半导体封装件的制作成本，且能简化制程，使该半导体封装件的生产量提高及提高制作良率。
又，本发明的半导体封装件因无现有硅中介板的结构，所以能使最终产品的整体厚度较薄，且能使该电子元件的传输速度更快。
另外，藉由该承载件为含硅材质的设计，以避免该承载件发生翘曲的现象。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (19)

1.一种半导体封装件，包括：
绝缘槽体，其具有相对的第一表面与第二表面，且该第一表面上具有开口；
绝缘片体，其自该绝缘槽体的第一表面的边缘向外延伸，且该绝缘片体的厚度小于该绝缘槽体的厚度；
电子元件，其设于该开口中，且该电子元件具有相对的作用侧与非作用侧，该电子元件的非作用侧通过结合层结合至该开口上；
介电层，其形成于该绝缘槽体的第一表面、该绝缘片体与该电子元件的作用侧上、及该开口中，以包覆该电子元件；以及
线路层，其设于该介电层上并电性连接该电子元件。
2.如权利要求1所述的半导体封装件，其特征为，形成该绝缘槽体的材质为氧化硅或氮化硅。
3.如权利要求1所述的半导体封装件，其特征为，形成该绝缘片体的材质为氧化硅或氮化硅。
4.如权利要求1所述的半导体封装件，其特征为，该绝缘片体为与该绝缘槽体一体成形。
5.如权利要求1所述的半导体封装件，其特征为，该电子元件的非作用侧外露于该绝缘槽体的第二表面。
6.如权利要求1所述的半导体封装件，其特征为，该线路层穿过该介电层而外露于该绝缘片体。
7.如权利要求1所述的半导体封装件，其特征为，该半导体封装件还包括线路重布结构，其设于该介电层与该线路层上并电性连接该线路层。
8.如权利要求7所述的半导体封装件，其特征为，该半导体封装件还包括封装基板，其设于该线路重布结构上并电性连接该线路重布结构。
9.如权利要求1所述的半导体封装件，其特征为，该半导体封装件还包括封装基板，其设于该线路层上并电性连接该线路层。
10.一种半导体封装件的制法，包括：
提供一具有凹部的承载件，且该承载件的表面与该凹部的表面上形成有一绝缘层；
置放至少一电子元件于该凹部中的绝缘层上，该电子元件具有相对的作用侧与非作用侧，且该电子元件以其非作用侧通过结合层结合至该凹部；
形成介电层于该绝缘层与电子元件上，以令该介电层包覆该电子元件；
形成线路层于该介电层上，并与该电子元件电性连接；以及
移除该承载件，以外露该承载件的表面与该凹部的表面上的该绝缘层。
11.如权利要求10所述的半导体封装件的制法，其特征为，该承载件为含硅的板体。
12.如权利要求10所述的半导体封装件的制法，其特征为，该承载件具有多个该凹部，以于移除该承载件后，进行切单制程。
13.如权利要求10所述的半导体封装件的制法，其特征为，形成该绝缘层的材质为氧化硅或氮化硅。
14.如权利要求10所述的半导体封装件的制法，其特征为，是以湿蚀刻方式移除该承载件，且蚀刻至该绝缘层。
15.如权利要求10所述的半导体封装件的制法，其特征为，该半导体封装件还包括于移除该承载件后，移除该绝缘层的部分材质与该结合层，使该电子元件的非作用侧外露于该绝缘层。
16.如权利要求10所述的半导体封装件的制法，其特征为，该半导体封装件还包括于移除该承载件后，移除该绝缘层的部分材质，使该线路层外露于该绝缘层。
17.如权利要求10所述的半导体封装件的制法，其特征为，该半导体封装件还包括形成线路重布结构于该介电层与该线路层上，且该线路重布结构电性连接该线路层。
18.如权利要求17所述的半导体封装件的制法，其特征为，该半导体封装件还包括于移除该承载件后，结合封装基板至该线路重布结构上，且该线路重布结构电性连接该封装基板。
19.如权利要求10所述的半导体封装件的制法，其特征为，该半导体封装件还包括于移除该承载件后，结合封装基板至该线路层上，且该线路层电性连接该封装基板。
CN201410679766.7A 2014-11-12 2014-11-24 半导体封装件及其制法 Active CN105702658B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW103139187A TWI557853B (zh) 2014-11-12 2014-11-12 半導體封裝件及其製法
TW103139187 2014-11-12

Publications (2)

Publication Number Publication Date
CN105702658A CN105702658A (zh) 2016-06-22
CN105702658B true CN105702658B (zh) 2019-04-05

Family

ID=55912840

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410679766.7A Active CN105702658B (zh) 2014-11-12 2014-11-24 半导体封装件及其制法

Country Status (3)

Country Link
US (2) US9627307B2 (zh)
CN (1) CN105702658B (zh)
TW (1) TWI557853B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9379041B2 (en) * 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
TWI550783B (zh) * 2015-04-24 2016-09-21 矽品精密工業股份有限公司 電子封裝件之製法及電子封裝結構
US11189576B2 (en) 2016-08-24 2021-11-30 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US20180166356A1 (en) * 2016-12-13 2018-06-14 Globalfoundries Inc. Fan-out circuit packaging with integrated lid
CN107331627A (zh) * 2017-07-03 2017-11-07 京东方科技集团股份有限公司 一种芯片封装方法及芯片封装结构
CN113571494A (zh) * 2020-04-28 2021-10-29 群创光电股份有限公司 电子装置及其制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1384979A (zh) * 1999-02-08 2002-12-11 格姆普拉斯公司 用于生产芯片卡便携存储介质的方法
US6709898B1 (en) * 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
CN1971864A (zh) * 2005-11-25 2007-05-30 全懋精密科技股份有限公司 半导体芯片埋入基板的结构及制法
CN103219297A (zh) * 2012-01-20 2013-07-24 矽品精密工业股份有限公司 承载板、半导体封装件及其制法
TW201444047A (zh) * 2013-05-10 2014-11-16 矽品精密工業股份有限公司 半導體封裝件及其製法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6586822B1 (en) * 2000-09-08 2003-07-01 Intel Corporation Integrated core microelectronic package
CN100561696C (zh) * 2007-03-01 2009-11-18 全懋精密科技股份有限公司 嵌埋半导体芯片的结构及其制法
CN101295650A (zh) * 2007-04-25 2008-10-29 矽品精密工业股份有限公司 半导体装置及其制法
CN101295651A (zh) * 2007-04-26 2008-10-29 矽品精密工业股份有限公司 半导体装置及其制法
JP5224845B2 (ja) * 2008-02-18 2013-07-03 新光電気工業株式会社 半導体装置の製造方法及び半導体装置
TWI387074B (zh) * 2008-06-05 2013-02-21 Chipmos Technologies Inc 晶粒堆疊結構及其形成方法
US7863096B2 (en) * 2008-07-17 2011-01-04 Fairchild Semiconductor Corporation Embedded die package and process flow using a pre-molded carrier
JP5325736B2 (ja) * 2009-10-06 2013-10-23 新光電気工業株式会社 半導体装置及びその製造方法
TWI418269B (zh) * 2010-12-14 2013-12-01 Unimicron Technology Corp 嵌埋穿孔中介層之封裝基板及其製法
TWI492680B (zh) * 2011-08-05 2015-07-11 Unimicron Technology Corp 嵌埋有中介層之封裝基板及其製法
US8828802B1 (en) * 2011-11-01 2014-09-09 Amkor Technology, Inc. Wafer level chip scale package and method of fabricating wafer level chip scale package
CN103579145B (zh) * 2012-08-10 2017-12-08 欣兴电子股份有限公司 穿孔中介板及其制法与封装基板及其制法
TWI503928B (zh) * 2012-09-10 2015-10-11 矽品精密工業股份有限公司 半導體封裝件及其製法與中介板結構
TWI483365B (zh) * 2012-09-26 2015-05-01 Ind Tech Res Inst 封裝基板及其製法
TWI497616B (zh) * 2012-11-08 2015-08-21 矽品精密工業股份有限公司 半導體封裝件之製法
US9318404B2 (en) * 2013-02-05 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming stress relieving vias for improved fan-out WLCSP package
TWI607534B (zh) * 2013-04-19 2017-12-01 精材科技股份有限公司 晶片封裝體及其製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1384979A (zh) * 1999-02-08 2002-12-11 格姆普拉斯公司 用于生产芯片卡便携存储介质的方法
US6709898B1 (en) * 2000-10-04 2004-03-23 Intel Corporation Die-in-heat spreader microelectronic package
CN1971864A (zh) * 2005-11-25 2007-05-30 全懋精密科技股份有限公司 半导体芯片埋入基板的结构及制法
CN103219297A (zh) * 2012-01-20 2013-07-24 矽品精密工业股份有限公司 承载板、半导体封装件及其制法
TW201444047A (zh) * 2013-05-10 2014-11-16 矽品精密工業股份有限公司 半導體封裝件及其製法

Also Published As

Publication number Publication date
CN105702658A (zh) 2016-06-22
US20160133556A1 (en) 2016-05-12
TWI557853B (zh) 2016-11-11
US20170186703A1 (en) 2017-06-29
TW201618246A (zh) 2016-05-16
US9627307B2 (en) 2017-04-18
US9748183B2 (en) 2017-08-29

Similar Documents

Publication Publication Date Title
CN105702658B (zh) 半导体封装件及其制法
KR101830904B1 (ko) 리세스된 반도체 기판
TWI514542B (zh) 具有圍繞矽穿封裝孔（ＴＰＶ）的末端部分之開口的晶粒封裝及使用該晶粒封裝之層疊封裝（ＰｏＰ）
TWI582913B (zh) 半導體封裝件及其製法
KR102649471B1 (ko) 반도체 패키지 및 그의 제조 방법
TWI570842B (zh) 電子封裝件及其製法
TWI541954B (zh) 半導體封裝件及其製法
TWI544599B (zh) 封裝結構之製法
US9786610B2 (en) Semiconductor package and fabrication method thereof
CN106206463B (zh) 电子封装件的制法及电子封装结构
TW201640590A (zh) 電子封裝件及其製法
TW201543622A (zh) 半導體封裝件及其製法與承載結構
TWI574333B (zh) 電子封裝件及其製法
TW201707174A (zh) 電子封裝件及其製法
TWI566349B (zh) 封裝結構及其製法
TWI515841B (zh) 半導體封裝件及其製法
CN104733407B (zh) 半导体装置的制法
TWI566354B (zh) 中介板及其製法
TWI574356B (zh) 半導體封裝件之製法
TWI556363B (zh) 半導體裝置及其製法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant