CN105702657B - 用于表面贴装半导体器件的改进的封装及其制造方法 - Google Patents
用于表面贴装半导体器件的改进的封装及其制造方法 Download PDFInfo
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- CN105702657B CN105702657B CN201510591929.0A CN201510591929A CN105702657B CN 105702657 B CN105702657 B CN 105702657B CN 201510591929 A CN201510591929 A CN 201510591929A CN 105702657 B CN105702657 B CN 105702657B
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Abstract
本发明涉及用于表面贴装半导体器件的改进的封装及其制造方法。一种表面贴装电子器件包括:半导体材料的本体(20)、形成多个接触端子(70)的引线框架(4);覆盖半导体本体(20)的封装电介质区域(69)。每个接触端子(70)包括由封装电介质区域(69)上覆的内部部分以及在侧向上凸出到封装电介质区域(69)之外并且通过第一侧向表面(Sflank1)界定的外部部分。对于每个接触端子(70)器件进一步包括在对应的第一侧向表面(Sflank1)之上延伸的抗氧化区域(60)。
Description
技术领域
本发明涉及一种用于表面贴装半导体器件的改进的封装,还涉及它的制造方法。
背景技术
众所周知,诸如例如集成电路和MEMS器件的半导体器件封装在执行保护功能并且与外部世界进行接口的对应的封装内。例如,在印刷电路板上实现所谓的“表面贴装”的封装是已知的。
更详细地,表面贴装封装包括,例如,所谓的“方形扁平无引线封装”(QFN)类型的封装,也被称为“微引线框架”(MLF)封装或“小外形无引线”(SON)封装。
一般来说,QFN封装包括树脂的区域,包在树脂内的是引线框架,该引线框架又形成散发到封装的底面上的至少一个端子阵列。
QFN封装的特征在于小尺寸以及好的电和热性能;然而,检查已经正确执行了印刷电路板上的焊接经常成问题。实际上,端子和印刷电路板的对应的焊盘之间存在的焊接点(weld)的目检正是被封装的底面上的端子的布置所阻碍。在这点上,文件号US2005/0116321描述了一种用于制造封装的方法,其中端子通过冲压形成使得呈现面向印刷电路板的凹槽。以这种方式,端子形成了在焊膏的施加的操作期间依然暴露的表面。进一步地,封装使得当它被焊接在印刷电路板上时,对应的焊点(soldering joint)呈现在封装的端子和印刷电路板的焊盘之间,该焊点可以以相对容易的方式注意和目检。然而,每个焊点可见的角度不是特别宽,另一方面每个端子的可焊区域也不是特别宽。
发明内容
因此本发明的目的是提供将至少部分解决现有技术的缺点的用于半导体器件的封装。
根据本发明,提供了一种表面贴装电子器件,其包括:半导体材料的本体;形成多个接触端子的引线框架;以及覆盖半导体本体的封装电介质区域;并且其中每个接触端子包括由封装电介质区域覆盖的内部部分和在侧向上凸出到封装电介质区域之外并且通过第一侧向表面界定的外部部分,对于每个接触端子,该器件进一步包括:在对应的第一侧向表面上延伸的抗氧化区域。
根据本发明,还提供了一种用于制造表面贴装电子器件的方法,该方法包括以下步骤:执行组件的第一局部切割,该组件至少包括一个第一裸片焊盘和一个第二裸片焊盘以及分别布置在第一裸片焊盘和第二裸片焊盘的顶上的至少一个第一半导体本体和一个第二半导体本体,该组件进一步包括布置在第一裸片焊盘和第二裸片焊盘之间的多个端子区域以及覆盖第一半导体本体和第二半导体本体和端子区域的电介质区域,每个端子区域通过彼此相对的第一区域表面和第二区域表面界定,第一区域表面面对电介质区域,从相应的第二区域表面开始进行第一切割使得去除端子区域中的每个端子区域的一部分,使得端子区域形成凹槽的横向壁和第一侧壁和第二侧壁;利用抗氧化层涂覆由每个端子区域形成的第一侧壁和第二侧壁;以及从电介质区域开始执行组件的第二局部切割以便针对每个端子区域去除形成对应的横向壁的相应顶部部分,并且将第一半导体本体和第二半导体本体分离;并且其中第二切割具有大于第一切割的宽度的宽度。
附图说明
为了更好地理解本发明,现在仅通过非限制性示例的方式并且参考附图描述它的优选的实施例,其中:
-图1a是引线框架带的示意俯视平面图;
-图1b示出了图1a中所示的引线框架带的一部分的放大图;
-图2到图5、图7、图9和图11是示意横截面图,示出了根据本半导体器件的一个实施例的封装方法的连续步骤;
-图6是图5中所示的一部分的放大的示意图;
-图8是图7中所示的一部分的放大的示意图;
-图10是电子器件的示意侧视图;以及
-图12和图13是示意横截面图,示出了本封装方法的变形例的连续的步骤。
具体实施方式
图1a仅以示例的方式示出了引线框架带2,该引线框架带2是本身已知的类型的,并且是导电材料(例如,铜)的。引线框架带2包括多个器件区域4,多个器件区域4中的每个器件区域又包括在图1b更详细地示出的相应的裸片焊盘6。此外,引线框架带2包括多个接触区域8。
尽管如此,图2示出了组件3,该组件3仅以示例的方式包括引线框架带2并且特别地包括第一器件区域和第二器件区域,第一器件区域和第二器件区域分别由4'和4"指定并且分别包括分别由6'和6"指定的第一裸片焊盘和第二裸片焊盘。进一步地,组件3包括由8'指定的接触区域,该接触区域在第一裸片焊盘6'和第二裸片焊盘6"之间距其一定距离处延伸。接触区域8'的顶表面以及第一裸片焊盘6'和第二裸片焊盘6"的顶表面限定第一表面S1,而接触区域8'的底表面以及第一裸片焊盘6'和第二裸片焊盘6"的底表面限定第二表面S2。
不失一般性,引线框架带2是所谓的“预镀”类型的,并且因此包括例如由锡制成的第一涂覆层14和第二涂覆层16。
第一涂覆层14在第一表面S1之上延伸,并且因此在与其直接接触的接触区域8'以及第一裸片焊盘6'和第二裸片焊盘6"之上延伸。第二涂覆层16在第二表面S2下方延伸,并且因此在与其直接接触的接触区域8'以及第一裸片焊盘6'和第二裸片焊盘6"的下方延伸。
更特别地,第一涂覆层14包括在下文中将被称为“第一焊盘部 分140”、“第二焊盘部分144”和“接触部分142”的第一部分、第二部分和第三部分。第一涂覆层14的第一焊盘部分140、第二焊盘部分144和接触部分142分别在第一裸片焊盘6'、第二裸片焊盘6"和接触区域8'上延伸。
第二涂覆层16包括在下文中将被称为“第一焊盘部分160”、“第二焊盘部分164”和“接触部分162”的第一部分、第二部分和第三部分。第二涂覆层16的第一焊盘部分160、第二焊盘部分164和接触部分162分别在第一裸片焊盘6'、第二裸片焊盘6"和接触区域8'下方延伸。
组件3进一步包括第一裸片20和第二裸片22,第一裸片20和第二裸片22分别通过插入第一键合层24和第二键合层26分别固定到第一涂覆层14的第一焊盘部分140和第二焊盘部分144。
进一步地,组件3包括第一导线30和第二导线32。第一导线30将第一裸片20电连接到第一涂覆层14的接触部分142,它与接触部分142形成第一接线键合。第二导线32将第二裸片22电连接到第一涂覆层14的接触部分142,它与接触部分142形成第二接线键合。
组件3可以在先以本身已知的方式形成并且进一步包括例如由热固性的环氧树脂制成的所谓的“模制化合物”36,并且以本身已知的方式覆盖第一裸片20和第二裸片22以及引线框架带2直到它至少部分地在第一裸片焊盘6'和第二裸片焊盘6"和接触区域8'之间存在的间隙中延伸。在下文中模制化合物36将被称为“树脂区域36”。进一步地,树脂区域36在顶部通过在下文中将被称为“第三表面S3”的相应表面S3界定。
尽管如此,如图3中所示,根据本制造方法执行了选择性的去除引线框架带2的一部分。在下文中特别参考在接触区域8'中产生的效果来描述该去除以及后续的步骤,除非另外指明。
详细地,使用至少具有局部矩形横截面的第一刀片40进行第一局部切割。该第一切割从第二涂覆层16的接触部分162开始,从下方进行,用于去除该接触部分162的一部分和接触区域8'的上覆部分。
更详细地,如果w是接触区域8'的厚度,则第一切割使得接触区域8'的去除部分具有厚度k<w,例如k=w·0.8。
在实践中,也如在图4中所示,第一切割使得在接触区域8'内形成凹槽R。在凹槽R的顶部上延伸的是接触区域8'的未去除部分,该未去除部分在下文中将被称为“剩余区域45”。剩余区域45具有等于w-k的厚度。应当注意,凹槽R是这样的凹槽,该凹槽还穿过形成接触区域8'所属的阵列的其他接触区域8延伸,并且穿过树脂区域36的布置在其间的部分之间延伸。然而,为了简化描述,也特别参考由接触区域8'形成的部分来描述凹槽R。
凹槽R在侧向上通过第一侧壁L1和第二侧壁L2界定,这两个侧壁由接触区域8'以及在较小程度上由第二涂覆层16的接触部分162形成。此外,凹槽R在顶部通过由剩余区域45形成的顶壁T界定。
更详细地,第一侧壁L1和第二侧壁L2相互平行。进一步地,在与第一切割的方向垂直的方向上测量,凹槽R具有宽度l。在实践中,第一侧壁L1和第二侧壁L2与彼此相隔等于宽度l的距离。
接下来,如图5所示并且在图6中更详细地示出的,执行镀制工艺,在下文中特别参考接触区域8'上产生的效果来对其进行描述。
详细地,如果将第二涂覆层16的底表面指定为“第四表面S4”,则镀制导致形成在第四表面S4的下方的并且与第四表面S4直接接触的层52。在下文中,层52将被称为“第三涂覆层52”。
更详细地,第三涂覆层52可以例如由锡制成。进一步地,顶壁T和第一侧壁L1和第二侧壁L2也用第三涂覆层52来涂覆。第三涂覆层52在不与树脂区域36接触的情况下延伸。
上述的镀制可以以本身已知的方式执行,例如通过电镀执行。在这种情况下,将电势施加到接触区域8',由于剩余区域45的存在,接触区域8'形成单个电节点。
接下来,如在图7中所示,使用至少具有局部矩形横截面的第二刀片54进行第二局部切割。该第二切割从上面进行,从树脂区域36开始,基本上相对于凹槽R垂直地对准。在下文中,第二切割也特别 参考接触区域8'上产生的效果描述,除非另外指明。
更特别地,如在图8中更详细地示出的,第二切割导致完全地去除剩余区域45。更精确地,第二刀片54比第一刀片40更宽。因此,第二切割导致去除接触区域8'的包括剩余部分45的顶部。进一步地,第二刀片54穿透到接触区域8'内达到至少等于w-k+s的程度,其中s是第三涂覆层52的厚度。因此,第二切割还导致去除第三涂覆层52的在与顶壁T接触的情况下延伸的部分,并且因此导致在接触区域8'中形成具有纵向轴H的裂缝55。此外,在第二刀片54穿透到接触区域8'内达到大于w-k+s的程度的情况下,接触区域8'的布置在接触区域8'的上述的顶部部分下方并且与第一侧壁L1和第二侧壁L2相邻的部分也被去除。换句话说,接触区域8'的包围凹槽R的顶部部分的一部分被去除。
在下文中,裂缝55特别参考延伸穿过接触区域8'的部分描述,除非另外指明。
详细地,裂缝55穿过树脂区域36、第一涂覆层14的接触部分142、接触区域8'和第二涂覆层16的接触部分162。换句话说,如果通过“第五表面S5”指定第三涂覆层52的底表面,则裂缝55在第三表面S3和第五表面S5之间延伸。
裂缝55具有形成彼此连通并且彼此垂直对准的对应凹槽的顶部部分57和底部部分59。
顶部部分57在侧向上通过彼此平行并且与第一侧壁L1和第二侧壁L2平行的第三侧壁L3和第四侧壁L4界定。进一步地,顶部部分57具有大于凹槽R的宽度l的宽度u。更详细地,第三侧壁L3和第四侧壁L4中的每个侧壁部分地由树脂区域36、部分地由第一涂覆层14的接触部分142以及部分地由接触区域8'形成。
底部部分59具有j=l-2·s的宽度,因为第一侧壁L1和第二侧壁L2现在涂覆有第三涂覆层52的对应部分,第三涂覆层52的这些对应部分在下文中出于将在下文中阐明的理由将被称为“第一保护区域60和第二保护区域62”。第一保护区域60和第二保护区域62进一步也 在与第四表面S4接触的情况下延伸。
第三侧壁L3的底部部分由接触区域8'形成并且经由第一中壁I1连接到第一侧壁L1,该第一中壁I1也由接触区域8'形成并且基本上与第一侧壁L1和第三侧壁L3垂直。同样地,第四侧壁L4的底部部分由接触区域8'形成并且经由第一中壁I2连接到第二侧壁L2,该第二中壁I2也由接触区域8'形成并且基本上与第二侧壁L2和第四侧壁L4垂直。在实践中,第一中壁I1和第二中壁I2在第二切割之后已经暴露出并且分别从第三侧壁L3和第四侧壁L4向裂缝55的内部延伸直到它们分别与第一侧壁L1和第二侧壁L2连接。以这种方式,第一侧壁L1和第三侧壁L3与第一中壁I1一起形成第一肩部,第一肩部的底部部分由第一保护区域60涂覆,而第二侧壁L2和第四侧壁L4与第二中壁I2一起形成第二肩部,第二肩部的底部部分由第二保护区域62涂覆。在下文中,第一保护区域60和第二保护区域62与纵向轴H平行布置的表面,因此面对第一保护区域60和第二保护区域62的涂覆第一侧壁L1和第二侧壁L2的部分的裂缝55的表面,分别被称为“第一保护表面SW1和第二保护表面SW2”。
第二切割进一步导致组件3的切块,并且因此导致第一切块20和第二切块22的分离。例如,特别地参考第一裸片20,这形成如在图9中所示的对应的电子器件65。
在切块之后,树脂区域36的相对于第一裸片20固定的部分形成封装区域69(也被称为“盖”),而引线框架带2的相对于第一裸片20固定的部分形成电子器件65的引线框架。进一步地,接触区域8'的相对于第一裸片20固定的部分形成电子器件65的对应的端子70。尽管未示出,端子70属于对应的第一阵列的端子,第一阵列的端子例如彼此相同并且布置在电子器件65的第一侧上,该电子器件65又可以包括第二阵列的端子,第二阵列例如与第一阵列相同并且布置在电子器件65的与第一侧相对的第二侧上。进一步地,电子器件65可以是例如QFN类型的。
更详细地,封装区域69通过侧向表面Sl界定,表面S1在下文中 将被称为“封装的侧向表面Sl”。进一步地,封装区域69在底部通过表面Sbot界定,表面Sbot在下文中将被称为“封装底表面Sbot”。
端子70在底部通过第二表面S2的在下文中将被称为“端子底面Sinf”的部分界定。进一步地,端子70包括由封装区域69覆盖的内部部分以及相对于封装区域69向外凸出并且在侧向上通过第一侧壁L1的一部分界定的外部部分,第一侧壁L1的这一部分在下文中将被称为“第一端子侧向表面Sflank1”。进一步地,端子70的外部部分在顶部通过第一中壁I1界定。在实践中,在俯视平面图(未示出)中,端子70的外部部分凸出在由封装区域69的形状限定的边界之外。
端子70的内部部分又具有面对封装区域69并且在侧向上通过相应的侧向表面界定的顶部部分,该侧向表面在下文中将被称为“第二端子侧向表面Sflank2”;第二端子侧向表面Sflank2与封装侧向表面Sl共面。
如在图10中所示的,封装侧向表面Sl和封装底表面Sbot之间的交叉限定了边缘E。此外,端子70沿着边缘E延伸。
尽管如此,电子器件65可以通过在端子70和印刷电路板72之间形成临时固定区域74而被焊接到印刷电路板72。
通过本身已知的类型的焊膏形成临时固定区域74;例如,焊膏可以是基于锡的并且可以包含助焊剂。进一步地,临时固定区域74不仅在第五表面S5的下方延伸而且在与第一保护表面SW1接触的情况下延伸。
在焊接之后,并且因此在热工艺以及随后的第一保护区域60的融化之后,形成最终固定区域76(在图11中示出),固定区域76是锡的并且在端子70和印刷电路板72之间布置。特别地,最终固定区域76在不仅与端子底表面Sinf接触而且与第一端子侧向表面Sflank1接触的情况下延伸。实际上,由于第一保护区域60的存在,第一端子侧向表面Sflank1之前没有经受氧化,并且因此形成它的材料可以在焊接步骤期间被以液相存在的锡润湿。因此可以在端子70的材料和存在于焊膏中的金属材料之间形成金属间键合。
由于最终固定区域76不仅在端子底表面Sinf下方延伸而且在第一端子侧向表面Sflank1上延伸,因此可以轻松地检查最终固定区域76。
根据在图12中示出的制造方法的变形例,第二刀片(这里通过80指定)具有向下逐渐变窄的形状。特别地,第二刀片80的至少一部分具有底是等腰梯形的形状的棱柱形状,并且进行第二切割使得第三侧壁L3和第四侧壁L4被布置成横切但不垂直于裂缝55的纵向轴H。进一步地,第三侧壁L3和第四侧壁L4朝着裂缝55的底部部分59会聚。
如在图13中更详细地示出的,封装侧向表面Sl横切但不垂直于封装底面Sbot。进一步地,第二端子侧向表面Sflank2仍然与封装侧向表面Sl共面,封装侧向表面Sl以包括例如8°和12°之间的角度相对于第一端子侧向表面Sflank1倾斜。然而,第二端子的侧向表面Sflank2通过端子70的外部部分形成,因此侧向表面Sflank2在顶部通过第二端子侧向表面Sflank2本身并且通过相对于第二端子侧向表面Sflank2再次在侧向上错开的第一中壁I1界定。
以这种方式,进一步地改善了端子70和印刷电路板72之间存在的键合的可视性。进一步地,在任何情况下第一切割的宽度小于第二切割的最小宽度。
从已经描述的和之前图示的内容,本解决方案提供的优点清楚地显现。
特别地,本制造方法设想执行双重切割工艺,在两次切割工艺之间执行镀制(例如,通过电镀)工艺,以便保证电子器件的端子的外部侧向表面(也被称为“侧面(flanks)”)可以由用于将端子焊接到下方的板的焊膏润湿以有助于焊接点的检查。进一步地,本制造方法使得能够形成导电肩部,该导电肩部除了具有可润湿的侧向表面以外,还向上露出使得保证目检的特别宽的视角。
此外,本制造方法特别地廉价并且使得能够创建具有大的可焊区域的端子。
总之,清楚的是,可以对目前已经描述和图示的内容做出修改和 变化。而不因此脱离如在附加的权利要求中限定的本发明的范围。
例如,引线框架带可以不是预镀的类型的,或不管怎样仅仅是部分预镀的。例如,可以不存在第二涂覆层16。进一步地,第一涂覆层14和/或第二涂覆层16可以具有与已经描述的不同的延伸。例如,第一涂覆层14和/或第二涂覆层16可以仅仅涂覆引线框架带2的一部分。
如果不存在第二涂覆层16或不管怎样不在接触区域8'的下方延伸,则第一侧壁L1和第二侧壁L2完全由接触区域8'形成。进一步地,第一涂覆层14可能没有散发到裂缝55上,在这种情况下,所述层在形成第三侧壁L3和第四侧壁L4时并不同时发生。
至于第三涂覆层52,其可以是具有铅和锡的基材的合金的,而不是锡的。此外,它可以不涂覆顶壁T。
进一步地,第二端子侧向表面Sflank2可以不与封装侧向表面Sl共面。
至于切割操作,至少它们中的一些可以使用激光或水射流而不是使用刀片执行。
最后,电子器件可以包括多个裸片。
Claims (12)
1.一种表面贴装电子器件包括:
-半导体材料的本体(20);
-引线框架(4),形成多个接触端子(70);以及
-封装电介质区域(69),覆盖所述半导体材料的本体(20);
并且其中每个接触端子(70)包括由所述封装电介质区域(69)覆盖的内部部分和在侧向上凸出到所述封装电介质区域(69)之外并且通过第一侧向表面(Sflank1)界定的外部部分,对于每个接触端子(70),所述器件进一步包括:在对应的第一侧向表面(Sflank1)上延伸的抗氧化区域(60)。
2.根据权利要求1所述的电子器件,其中所述封装电介质区域(69)形成边缘(E),所述接触端子(70)的至少一部分沿着所述边缘(E)延伸。
3.根据权利要求1或权利要求2所述的电子器件,其中每个接触端子(70)通过设计成焊接到印刷电路板(72)上的底表面(Sinf)界定。
4.根据权利要求1或权利要求2所述的电子器件,所述电子器件是QFN类型的。
5.根据权利要求1或权利要求2所述的电子器件,其中所述内部部分形成第二侧向表面(Sflank2),并且其中所述外部部分在顶部处通过横向表面(I1)界定,所述横向表面(I1)连接到所述第一侧向表面(Sflank1)和所述第二侧向表面(Sflank2)并且横切所述第一侧向表面(Sflank1)和所述第二侧向表面(Sflank2)。
6.根据权利要求1或权利要求2所述的电子器件,其中所述外部部分在顶部处通过横向表面(I1)和通过第二侧向表面(Sflank2)界定,并且其中所述横向表面(I1)连接到所述第一侧向表面(Sflank1)和所述第二侧向表面(Sflank2)并且与所述第一侧向表面(Sflank1)基本上垂直,所述第二侧向表面(Sflank2)以包括8°和12°之间的角度相对于所述第一侧向表面(Sflank1)倾斜。
7.一种用于制造表面贴装电子器件的方法,包括步骤:
-执行组件(3)的第一切割,所述组件(3)至少包括一个第一裸片焊盘(6')和一个第二裸片焊盘(6")以及分别布置在所述第一裸片焊盘(6')和所述第二裸片焊盘(6")的顶上的至少一个第一半导体本体(20)和一个第二半导体本体(22),所述组件(3)进一步包括布置在第一裸片焊盘(6')和第二裸片焊盘(6")之间的多个端子区域(8)以及覆盖所述第一半导体本体(20)和所述第二半导体本体(22)和所述端子区域(8)的电介质区域(36),每个端子区域(8)通过彼此相对的第一区域表面(S1)和第二区域表面(S2)界定,所述第一区域表面(S1)面对所述电介质区域(36),从相应的第二区域表面(S2)开始进行所述第一切割使得去除所述端子区域(8')中的每个端子区域的一部分,使得所述端子区域(8')形成凹槽(R)的横向壁(T)和第一侧壁(L1)和第二侧壁(L2);
-利用抗氧化层(52)涂覆由每个端子区域(8')形成的所述第一侧壁(L1)和所述第二侧壁(L2);以及
-从所述电介质区域(36)开始执行所述组件(3)的第二切割以便针对每个端子区域(8')去除形成对应的横向壁(T)的相应顶部部分(45),并且将所述第一半导体本体(20)和第二半导体本体(22)分离;
并且其中所述第二切割具有大于所述第一切割的宽度的宽度。
8.根据权利要求7所述的方法,其中所述第一切割和所述第二切割以基本上对准的方式进行并且导致形成彼此连通的第一凹槽(57)和第二凹槽(59)。
9.根据权利要求7或权利要求8所述的方法,其中涂覆所述第一侧壁(L1)和所述第二侧壁(L2)的所述步骤通过电镀执行。
10.根据权利要求7或权利要求8所述的方法,其中执行涂覆所述第一侧壁(L1)和所述第二侧壁(L2)的所述步骤以便还利用所述抗氧化层(52)涂覆对应的所述横向壁(T)。
11.根据权利要求7或权利要求8所述的方法,其中所述第一切割和所述第二切割分别使用至少具有局部矩形横截面的第一刀片(40)和第二刀片(54)进行。
12.根据权利要求7或权利要求8所述的方法,其中使用具有锥形形状的第二刀片(80)进行所述第二切割用于针对每个端子区域(8')来暴露出所述端子区域(8')的相对于第一半导体本体(20)固定的并且通过对应的第一侧壁(L1)、中壁(I1)以及倾斜壁(Sflank2)界定的部分,所述中壁(I1)连接到所述第一侧壁(L1)并且连接到所述倾斜壁(Sflank2)并且与所述第一侧壁(L1)基本上垂直,所述倾斜壁(Sflank2)以包括8°和12°之间的角度相对于所述第一侧壁(L1)倾斜。
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TW418514B (en) * | 1998-06-30 | 2001-01-11 | Fujitsu Ltd | Semiconductor device and method of producing the same |
US6399415B1 (en) * | 2000-03-20 | 2002-06-04 | National Semiconductor Corporation | Electrical isolation in panels of leadless IC packages |
US20020084518A1 (en) * | 2000-12-28 | 2002-07-04 | Hajime Hasebe | Semiconductor device |
US20050116321A1 (en) * | 2002-12-10 | 2005-06-02 | National Semiconductor Corporation, A Delaware Corp. | Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) |
Also Published As
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US20160351477A1 (en) | 2016-12-01 |
US9640464B2 (en) | 2017-05-02 |
CN205194694U (zh) | 2016-04-27 |
US20160172275A1 (en) | 2016-06-16 |
CN105702657A (zh) | 2016-06-22 |
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