US20160172275A1 - Package for a surface-mount semiconductor device and manufacturing method thereof - Google Patents

Package for a surface-mount semiconductor device and manufacturing method thereof Download PDF

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Publication number
US20160172275A1
US20160172275A1 US14/840,663 US201514840663A US2016172275A1 US 20160172275 A1 US20160172275 A1 US 20160172275A1 US 201514840663 A US201514840663 A US 201514840663A US 2016172275 A1 US2016172275 A1 US 2016172275A1
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Prior art keywords
electronic device
mount electronic
lateral surface
package
region
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US14/840,663
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English (en)
Inventor
Fabio Marchisi
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STMicroelectronics SRL
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STMicroelectronics SRL
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Assigned to STMICROELECTRONICS S.R.L. reassignment STMICROELECTRONICS S.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MARCHISI, FABIO
Publication of US20160172275A1 publication Critical patent/US20160172275A1/en
Priority to US15/235,373 priority Critical patent/US9640464B2/en
Abandoned legal-status Critical Current

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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/171—Frame
    • H01L2924/176—Material
    • H01L2924/177—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/17738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/17747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to manufacturing of a surface-mount semiconductor device, and more particularly to methods for manufacturing a package for a surface-mount semiconductor device and a packaged surface-mount semiconductor device.
  • Semiconductor devices such as for example integrated circuits and micro-electro-mechanical systems (MEMS) devices, are packaged inside corresponding packages, which perform functions of protection and interfacing with the outside world.
  • packages are known that enable so-called “surface mounting” on a printed-circuit board.
  • surface-mount packages include, for example, packages of a “quad-flat no-leads” (QFN) type, also known as “micro lead frame” (MLF) packages or “small-outline no-leads” (SON) packages.
  • QFN quad-flat no-leads
  • MLF micro lead frame
  • SON small-outline no-leads
  • a QFN package includes a region of resin on a lead frame, which forms at least one array of terminals that are exposed by a bottom surface of the package.
  • the package is such that, when it is soldered on the printed-circuit board, corresponding soldering joints are present between the terminals of the package and the pads of the printed-circuit board.
  • the soldering joints may be noted and inspected visually in a relatively easy way.
  • the angle under which each soldering joint is visible is not particularly wide, nor is the weldable area of each terminal.
  • the present disclosure provides a package for a semiconductor device that solves, at least in part, the drawbacks of the known art.
  • a surface-mount electronic device includes a body of semiconductor material, and a lead frame that forms a plurality of contact terminals.
  • a package dielectric region overlies the body of semiconductor material, and each contact terminal includes an inner portion that is overlaid by the package dielectric region and an outer portion that projects laterally beyond the package dielectric region and is delimited by a first lateral surface.
  • an anti-oxidation layer is disposed on the first lateral surface.
  • the inner portion forms a second lateral surface, and a transverse surface of the outer portion is connected to the first and second lateral surfaces.
  • a method for manufacturing a surface-mount electronic device includes applying a semiconductor material to a first and a second die pad to form a first and second semiconductor die.
  • the first and second semiconductor dies are electrically connected to a terminal region that is disposed between the first and second semiconductor dies.
  • a molding compound is applied to the first semiconductor die, the top side of the terminal region, and the second semiconductor die.
  • a first partial cut is made through a bottom side of the terminal region where the bottom side is disposed opposite the top side of the terminal region.
  • the first partial cut forms a first recess that is defined by a pair of sidewalls and a transverse wall.
  • a distance between the sidewalls defines a first recess width.
  • the pair of sidewalls is coated with an anti-oxidation layer.
  • a second partial cut is made through the molding compound and the top side of the terminal region. A depth of the second partial cut extends into the first recess to sever the terminal region.
  • the width of the second partial cut is greater than the first rece
  • FIG. 1A is a schematic top plan view of a lead-frame strip
  • FIG. 1B shows an enlarged view of a portion of the lead-frame strip shown in FIG. 1A ;
  • FIGS. 2-5, 7, 9, and 11 are schematic cross-sectional views that show successive steps of a packaging method according to one embodiment of the present semiconductor device
  • FIG. 6 is an enlarged schematic view of a portion shown in FIG. 5 ;
  • FIG. 8 is an enlarged schematic view of a portion shown in FIG. 7 ;
  • FIG. 10 is a schematic side view of an electronic device.
  • FIGS. 12 and 13 are schematic cross-sectional views that show successive steps of a variant of the present packaging method.
  • FIG. 1A shows, by way of example, a lead-frame strip 2 , which is of a known type and is formed of conductive material (for example, copper).
  • the lead-frame strip 2 includes a plurality of device areas 4 , each of which in turn includes a respective die pad 6 , shown in greater detail in FIG. 1B .
  • the lead-frame strip 2 includes a plurality of contact regions 8 .
  • FIG. 2 shows an assembly 3 , which, by way of example, includes the lead-frame strip 2 , and in particular includes a first device area 4 ′ and a second device area 4 ′′.
  • the first device area 4 ′ includes a first die pad 6 ′ and the second device area 4 ′′ includes a second die pad 6 ′′.
  • the assembly 3 includes a contact region 8 ′, which extends between the first and second die pads 6 ′, 6 ′′, at a distance therefrom.
  • the top surfaces of the contact region 8 ′ and of the first and second die pads 6 ′, 6 ′′ define a first surface S 1
  • the bottom surfaces of the contact region 8 ′ and of the first and second die pads 6 ′, 6 ′′ define a second surface S 2 .
  • the lead-frame strip 2 is of the pre-plated type, and consequently includes a first coating layer 14 and a second coating layer 16 , which are made, for example, of tin.
  • the first coating layer 14 extends over the first surface S 1 , and thus over the contact region 8 ′ and the first and second die pads 6 ′, 6 ′′, with which it is in direct contact.
  • the second coating layer 16 extends underneath the second surface S 2 , and thus underneath the contact region 8 ′ and the first and second die pads 6 ′, 6 ′′, with which it is in direct contact.
  • the first coating layer 14 includes a first pad portion 140 , a second pad portion 144 , and a contact portion 142 .
  • the first pad portion 140 , the second pad portion 144 , and the contact portion 142 of the first coating layer 14 extend, respectively, on the first die pad 6 ′, the second die pad 6 ′′, and the contact region 8 ′.
  • the second coating layer 16 includes a first pad portion 160 , a second pad portion 164 , and a contact portion 162 .
  • the first pad portion 160 , second pad portion 164 , and contact portion 162 of the second coating layer 16 extend, respectively, underneath the first die pad 6 ′, the second die pad 6 ′′, and the contact region 8 ′.
  • the assembly 3 further includes a first die 20 and a second die 22 , which are fixed, respectively, to the first pad portion 140 and to the second pad portion 144 of the first coating layer 14 , by interposition, respectively, of a first bonding layer 24 and a second bonding layer 26 .
  • the assembly 3 includes a first conductive wire 30 and a second conductive wire 32 .
  • the first conductive wire 30 electrically connects the first die 20 to the contact portion 142 of the first coating layer 14 , with which it forms a first wire bonding.
  • the second conductive wire 32 electrically connects the second die 22 to the contact portion 142 of the first coating layer 14 , with which it forms a second wire bonding.
  • the assembly 3 may be previously formed as is known in the art and further includes a molding compound 36 , which is made, for example, of a thermosetting epoxy resin and overlies, as is known in the art, the first die 20 and the second die 22 , as well as the lead-frame strip 2 .
  • the molding compound 36 also extends at least in partially in the gaps between the first and second die pads 6 ′, 6 ′′ and the contact region 8 ′.
  • the molding compound 36 will be referred to as resin region 36 .
  • the resin region 36 is delimited at the top by a respective surface S 3 , which will be referred to hereinafter as third surface S 3 .
  • a selective removal of a portion of lead-frame strip 2 is carried out, as shown in FIG. 3 .
  • This removal and the subsequent steps are described in what follows, with particular reference to the effects produced in the contact region 8 ′, except where otherwise specified.
  • a first partial cut is made using a first blade 40 having at least locally a rectangular cross-section. This first cut is made from beneath, starting from the contact portion 162 of the second coating layer 16 for removing a part of this contact portion 162 , as well as an overlying portion of the contact region 8 ′.
  • the first cut is such that a recess R is formed within the contact region 8 ′.
  • a recess R Extending on top of the recess R is a non-removed portion of the contact region 8 ′, which will be referred to hereinafter as “residual region 45 ”.
  • the residual region 45 has a thickness equal to w ⁇ k.
  • the recess R is a recess that extends also through the other contact regions 8 that form the array to which the contact region 8 ′ belongs, as well as between the portions of resin region 36 arranged in between. However, for simplicity of description, the recess R is described with particular reference to the portion formed by the contact region 8 ′.
  • the recess R is delimited laterally by a first sidewall L 1 and a second sidewall L 2 , which are formed by the contact region 8 ′ and, to a lesser extent, by the contact portion 162 of the second coating layer 16 .
  • the recess R is delimited at the top by a top wall T, which is formed by the residual region 45 .
  • the first and second sidewalls L 1 , L 2 are parallel to one another. Further, the recess R has a width l, measured in a direction perpendicular to the direction of the first cut. In practice, the first and second sidewalls L 1 , L 2 are at a distance from one another equal to the width l.
  • the bottom surface of the second coating layer 16 is designated as “fourth surface S 4 ” .
  • the plating forms a layer 52 underneath and in direct contact with the fourth surface S 4 .
  • the layer 52 will be referred to as “third coating layer 52 ”.
  • the third coating layer 52 may be made, for example, of tin. Further, the top wall T and the first and second sidewalls L 1 , L 2 are also coated with the third coating layer 52 . The third coating layer 52 does not extend in contact with the resin region 36 .
  • the aforementioned plating may be carried out, for example, by electroplating, in a known manner.
  • a potential is applied to the contact region 8 ′, which, due to the presence of the residual region 45 , forms a single electrical node.
  • a second partial cut is made using a second blade 54 having at least locally a rectangular cross-section.
  • This second cut is made from above, starting from the resin region 36 , to be substantially vertically aligned with respect to the recess R.
  • the second cut is described with particular reference to the effects produced in the contact region 8 ′, except where otherwise specified.
  • the second cut leads to complete removal of the residual region 45 . More precisely, the second blade 54 is wider than the first blade 40 . Thus, the second cut leads to removal of a top portion of the contact region 8 ′, which includes the residual portion 45 . Further, the second blade 54 penetrates within the contact region 8 ′ for an extent at least equal to w ⁇ k+s, where s is the thickness of the third coating layer 52 . Consequently, the second cut also leads to removal of the portion of third coating layer 52 that extends in contact with the top wall T, and thus leads to formation of a split 55 in the contact region 8 ′, which has a longitudinal axis H.
  • portions of the contact region 8 ′ arranged underneath the aforementioned top portion of the contact region 8 ′ and adjacent to the first and second sidewalls L 1 , L 2 are also removed. In other words, a part of the contact region 8 ′ that surrounds a top portion of the recess R is removed.
  • the split 55 traverses the resin region 36 , the contact portion 142 of the first coating layer 14 , the contact region 8 ′ and the contact portion 162 of the second coating layer 16 .
  • the split 55 extends between the third surface S 3 and the fifth surface S 5 .
  • the split 55 has a top portion 57 and a bottom portion 59 , which form corresponding recesses that communicate and are vertically aligned with one another.
  • the top portion 57 is delimited laterally by a third sidewall L 3 and a fourth sidewall L 4 , which are parallel to one another and to the first and second sidewalls L 1 , L 2 . Further, the top portion 57 has a width u, greater than the width l of the recess R.
  • each of the third sidewall L 3 and the fourth sidewall L 4 is formed in part by the resin region 36 , in part by the contact portion 142 of the first coating layer 14 , and in part by the contact region 8 ′.
  • the first and second protective regions 60 , 62 further extend also in contact with the fourth surface S 4 .
  • a bottom portion of the third sidewall L 3 is formed by the contact region 8 ′ and is connected to the first sidewall L 1 via a first intermediate wall I 1 , which is also formed by the contact region 8 ′ and is substantially perpendicular to the first and third sidewalls L 1 , L 3 .
  • a bottom portion of the fourth sidewall L 4 is formed by the contact region 8 ′ and is connected to the second sidewall L 2 via a second intermediate wall I 2 , which is also formed by the contact region 8 ′ and is substantially perpendicular to the second and fourth sidewalls L 2 , L 4 .
  • the first and second intermediate walls I 1 , I 2 have been exposed following the second cut and extend from the third and fourth sidewalls L 3 , L 4 , respectively, towards the inside of the split 55 , until they connect, respectively, with the first and second sidewalls L 1 , L 2 .
  • first and third sidewalls L 1 , L 3 form, together with the first intermediate wall I 1 , a first shoulder, a bottom portion of which is coated by the first protective region 60
  • second and fourth sidewalls L 2 , L 4 form, together with the second intermediate wall I 2 , a second shoulder.
  • the second protective region 62 coats a bottom portion of the second shoulder.
  • the first and second protective surfaces SW 1 , SW 2 are, respectively, the surfaces of the first and second protective regions 60 , 62 that are arranged parallel to the longitudinal axis H, and thus are the surfaces facing the split 55 of the portions of the first and second protective regions 60 , 62 that coat the first and second sidewalls L 1 , L 2 .
  • the second cut further leads to dicing of the assembly 3 , and thus separation of the first and second dies 20 , 22 .
  • this forms a corresponding electronic device 65 as shown in FIG. 9 .
  • the portion of resin region 36 fixed with respect to the first die 20 forms a package dielectric region 69 (also known as “cap”), whereas the portion of the lead-frame strip 2 fixed with respect to the first die 20 forms the lead frame of the electronic device 65 .
  • the portion of the contact region 8 ′ fixed with respect to the first die 20 forms a corresponding terminal 70 of the electronic device 65 .
  • the terminal 70 belongs to a corresponding first array of terminals that are for example the same as one another and arranged on a first side of the electronic device 65 , which in turn may include a second array of terminals, which is, for example, identical to the first array and is arranged on a second side of the electronic device 65 , opposite to the first side.
  • the electronic device 65 it is possible for the electronic device 65 to be, for example, of a quad-flat no-leads (QFN) type.
  • QFN quad-flat no-leads
  • the package dielectric region 69 is delimited by a lateral surface S l , which will be referred to hereinafter as “lateral surface of the package S l ”. Further, the package dielectric region 69 is delimited at the bottom by a surface S bot , which will be referred to hereinafter as “package bottom surface S bot ”.
  • the terminal 70 is delimited at the bottom by a portion of the second surface S 2 , which will be referred to hereinafter as “terminal bottom surface S inf ”. Further, the terminal 70 includes an inner portion, which is overlaid by the package dielectric region 69 , and an outer portion, which projects outwards with respect to the package dielectric region 69 and is delimited laterally by a portion of the first sidewall L 1 , which will be referred to hereinafter as “first terminal lateral surface S flank1 ”. Further, the outer portion of the terminal 70 is delimited at the top by the first intermediate wall I 1 . In a top plan view (not shown), the outer portion of the terminal 70 projects beyond the perimeter that is defined by the shape of the package dielectric region 69 .
  • the inner portion of the terminal 70 has, in turn, a top portion, which faces the package dielectric region 69 and is delimited laterally by a respective lateral surface, which will be referred to hereinafter as “second terminal lateral surface S flank2 ”; the second terminal lateral surface S flank2 is coplanar with the package lateral surface S l .
  • the intersection between the package lateral surface S l and the package bottom surface S bot defines an edge E.
  • the terminal 70 extends along the edge E.
  • the electronic device 65 may be soldered to a printed-circuit board 72 by forming a temporary fixing region 74 between the terminal 70 and the printed-circuit board 72 .
  • a solder paste of a known type forms the temporary fixing region 74 ; for example, the solder paste may be tin-based and may contain a flux. Further, the temporary fixing region 74 extends, not only underneath the fifth surface S 5 , but also in contact with the first protective surface SW 1 .
  • a final fixing region 76 (shown in FIG. 11 ) is formed, which is formed of tin and is arranged between the terminal 70 and the printed-circuit board 72 .
  • the final fixing region 76 extends, not only in contact with the terminal bottom surface S inf , but also in contact with the first terminal lateral surface S flank1 .
  • the first protective region 60 may be referred to as an anti-oxidation layer or an anti-oxidizing region. Intermetallic bonds may thus form between the material of the terminal 70 and the metal material present in the solder paste.
  • the final fixing region 76 may be easily inspected, due at least in part to the fact that it extends, not only underneath the terminal bottom surface S inf , but also on the first terminal lateral surface S flank1 .
  • the second blade (here designated by 80 ) has a shape tapered downwards.
  • at least one portion of the second blade 80 has the shape of a prism, the base of which has the shape of an isosceles trapezium, and the second cut is made in such a way that the third and fourth sidewalls L 3 , L 4 are arranged transverse, but not perpendicular, to the longitudinal axis H of the split 55 . Further, the third and fourth sidewalls L 3 , L 4 converge towards the bottom portion 59 of the split 55 . As shown in greater detail in FIG.
  • the package lateral surface S l is transverse, but not perpendicular, to the package bottom surface S bot .
  • the second terminal lateral surface S flank2 is still coplanar with the package lateral surface S l , which is inclined with respect to the first terminal lateral surface S flank1 by an angle, for example, between 8° and 12°.
  • the second terminal lateral surface S flank2 is, however, formed by the outer portion of the terminal 70 , which is thus delimited at the top by the second terminal lateral surface S flank2 itself, as well as by the first intermediate wall I 1 , which is once again laterally staggered with respect to the second terminal lateral surface S flank2 .
  • the width of the first cut is in any case less than the minimum width of the second cut.
  • the manufacturing methods of the present disclosure provide certain advantages.
  • the manufacturing methods of the present disclosure include carrying out a dual cutting process, between which a plating process is carried out (for example, by electroplating), such that the external lateral surfaces (also known as “flanks”) of the terminals of the electronic device may be wetted by the solder paste used for soldering the terminals to the underlying board for facilitating inspection of the welds.
  • the present manufacturing method enables formation of conductive shoulders, which, in addition to having wettable lateral surfaces, are exposed upwards, such that a particularly wide angle of visual inspection is provided.
  • the present manufacturing method is particularly inexpensive and enables creation of terminals having a large weldable area.
  • the lead-frame strip may not to be of the pre-plated type, or in any case to be only partially pre-plated.
  • the second coating layer 16 may be absent.
  • the first coating layer 14 and/or the second coating layer 16 may have extensions different from what has been described.
  • the first coating layer 14 and/or the second coating layer 16 may coat only portions of the lead-frame strip 2 .
  • the first and second sidewalls L 1 , L 2 are entirely formed by the contact region 8 ′. It is further possible for the first coating layer 14 not to extend to the split 55 , in which case said layer does not form the third and fourth sidewalls L 3 , L 4 .
  • the third coating layer 52 instead of being of tin, this may be of an alloy with a base of lead and tin. In addition, it may not coat the top wall T.
  • the second terminal lateral surface S flank2 not to be coplanar with the package lateral surface S l .
  • the electronic device may include more than one die.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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US9184121B2 (en) 2014-02-05 2015-11-10 Texas Instruments Incorporated Stacked synchronous buck converter having chip embedded in outside recess of leadframe
KR102178587B1 (ko) * 2014-03-27 2020-11-13 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치의 제조 방법 및 반도체 장치

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JP2020524410A (ja) * 2017-06-19 2020-08-13 日本テキサス・インスツルメンツ合同会社 事前に濡れさせたコンタクト側壁表面を備える集積回路パッケージ
JP7505145B2 (ja) 2017-06-19 2024-06-25 テキサス インスツルメンツ インコーポレイテッド 事前に濡れさせたコンタクト側壁表面を備える集積回路パッケージ
US11581247B2 (en) * 2020-10-08 2023-02-14 Mitsubishi Electric Corporation Semiconductor device resistant to thermal cracking and manufacturing method thereof

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US9640464B2 (en) 2017-05-02
CN105702657B (zh) 2019-01-11
CN205194694U (zh) 2016-04-27

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