CN105529257A - 一种优化堆叠栅介质与锗界面的方法 - Google Patents
一种优化堆叠栅介质与锗界面的方法 Download PDFInfo
- Publication number
- CN105529257A CN105529257A CN201610053917.7A CN201610053917A CN105529257A CN 105529257 A CN105529257 A CN 105529257A CN 201610053917 A CN201610053917 A CN 201610053917A CN 105529257 A CN105529257 A CN 105529257A
- Authority
- CN
- China
- Prior art keywords
- substrate
- sample
- gate medium
- interface
- germanium interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 229910052732 germanium Inorganic materials 0.000 title claims abstract description 17
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 title claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 14
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000005457 optimization Methods 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 7
- 230000008021 deposition Effects 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims abstract description 3
- 238000000231 atomic layer deposition Methods 0.000 claims description 19
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 13
- 239000008367 deionised water Substances 0.000 claims description 12
- 229910021641 deionized water Inorganic materials 0.000 claims description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 10
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005406 washing Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 4
- 229910052593 corundum Inorganic materials 0.000 abstract 4
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 4
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 abstract 1
- 238000001755 magnetron sputter deposition Methods 0.000 abstract 1
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 239000002957 persistent organic pollutant Substances 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 3
- 229910005793 GeO 2 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
一种优化堆叠栅介质与锗界面的方法,涉及堆叠栅介质。对Ge衬底进行清洗,去除有机污染物、氧化物和金属杂质等物质;将清洗后的Ge衬底放入原子层沉积系统中,沉积一层Al2O3薄膜,实现对Ge衬底的表面钝化,获得Al2O3/Ge结构;将Al2O3/Ge结构样品进行湿法退火处理,实现Al2O3/Ge界面态的优化;在处理后的样品上生长HfO2高K介质;将获得的样品正面固定在掩膜板上,放入磁控溅射机中沉积金属层作为上电极,在样品Ge衬底的背面溅射金属层作为背电极,即得MOS结构器件,实现优化堆叠栅介质与锗界面。可优化高K介质/Ge界面态,并能维持钝化层的热稳定性,可减小工艺流程和时间成本。
Description
技术领域
本发明涉及堆叠栅介质,尤其是涉及一种优化堆叠栅(HfO2/Al2O3)介质与锗界面的方法。
背景技术
随着半导体技术的发展,晶体管的特征尺寸不断等比例缩小[1],栅极介质材料SiO2的厚度越来越接近其极限物理厚度,采用HfO2等高K介质代替传统的SiO2栅介质已成为发展的必然。此外,锗衬底由于具有较大的空穴迁移率(Si的四倍),基于这些优点,锗衬底高K介质栅MOSFET器件已成为业内人士的研究热点[2-3]。但HfO2/Ge界面态密度过大已成为锗衬底MOSFET器件进一步发展的一个重要问题[4-5]。研究人员已多方面尝试采用湿法退火[6-7]、GeO2钝化、GeOxNy钝化及Si表面钝化等手段实现HfO2/Ge界面性能的优化。
此外,Al2O3因为具有较高的介电常数9和较好的阻隔效果而被广泛应用于Ge表面钝化领域。目前为止,HfO2/Al2O3/Ge结构堆叠栅的研究已经取得了一定的进展[8-9],但Al2O3/Ge的界面态仍有进一步优化的空间。
参考文献:
[1]奥地利,艾罗拉,张兴.用于VLSI模拟的小尺寸MOS器件模型:理论与实践[J].1999。
[2]RaviPillarisetty,Academicandindustryresearchprogressingermaniumnanodevices[J],NATURE,2011,479:324-328。
[3]INTERNATIONALTECHNOLOGYROADMAPFORSEMICONDUCTORS[J],2011EDITIO。
[4]M.Houssa,G.Pourtois,M.Caymax,etal.First-principlesstudyofthestructuralandelectronicpropertiesof(100)Ge/Ge(M)O[sub2]interfaces(M=Al,La,orHf)[J],Appl.Phys.Lett.2008,92,242101。
[5]KojiKita,ShoSuzuki,HideyukiNomura,etal.DirectEvidenceofGeOVolatilizationfromGeO2/GeandImpactofItsSuppressiononGeO2/GeMetal–Insulator–SemiconductorCharacteristics[J].Jpn.J.Appl.Phys.200847:2349。
[6]GuanzhouLiu,ChengLi,HongkaiLai,etal.GeIncorporationinHfO2DielectricDepositedonGeSubstrateduringDry/WetThermalAnnealing[J],J.Electrochem.Soc.,2010,157:6H603-H606。
[7]Xu,J.P,Lai,P.T,Li,C.X,etal.ImprovedelectricalpropertiesofGermaniumMOScapacitorswithgatedielectricgrowninwet-NOambient[J],ElectronDeviceLetters,IEEE,2006,27:439-441。
[8]ShankarSwaminathan,MichaelShandalov,YasuhiroOshima,etal.BilayermetaloxidegateinsulatorsforscaledGe-channelmetal-oxide-semiconductordevices[J],Appl.Phys.Lett.2010,96:082904。
[9]S.Mather,N.Sedghi,M.Althobaiti,etal.LowEOTGeO2/Al2O3/HfO2onGesubstrateusingultrathinAldeposition[J],MicroelectronicEngineering2013,109:126–128。
发明内容
本发明的目的在于针对目前锗MOS器件中高K介质HfO2/Ge界面态密度过大,造成沟道迁移率下降、栅极漏电流变大等问题,提供既能优化界面又可以有效阻隔界面互扩散,可获得较小界面态密度(Dit)和较小等效氧化层厚度(EOT<1nm)的锗沟道MOS堆叠栅结构的一种优化堆叠栅介质与锗界面的方法。
本发明包括以下步骤:
1)对Ge衬底进行清洗,去除有机污染物、氧化物和金属杂质等物质;
2)将清洗后的Ge衬底放入原子层沉积系统(ALD)中,沉积一层Al2O3薄膜,实现对Ge衬底的表面钝化,获得Al2O3/Ge结构;
3)将步骤2)得到的Al2O3/Ge结构样品进行湿法退火处理,实现Al2O3/Ge界面态的优化;
4)在步骤3)处理后的样品上生长HfO2高K介质;
5)将步骤4)中获得的样品正面固定在掩膜板上,放入磁控溅射机中沉积金属层作为上电极,在样品Ge衬底的背面溅射金属层作为背电极,即得到MOS结构器件,实现优化堆叠栅介质与锗界面。
在步骤1)中,所述清洗可采用如下方法:先对Ge片进行有机清洗,依次在丙酮、乙醇、去离子水中各超声清洗10min,去除有机污染物;再用去离子水冲洗后放入盐酸溶液中漂洗4min,去除表面氧化物层;然后用去离子水冲洗后放入氢氟酸溶液中漂洗30s;经过去离子水冲洗,最后用N2吹干;所述盐酸溶液中按体积比HCl∶H2O=1∶4;所述氢氟酸溶液中按体积比HF∶H2O=1∶50。
在步骤4)中,所述生长HfO2高K介质可采用原子层沉积法。
在步骤5)中,所述作为上电极的金属层的厚度可为300nm。
本发明的技术方案是首先在清洗后的Ge衬底上采用原子层沉积系统(ALD)沉积一层超薄的Al2O3钝化层,接着对Al2O3表面钝化后的Ge衬底进行湿法退火。退火完成后在ALD系统中进行HfO2介质的沉积,获得界面较好的HfO2/Al2O3/Ge堆叠栅结构。
本发明是采用原子层沉积系统获得HfO2/Al2O3/Ge结构的堆叠栅,并采用湿法退火的方式实现Al2O3/Ge界面态的性能优化。这种方法可以优化高K介质/Ge界面态,并能维持钝化层的热稳定性,是一种具有广阔应用空间的新方法。尤其是原子层沉积系统(ALD)原位湿法退火法,该方法可以大大减小工艺的流程和时间成本。这一方法可实现锗MOSFET器件的产业化应用。
附图说明
图1为本发明脉冲湿法退火优化界面态并制备HfO2/Al2O3/Ge结构堆叠栅MOS器件的流程示意图。
具体实施方式
以下实施例将结合附图对本发明作进一步的说明。
实施例1:图1给出本发明脉冲湿法退火优化界面态并制备HfO2/Al2O3/Ge结构堆叠栅MOS器件的流程示意图。其中,1为Ge衬底,2为原子层沉积法制备的Al2O3超薄钝化层,3为经过脉冲湿法退火处理的Al2O3超薄钝化层,4为原子层沉积法制备的HfO2栅介质层,5为金属电极层。首先对Ge衬底进行清洗:先对Ge片进行有机清洗,溶液(先丙酮,后乙醇,最后去离子水)中各超声10min,去除有机污染物;用去离子水冲洗后放入盐酸溶液中(HCl∶H2O=1∶4)漂洗4min,去除表面氧化物层;用去离子水冲洗后放入氢氟酸溶液中(HF∶H2O=1∶50)漂洗30s;经过去离子水冲洗,最后用N2吹干(见图1(a))。
将清洗后的Ge片迅速放入原子层沉积系统(ALD)中,用ALD沉积一层超薄的Al2O3薄膜(见图1(b));接着,对Al2O3钝化后的样品进行湿法退火处理(见图1(c));然后,使用ALD在样品表面沉积一定厚度的HfO2薄膜(见图1(d))。
最后,将处理过的样品固定在掩膜板上,用磁控溅射机沉积一层300nm左右的金属电极作为上电极,在Si衬底背面溅射金属作为背电极,得到MOS器件结构(见图1(e))。
本发明首先使用原子层沉积法在锗衬底表面沉积薄层Al2O3钝化层,并采用湿法退火的方式对Al2O3/Ge进行界面优化,最后沉积HfO2介质层获得堆叠栅结构。本发明是一种与硅标准工艺相兼容的工艺方法。
Claims (5)
1.一种优化堆叠栅介质与锗界面的方法,其特征在于包括以下步骤:
1)对Ge衬底进行清洗,去除有机污染物、氧化物和金属杂质等物质;
2)将清洗后的Ge衬底放入原子层沉积系统(ALD)中,沉积一层Al2O3薄膜,实现对Ge衬底的表面钝化,获得Al2O3/Ge结构;
3)将步骤2)得到的Al2O3/Ge结构样品进行湿法退火处理,实现Al2O3/Ge界面态的优化;
4)在步骤3)处理后的样品上生长HfO2高K介质;
5)将步骤4)中获得的样品正面固定在掩膜板上,放入磁控溅射机中沉积金属层作为上电极,在样品Ge衬底的背面溅射金属层作为背电极,即得到MOS结构器件,实现优化堆叠栅介质与锗界面。
2.如权利要求1所述一种优化堆叠栅介质与锗界面的方法,其特征在于在步骤1)中,所述清洗采用如下方法:先对Ge片进行有机清洗,依次在丙酮、乙醇、去离子水中各超声清洗10min,去除有机污染物;再用去离子水冲洗后放入盐酸溶液中漂洗4min,去除表面氧化物层;然后用去离子水冲洗后放入氢氟酸溶液中漂洗30s;经过去离子水冲洗,最后用N2吹干。
3.如权利要求2所述一种优化堆叠栅介质与锗界面的方法,其特征在于所述盐酸溶液中按体积比HCl∶H2O=1∶4;所述氢氟酸溶液中按体积比HF∶H2O=1∶50。
4.如权利要求1所述一种优化堆叠栅介质与锗界面的方法,其特征在于在步骤4)中,所述生长HfO2高K介质采用原子层沉积法。
5.如权利要求1所述一种优化堆叠栅介质与锗界面的方法,其特征在于在步骤5)中,所述作为上电极的金属层的厚度为300nm。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610053917.7A CN105529257A (zh) | 2016-01-27 | 2016-01-27 | 一种优化堆叠栅介质与锗界面的方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610053917.7A CN105529257A (zh) | 2016-01-27 | 2016-01-27 | 一种优化堆叠栅介质与锗界面的方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105529257A true CN105529257A (zh) | 2016-04-27 |
Family
ID=55771404
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610053917.7A Pending CN105529257A (zh) | 2016-01-27 | 2016-01-27 | 一种优化堆叠栅介质与锗界面的方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105529257A (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106711021A (zh) * | 2016-11-29 | 2017-05-24 | 东莞市广信知识产权服务有限公司 | 一种硅锗基mos表面处理与介质生长方法 |
CN111628000A (zh) * | 2020-05-06 | 2020-09-04 | 武汉大学 | 激光冲击制备亚纳米级沟道背电极场效应晶体管的方法 |
CN112259613A (zh) * | 2020-10-26 | 2021-01-22 | 上海交通大学 | 提高锗Ge MOS电容器件性能的方法、系统及设备 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101916719A (zh) * | 2010-07-17 | 2010-12-15 | 厦门大学 | 一种调节金属与n型锗肖特基接触势垒高度的方法 |
US20150093889A1 (en) * | 2013-10-02 | 2015-04-02 | Intermolecular | Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuits |
-
2016
- 2016-01-27 CN CN201610053917.7A patent/CN105529257A/zh active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101916719A (zh) * | 2010-07-17 | 2010-12-15 | 厦门大学 | 一种调节金属与n型锗肖特基接触势垒高度的方法 |
US20150093889A1 (en) * | 2013-10-02 | 2015-04-02 | Intermolecular | Methods for removing a native oxide layer from germanium susbtrates in the fabrication of integrated circuits |
Non-Patent Citations (2)
Title |
---|
J.P. XU ET AL: "Use of water vapor for suppressing the growth of unstable low-κ interlayer in HfTiO gate-dielectric Ge metal-oxide-semiconductor capacitors with sub-nanometer capacitance equivalent thickness", 《THIN SOLID FILMS》 * |
R. ZHANG ET AL: "High Mobility Ge pMOSFETs with 0.7 nm Ultrathin EOT using HfO2/Al2O3/GeOx/Ge Gate Stacks Fabricated by Plasma Post Oxidation", 《SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS》 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106711021A (zh) * | 2016-11-29 | 2017-05-24 | 东莞市广信知识产权服务有限公司 | 一种硅锗基mos表面处理与介质生长方法 |
CN111628000A (zh) * | 2020-05-06 | 2020-09-04 | 武汉大学 | 激光冲击制备亚纳米级沟道背电极场效应晶体管的方法 |
CN112259613A (zh) * | 2020-10-26 | 2021-01-22 | 上海交通大学 | 提高锗Ge MOS电容器件性能的方法、系统及设备 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102332395B (zh) | 一种选择性淀积栅氧和栅电极的方法 | |
US20140264281A1 (en) | Channel-Last Methods for Making FETS | |
CN101752236B (zh) | 一种调控GaAs半导体与栅介质间能带补偿的原子层沉积Al2O3/HfO2方法 | |
CN102629559B (zh) | 叠栅SiC-MIS电容的制作方法 | |
CN105529257A (zh) | 一种优化堆叠栅介质与锗界面的方法 | |
CN101838812B (zh) | 一种清洗钝化Ge衬底表面的方法 | |
CN103295890B (zh) | 淀积在锗基或三五族化合物基衬底上的栅介质的处理方法 | |
CN104966665A (zh) | 一种改善SiC与SiO2界面态密度的方法 | |
CN103531538A (zh) | 互补型金属氧化物半导体管的形成方法 | |
CN101728257B (zh) | 一种栅介质/金属栅集成结构的制备方法 | |
CN103137691A (zh) | 场效应晶体管及其制作方法 | |
CN102543751A (zh) | 等效氧化物厚度为亚纳米的Ge基MOS器件的制备方法 | |
WO2012145952A1 (zh) | 沉积栅介质的方法、制备mis电容的方法及mis电容 | |
CN102024707B (zh) | 一种GaAs基MOS器件的制备方法 | |
CN103956325B (zh) | 一种多层复合氧化物高k介质薄膜晶体管的制备方法 | |
CN104716191B (zh) | 双栅双极石墨烯场效应晶体管及其制作方法 | |
CN103646865A (zh) | 在Ge衬底制备超薄氧化锗界面修复层的方法 | |
CN102064111A (zh) | 一种利用等离子体释放费米能级钉扎的方法 | |
Schilirò et al. | Plasma enhanced atomic layer deposition of Al2O3 gate dielectric thin films on AlGaN/GaN substrates: The role of surface predeposition treatments | |
CN115621128A (zh) | 高热导率二维半导体场效应晶体管的制作方法及晶体管 | |
CN104733285A (zh) | 在半导体衬底表面制备锌掺杂超浅结的方法 | |
KR102488508B1 (ko) | 실리콘-함유 층들을 형성하는 방법들 | |
CN108172613A (zh) | 一种具有高介电常数结晶相的锆基栅介质材料以及其制备方法 | |
CN102176414A (zh) | 金属硅化物的制备方法 | |
CN101404252A (zh) | 全硅化物金属栅电极制造工艺 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160427 |
|
RJ01 | Rejection of invention patent application after publication |