CN105283943B - 贴合晶圆的制造方法 - Google Patents

贴合晶圆的制造方法 Download PDF

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Publication number
CN105283943B
CN105283943B CN201480032979.9A CN201480032979A CN105283943B CN 105283943 B CN105283943 B CN 105283943B CN 201480032979 A CN201480032979 A CN 201480032979A CN 105283943 B CN105283943 B CN 105283943B
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CN
China
Prior art keywords
wafer
bonded
wafers
thickness
ion
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Active
Application number
CN201480032979.9A
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English (en)
Chinese (zh)
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CN105283943A (zh
Inventor
小林德弘
阿贺浩司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shin Etsu Handotai Co Ltd
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Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of CN105283943A publication Critical patent/CN105283943A/zh
Application granted granted Critical
Publication of CN105283943B publication Critical patent/CN105283943B/zh
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/7806—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate
    • H01L21/7813—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices involving the separation of the active layers from a substrate leaving a reusable substrate, e.g. epitaxial lift off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
CN201480032979.9A 2013-06-26 2014-05-19 贴合晶圆的制造方法 Active CN105283943B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2013-133868 2013-06-26
JP2013133868A JP5888286B2 (ja) 2013-06-26 2013-06-26 貼り合わせウェーハの製造方法
PCT/JP2014/002615 WO2014207988A1 (ja) 2013-06-26 2014-05-19 貼り合わせウェーハの製造方法

Publications (2)

Publication Number Publication Date
CN105283943A CN105283943A (zh) 2016-01-27
CN105283943B true CN105283943B (zh) 2018-05-08

Family

ID=52141364

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201480032979.9A Active CN105283943B (zh) 2013-06-26 2014-05-19 贴合晶圆的制造方法

Country Status (8)

Country Link
US (1) US9859149B2 (enExample)
EP (1) EP3016133B1 (enExample)
JP (1) JP5888286B2 (enExample)
KR (1) KR102095383B1 (enExample)
CN (1) CN105283943B (enExample)
SG (1) SG11201510639QA (enExample)
TW (1) TWI567833B (enExample)
WO (1) WO2014207988A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6136786B2 (ja) * 2013-09-05 2017-05-31 信越半導体株式会社 貼り合わせウェーハの製造方法
EP3246937B1 (en) 2015-01-16 2023-05-10 Sumitomo Electric Industries, Ltd. Method for manufacturing semiconductor diamond substrate and semiconductor diamond substrate
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
JP6686962B2 (ja) * 2017-04-25 2020-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013057865A1 (ja) * 2011-10-17 2013-04-25 信越半導体株式会社 剥離ウェーハの再生加工方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963505A (en) * 1987-10-27 1990-10-16 Nippondenso Co., Ltd. Semiconductor device and method of manufacturing same
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3943782B2 (ja) 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
JP4509488B2 (ja) * 2003-04-02 2010-07-21 株式会社Sumco 貼り合わせ基板の製造方法
WO2006042181A1 (en) 2004-10-11 2006-04-20 Meadwestvaco Corporation Blister card for child-resistant package
DE602004018951D1 (de) 2004-11-09 2009-02-26 Soitec Silicon On Insulator Verfahren zum Herstellen von zusammengesetzten Wafern
JP4715470B2 (ja) 2005-11-28 2011-07-06 株式会社Sumco 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ
JP5314838B2 (ja) 2006-07-14 2013-10-16 信越半導体株式会社 剥離ウェーハを再利用する方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013057865A1 (ja) * 2011-10-17 2013-04-25 信越半導体株式会社 剥離ウェーハの再生加工方法

Also Published As

Publication number Publication date
WO2014207988A1 (ja) 2014-12-31
KR20160023712A (ko) 2016-03-03
US20160118294A1 (en) 2016-04-28
SG11201510639QA (en) 2016-01-28
CN105283943A (zh) 2016-01-27
JP2015012009A (ja) 2015-01-19
EP3016133B1 (en) 2020-01-15
KR102095383B1 (ko) 2020-03-31
US9859149B2 (en) 2018-01-02
EP3016133A4 (en) 2017-03-01
JP5888286B2 (ja) 2016-03-16
TW201511141A (zh) 2015-03-16
EP3016133A1 (en) 2016-05-04
TWI567833B (zh) 2017-01-21

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