CN105261607A - 有源区键合兼容高电流的结构 - Google Patents

有源区键合兼容高电流的结构 Download PDF

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CN105261607A
CN105261607A CN201510633289.5A CN201510633289A CN105261607A CN 105261607 A CN105261607 A CN 105261607A CN 201510633289 A CN201510633289 A CN 201510633289A CN 105261607 A CN105261607 A CN 105261607A
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metal layer
layer
welding pad
wire
bonding welding
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约翰·T.·加斯纳
迈克尔·D.·丘奇
萨米尔·D.·帕拉博
小保罗·E.·贝克曼
戴维·A.·德克罗斯塔
罗伯特·L.·罗曼尼科
克里斯·A.·迈克卡迪
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Intersil Corp
Intersil Americas LLC
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Intersil Americas LLC
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Abstract

本发明涉及一种有源区键合兼容高电流的结构。一种在键合焊盘下具有电路的集成电路。在一个实施例中，该集成电路包括：衬底；顶部导电层；一层或多层中间导电层；绝缘材料层和器件。顶部导电层具有至少一个键合焊盘和相对坚硬的材料亚层。一层或多层中间导电层形成于顶部导电层和衬底之间。绝缘材料层分离导电层。而且，绝缘层中的一层相对较硬且位于顶部导电层与最接近顶部导电层的中间导电层之间。器件形成在集成电路中。另外，至少最接近于顶部导电层的中间导电层适合于键合焊盘下的选择器件的实用互连。

Description

有源区键合兼容高电流的结构
本专利申请是申请日为2004年8月20日、申请号为200410095946.7、发明名称为“有源区键合兼容高电流的结构”的发明专利申请的分案申请，其在此全部引入作为参考。
该申请在35U.S.C§119(e)下要求于2003年8月21日提交的U.S.临时申请序列号No.60/496,881和于2003年9月30日提交的U.S.临时申请序列号No.60/507,539(律师案卷分别为No’s125.090USPR和125.090USP2)的优先权，这里将它们并入本文以作参考。
技术领域
本发明涉及半导体器件的构造，更为具体地，涉及在键合焊盘下的有源电路的形成。
背景技术
集成电路包括在半导体材料的衬底之中或之上形成的两个以上的电子器件。一般地，集成电路包括两层以上的用于形成选择器件和所述器件之间的互连的金属层。金属层还向集成电路的输入和输出连接提供电路径。通过键合焊盘来制作集成电路的输入和输出连接。键合焊盘形成在集成电路的顶部金属层上。键合工艺(即球键合布线至键合焊盘的键合)会损伤形成在要形成键合焊盘的金属层下的有源电路。因此，目前的电路布局标准不允许在键合焊盘下形成任何电路或仅允许必须要认真测试的限制结构。
键合焊盘下的损伤由很多种原因引起，但主要取决于在键合布线附着工艺期间发生的应力和随后在封装之后的应力。例如，在封装之后的温度偏移在整个结构上施加横向和垂直力。集成电路的金属层一般由通过较硬的氧化层彼此分离的软铝制成。软铝在压力下易于弯曲而较硬的氧化层不会。这最终导致氧化层中的裂缝。一旦氧化层裂缝，湿气会进入导致铝层的腐蚀并最终导致电路功能失灵。因此，键合工艺一般需要键合焊盘下的固定结构(realestate)仅用作防止在键合工艺期间发生损伤的缓冲层。然而，随着芯片设计师尽力减小芯片的尺寸，期望能够将键合焊盘下的固定结构用于有源电路或互连。
由于上述原因和下述其它原因，这些原因对于本领域技术人员通过阅读和理解本说明书将变得显而易见，在本领域中需要有效允许键合焊盘下的固定结构用于有源电路和互连的改善的集成电路。
发明内容
上述问题和其它问题由本发明来解决并通过阅读和研究下述说明书来理解。
在一个实施例中，公开了一种集成电路。该集成电路包括：衬底；顶部导电层；一层或多层中间导电层；绝缘材料层和器件。顶部导电层具有至少一个键合焊盘和相对坚硬材料的亚层。一层或多层中间导电层形成于顶部导电层和衬底之间。绝缘材料层分离导电层。而且，绝缘层中的一层相对较硬且位于顶部导电层与最接近顶部导电层的中间导电层之间。器件形成在集成电路中。另外，至少最接近于顶部导电层的中间导电层适合于键合焊盘下的选择器件的实用互连。
在另一个实施例中，公开了一种集成电路。该集成电路包括：衬底；器件区；顶部金属层；第二金属层和一层相对较厚的绝缘材料层。器件区形成于衬底上和衬底中。顶部金属层具有形成于其上的一个或多个键合焊盘。器件区位于衬底于顶部金属层之间。第二金属层位于顶部金属层和器件区之间。相对较厚的绝缘材料层将顶部金属层与第二金属层分离。相对较厚的绝缘层适合于抵抗裂缝。
在另一个实施例中，公开了另一种集成电路。该集成电路包括：衬底；多个器件；第二金属层和第一绝缘材料层。多个器件形成于衬底上和衬底中。顶部金属层具有至少一个形成在顶部金属层表面上的键合焊盘。第二金属层位于顶部金属层与衬底之间。而且，第二金属层具有适合于增强集成电路的间隙。第一绝缘材料层形成于顶部金属层和第二金属层之间。
在另一个实施例中，公开了一种形成具有在键合焊盘下的有源电路的集成电路的方法。该方法包括在衬底中和衬底上形成器件；形成第一金属层；形成覆盖第一金属层的第一相对较厚的绝缘材料层，其中绝缘材料的厚度增强集成电路；形成覆盖相对较厚的绝缘材料的顶部金属层和在顶层的表面上形成键合焊盘。
在另一实施例中，公开了一种形成集成电路的方法。该方法包括：在衬底中形成器件区；沉积覆盖器件区的第一金属层；构图第一金属层以形成间隙；其中间隙在电流流动的方向上延伸；形成覆盖第一金属层的绝缘层并填充间隙，其中间隙通过提供较硬绝缘材料的支柱来增强集成电路；沉积覆盖氧化层的金属层并在顶部金属层的表面上形成键合焊盘。
在本发明的又一实施例中，公开了一种形成集成电路的方法。该方法包括：在衬底中和衬底上形成器件区；形成覆盖器件区的第一金属层；形成覆盖第一金属层的绝缘层；形成覆盖绝缘层的包括接近于氧化层的相对较硬的材料亚层的顶部金属层；并在顶部金属层的表面上形成键合焊盘。
附图说明
当考虑到优选实施例的描述和下述附图，将更容易理解本发明，且其进一步的优点和使用将更加显而易见，其中：
图1是根据本发明的一个实施例的集成电路的部分横截面图；
图2是本发明的一个实施例的具有间隙的金属层的部分的顶视图；和
图3A至3G是本发明的一个实施例中的一种形成集成电路的方法的部分横截面图。
根据普通实践，所述的各种特征并非按比例绘制而是为强调与本发明相关的特殊特征来绘制。贯穿附图和全文参考标记表示相似的元件。
具体实施方式
在下述优选实施例的详细说明中，参考附图，附图形成实施例部分的且其中通过示例的方式来示出可以实践本发明的特定优选实施例。充分详细地描述这些实施例以使本领域技术人员可以实践本发明，并理解可以使用其它实施例且可以在不脱离本发明的精神和范围下作出逻辑、机械和电的改变。因此，下述详细描述并非限定意义，且本发明的范围仅由权利要求书和其等同物来限定。
在下述说明中，术语衬底通常用来指在其上形成集成电路的任何结构、以及在集成电路制造的各阶段期间的这种结构。该术语包括掺杂的和未掺杂的半导体、在支撑半导体或绝缘材料上的半导体外延层、这种层的结合、以及其它本领域公知的这类结构。用于该申请中的相对位置的术语根据平行于常规平面或晶片或衬底的工作表面的平面来限定，而无关于晶片或衬底的取向。用于该申请中的术语“水平平面”和“横向平面”限定为平行于常规平面或晶片或衬底的工作表面的平面，而无关于晶片或衬底的取向。术语“垂直”是指垂直于水平的方向。诸如“上”、“侧”(如“侧壁”)、“较高”、“较低”、“之上”、“顶部”和“底部”的术语是相对于常规平面或晶片或衬底的顶表面上的工作表面来限定的，无关于晶片或衬底的取向。
本发明的实施例提供集成电路的方法和结构，该集成电路允许使用键合焊盘下的固定结构来用于有源器件和互连。此外，本发明的实施例提供可以使用键合焊盘下的所有金属层用于器件的实用互连的结构。另外，本发明的实施例还提供允许使用TiN顶层的亚微米互连线和能够承载高电流的相对较宽的线同时存在于键合焊盘下面的结构。
图1，示出本发明的一个实施例的集成电路100的部分横截面图。在该实施例中，示出的集成电路100的部分包括：N沟道MOS功率器件102、N-DOMS器件104和NPN双极性器件106。图1还示出三层导电层，在该实施例中，这三层导电层包括第一金属层M1108、第二金属层M2110和第三金属层M3112。金属层108、110和112可以由诸如铝、铜等导电材料制成。此外，在另一实施例中，金属层108、110和112的其中至少一层通过形成许多交替导电层的亚层的亚微米工艺制成。第三金属层M3112可以称为顶部金属层112。如示出，通过构图钝化层132在第三金属层M3112的表面上形成键合焊盘130。球键合布线114(键合布线114)可以耦合于键合焊盘130以提供到集成电路100的输入和输出。虽然，该实施例仅示出三层金属层108、110和112，其它实施例具有更多或更少的金属层。例如，在多于三层金属层的实施例中，附加的金属层形成在金属层108和110之间。通过本领域公知的诸如沉积和构图的常规方法来形成每一互连金属层108、110和112。
如图1中所示，通路116选择性地耦合于互连金属层110和108以在集成电路100的器件102、104和106之间形成电互连。还示出提供到器件102、104和106的元件和第一金属层108的电互连的通路118。
在一个实施例中，使用亚微米工艺来形成金属层M2110和金属层M3112。亚微米工艺使用许多亚层来形成金属层。在一个实施例中，亚层为Ti、TiN和Al合金的交替层。在一个实施例中，金属层110的亚层的顶层(即面对金属112的亚层)为TiN层120。TiN层120用于该位置，是由于其有助于金属层110构图的低反射特性。然而，亚层120的存在易于增加在分离金属层110与金属层112的氧化层中形成裂缝的可能性。特别是，由于TiN层很硬，当施加应力时其不能弯曲。结果，在分离氧化层上的横向应力易于在分离氧化层中形成裂缝。此外，在另一实施例中，一层TiW形成亚层120。
本发明的实施例减小在分离氧化层122中形成裂缝的可能性。在一个实施例中，将分离氧化层122(即分离金属层110与金属层112的氧化层)形成的相对较厚。在一个实施例中，将分离氧化层122形成为至少1.5μm厚。相对较厚的分离氧化层122的使用减小了在氧化层122中形成裂缝的可能性。在另一实施例中，分离氧化层通常为电介质或绝缘层。
此外在一个实施例中，第三金属层M3112包括非常坚硬材料的相对较硬的亚层126。将硬亚层126形成为相邻于分离氧化层122并相对于形成键合焊盘114的第三金属层的一侧。硬亚层126相比于铝非常坚硬。硬亚层在氧化层122的较大区域上分布横向和垂直应力，由此减小氧化层122中的裂缝倾向。在一个实施例中，用于硬亚层126的材料为TiN。这取决于TiN与常规亚微米沉积和蚀刻技术的适应性。在另一实施例中，硬亚层126为氮化物层。在一个实施例中，硬亚层126近似80nm厚。在另一实施例中，诸如TiW的材料用于硬亚层126。
在另一实施例中，形成在被选择的区域中具有间隙124的第二金属层M2110。非常宽(横向宽度)的第二金属层110易于使结构变弱，因此使在分离氧化层122出现裂缝的几率更高。在该实施例中，间隙124易于通过提供较硬的氧化物柱体来增强该结构。通过正确的布图使间隙124在集成电路功能上的影响最小化。即，可以使间隙的密度最小化以便于布图设计不受显著限制。在一个实施例中，间隙124占键合焊盘下的第二金属层M2110的总面积的不足10％。在另一个实施例中，间隙如此趋向以便于最小化对流经第二金属层M2110的电流的影响。在图2中示出形成最小化对流经第二金属层M2中的电流的影响的间隙124的实例。图3还示出第三金属层112。
图3A至3G示出本发明的一个实施例的相关方面的形成。图3A示出在衬底301上的集成电路300形成开始的部分横截面侧视图。该部分横截面侧视图示出该实施例中的集成电路300包括：N沟道MOS302、N-DMOS304和NPN器件306。本领域人员会理解可以在集成电路300中形成其它类型的器件且本发明不限于仅具有N沟道MOS、N-DMOS和NPN器件的集成电路。由于器件302、304和306的形成并非本发明的特征部分，图3A示出已经形成它们。通过诸如沉积、蚀刻掩模和注入的本领域公知技术来形成这些器件302、304和306。形成覆盖器件302、304和306的第一绝缘层308。在一个实施例中，绝缘层308为第一氧化层308的一层。通过诸如掩模和蚀刻的本领域公知技术来形成通路310。然后由导电材料填充通路310以形成与第一金属层312和器件302、304以及306的接触。通过首先沉积金属层然后构图第一金属层312以形成选择互连来形成第一金属层312。然后形成覆盖第一金属层M1312和第一氧化层308的暴露区域的第二绝缘层314。在一个实施例中，第二绝缘层314为第二氧化层314。通过掩模第二氧化层的表面来在第二氧化层314中形成通路并向下蚀刻通路316到被构图的第一金属层312的选择的部分。然后用导电材料填充通路316。
参考图3B，在第二氧化层的表面上沉积第二金属层M2318。在一个实施例中，通过包括多个交替不同金属层的亚微米工艺形成第二金属层318。在一个实施例中，交替金属层为Ti、TiN和Al合金。第二金属层M2318的顶部亚层320由有助于第二金属层M2318构图的TiN制成。在图3C中示出顶部亚层320。如图3中示出，在该实施例中，然后构图第二金属层318以形成间隙322。间隙322通过提供坚硬氧化物柱体来增强结构。然后形成覆盖第二金属层M2的第三绝缘层324。这在图3D中示出。在一个实施例中，第三绝缘层324为第三氧化层324。第三氧化层324还填充间隙322。在一个实施例中，形成相对较厚的第三氧化层324(分离氧化层324)。此外，在一个实施例中分离氧化层324的厚度为至少1.5μm。
然后在分离氧化层324的表面上形成一层相对较坚硬的金属层326。这在图3E中示出。该硬层326在分离氧化层324的较大区域上分布横向和垂直应力。由一层诸如TiN或SiN的氮化物层形成一些实施例的硬层326。在另一实施例中，由一层TiW形成硬层326。而且，在一个实施例中，硬层326形成近似80nm厚。参考图3F，形成覆盖硬层326的第三金属层M3328。在一个实施例中，硬层326为在第三金属层M3328形成期间通过常规亚微米沉积和蚀刻技术形成的亚层。在另一实施例中(未示出)，硬层326为接近于分离氧化层324形成的第三金属层M3328的亚层。然后在第三金属层M3328的上表面上通过构图沉积的钝化层332来形成键合焊盘330。这在图3G中示出。在图3G中还示出，然后将球形键合布线334耦合于键合焊盘330。虽然，未在图中示出，在相对较厚的氧化层324中形成通路以便于顶部金属层328还可以用于互连器件。此外，在本领域中会理解单个集成电路可以具有多个键合焊盘且本发明不限于单个键合焊盘。
虽然已经在本文中示出并描述了具体的实施例，本领域普通技术人员会理解，计划获得相同目的的任何布置可以替代示出的具体实施例。该申请旨在覆盖本发明的任何修改和变化。因此，主要目的是该发明仅由权利要求书及其等同物来限定。

Claims (6)

1.一种形成半导体结构的方法，该方法包括：
在衬底上形成一个或多个中间金属层；
在所述一个或多个中间金属层上形成顶部金属层，其中，所述一个或多个中间金属层和所述顶部金属层通过绝缘材料的相应部分而被彼此分离；
在所述顶部金属层上形成钝化层；以及
对所述钝化层进行构图以暴露所述顶部金属层的一部分，所述顶部金属层的暴露部分包括键合焊盘；
在所述顶部金属层的暴露部分正下方形成一个或多个导线，所述一个或多个导线中的每个导线由所述一个或多个中间金属层中的相应一个中间金属层的部分形成；
其中，在所述顶部金属层的暴露部分正下方的所述一个或多个导线通过绝缘材料与所述键合焊盘电隔离；
其中，在所述键合焊盘和位置最接近顶部金属层的在下面的导线之间形成的绝缘材料的相应部分具有至少1.5微米的厚度，
其中，在绝缘材料的相应部分的所述键合焊盘下面的区域不被通孔中断。
2.根据权利要求1所述的方法，还包括：在所述键合焊盘之下的所述一个或多个导线中的至少一个导线的部分中形成一个或多个间隙。
3.根据权利要求2所述的方法，还包括：形成所述一个或多个间隙，以在电流流动的方向上延伸通过在所述顶部金属层的暴露部分正下方的至少一个导线的部分。
4.一种半导体结构，包括：
衬底；
在所述衬底上的一个或多个中间金属层；
在所述一个或多个中间金属层上的顶部金属层，其中，所述一个或多个中间金属层和所述顶部金属层通过绝缘材料的相应部分而被彼此分离；
在所述顶部金属层上叠加的钝化层，所述钝化层被构图以暴露所述顶部金属层的表面，所述顶部金属层的暴露表面包括键合焊盘；以及
在所述顶部金属层之下的一个或多个导线，所述一个或多个导线中的每个导线由所述一个或多个中间金属层中的相应一个中间金属层的部分形成，位于所述顶部金属层的暴露部分正下方的所述一个或多个导线通过绝缘材料的相应部分与所述键合焊盘电隔离；
其中，在所述键合焊盘和位于所述键合焊盘之下的最接近的导线之间的绝缘材料的相应部分具有至少1.5微米的厚度，
其中，在所述键合焊盘下面的区域中的绝缘材料的相应部分中不存在通孔。
5.根据权利要求4所述的半导体结构，还包括：位置在所述键合焊盘之下的所述一个或多个导线中的至少一个导线的部分中的一个或多个间隙。
6.根据权利要求5所述的半导体结构，其中，所述一个或多个间隙在电流流动的方向上延伸通过所述键合焊盘之下的至少一个导线的部分。
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