CN105190760A - 在存储器系统中并行地使用具有nmos通过门和pmos通过门两者的sram单元 - Google Patents
在存储器系统中并行地使用具有nmos通过门和pmos通过门两者的sram单元 Download PDFInfo
- Publication number
- CN105190760A CN105190760A CN201380067878.0A CN201380067878A CN105190760A CN 105190760 A CN105190760 A CN 105190760A CN 201380067878 A CN201380067878 A CN 201380067878A CN 105190760 A CN105190760 A CN 105190760A
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- Prior art keywords
- word line
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- memory unit
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims (22)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261725163P | 2012-11-12 | 2012-11-12 | |
US61/725,163 | 2012-11-12 | ||
PCT/US2013/067454 WO2014074362A1 (en) | 2012-11-12 | 2013-10-30 | Concurrent use of sram cells with both nmos and pmos pass gates in a memory system |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105190760A true CN105190760A (zh) | 2015-12-23 |
CN105190760B CN105190760B (zh) | 2018-04-24 |
Family
ID=50681563
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201380067878.0A Expired - Fee Related CN105190760B (zh) | 2012-11-12 | 2013-10-30 | 在存储器系统中并行地使用具有nmos通过门和pmos通过门两者的sram单元 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9142284B2 (zh) |
CN (1) | CN105190760B (zh) |
TW (1) | TWI613650B (zh) |
WO (1) | WO2014074362A1 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9042159B2 (en) | 2012-10-15 | 2015-05-26 | Marvell World Trade Ltd. | Configuring resistive random access memory (RRAM) array for write operations |
US9047945B2 (en) | 2012-10-15 | 2015-06-02 | Marvell World Trade Ltd. | Systems and methods for reading resistive random access memory (RRAM) cells |
US8885388B2 (en) | 2012-10-24 | 2014-11-11 | Marvell World Trade Ltd. | Apparatus and method for reforming resistive memory cells |
US9042162B2 (en) | 2012-10-31 | 2015-05-26 | Marvell World Trade Ltd. | SRAM cells suitable for Fin field-effect transistor (FinFET) process |
CN105190760B (zh) | 2012-11-12 | 2018-04-24 | 马维尔国际贸易有限公司 | 在存储器系统中并行地使用具有nmos通过门和pmos通过门两者的sram单元 |
ITUA20163999A1 (it) * | 2016-05-31 | 2017-12-01 | St Microelectronics Srl | Dispositivo di memoria con lettura progressiva di riga e relativo metodo di lettura |
KR102553181B1 (ko) * | 2016-07-12 | 2023-07-10 | 에스케이하이닉스 주식회사 | 메모리 장치 및 메모리 장치의 동작 방법 |
US11170844B1 (en) | 2020-07-07 | 2021-11-09 | Aril Computer Corporation | Ultra-low supply-voltage static random-access memory (SRAM) with 8-transistor cell with P and N pass gates to same bit lines |
US11984151B2 (en) | 2021-07-09 | 2024-05-14 | Stmicroelectronics International N.V. | Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) |
US11942145B2 (en) * | 2021-07-16 | 2024-03-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Static random access memory layout |
Citations (6)
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EP0011448A1 (en) * | 1978-11-14 | 1980-05-28 | Fujitsu Limited | Semiconductor memory device |
US5706226A (en) * | 1996-12-31 | 1998-01-06 | Sgs-Thomson Microelectronics, Inc. | Low voltage CMOS SRAM |
CN1956098A (zh) * | 2005-08-02 | 2007-05-02 | 株式会社瑞萨科技 | 半导体存储装置 |
US20090243652A1 (en) * | 2003-12-24 | 2009-10-01 | Nij Dorairaj | Incrementer based on carry chain compression |
US20100157706A1 (en) * | 2008-12-19 | 2010-06-24 | Sun Microsystems, Inc. | Methods and apparatuses for improving reduced power operations in embedded memory arrays |
US20100296336A1 (en) * | 2009-05-21 | 2010-11-25 | Texas Instruments Incorporated | 8T SRAM Cell with Two Single Sided Ports |
Family Cites Families (40)
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JPH05325557A (ja) | 1992-05-26 | 1993-12-10 | Mitsubishi Electric Corp | 半導体記憶装置 |
GB2376781B (en) | 2001-03-29 | 2003-09-24 | Mentor Graphics Corp | Memory device |
JP4187148B2 (ja) | 2002-12-03 | 2008-11-26 | シャープ株式会社 | 半導体記憶装置のデータ書き込み制御方法 |
JP4290457B2 (ja) | 2003-03-31 | 2009-07-08 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
DE102004047666B4 (de) | 2004-09-30 | 2015-04-02 | Qimonda Ag | Speicher mit Widerstandsspeicherzelle und Bewertungsschaltung |
US7495944B2 (en) | 2005-03-30 | 2009-02-24 | Ovonyx, Inc. | Reading phase change memories |
US7570524B2 (en) | 2005-03-30 | 2009-08-04 | Ovonyx, Inc. | Circuitry for reading phase change memory cells having a clamping circuit |
US8000127B2 (en) | 2009-08-12 | 2011-08-16 | Nantero, Inc. | Method for resetting a resistive change memory element |
US7286385B2 (en) * | 2005-07-27 | 2007-10-23 | International Business Machines Corporation | Differential and hierarchical sensing for memory circuits |
US7423911B2 (en) * | 2005-09-29 | 2008-09-09 | Hynix Semiconductor Inc. | Bit line control circuit for semiconductor memory device |
US7436708B2 (en) * | 2006-03-01 | 2008-10-14 | Micron Technology, Inc. | NAND memory device column charging |
JPWO2007138646A1 (ja) | 2006-05-25 | 2009-10-01 | 株式会社日立製作所 | 不揮発性メモリ素子およびその製造方法ならびに不揮発性メモリ素子を用いた半導体装置 |
JP2008146740A (ja) | 2006-12-08 | 2008-06-26 | Sharp Corp | 半導体記憶装置 |
KR100855585B1 (ko) | 2007-01-23 | 2008-09-01 | 삼성전자주식회사 | 소오스 라인 공유구조를 갖는 저항성 랜덤 억세스 메모리및 그에 따른 데이터 억세스 방법 |
EP2149884B1 (en) | 2007-05-18 | 2013-06-19 | Fujitsu Semiconductor Limited | Semiconductor memory |
JP4253038B2 (ja) | 2007-06-05 | 2009-04-08 | パナソニック株式会社 | 不揮発性記憶素子およびその製造方法、並びにその不揮発性記憶素子を用いた不揮発性半導体装置 |
US8068367B2 (en) | 2007-06-15 | 2011-11-29 | Micron Technology, Inc. | Reference current sources |
JP2009026382A (ja) | 2007-07-19 | 2009-02-05 | Hitachi Ltd | 半導体記憶装置 |
WO2009013819A1 (ja) | 2007-07-25 | 2009-01-29 | Renesas Technology Corp. | 半導体記憶装置 |
JP4356786B2 (ja) | 2007-12-12 | 2009-11-04 | ソニー株式会社 | 記憶装置および情報再記録方法 |
KR20090126587A (ko) | 2008-06-04 | 2009-12-09 | 삼성전자주식회사 | 상 변화 메모리 장치 및 그것의 읽기 방법 |
US7881096B2 (en) | 2008-10-08 | 2011-02-01 | Seagate Technology Llc | Asymmetric write current compensation |
CN101933096A (zh) | 2008-10-21 | 2010-12-29 | 松下电器产业株式会社 | 非易失性存储装置及向其存储单元的写入方法 |
US7852661B2 (en) | 2008-10-22 | 2010-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Write-assist SRAM cell |
US7974117B2 (en) | 2008-10-30 | 2011-07-05 | Seagate Technology Llc | Non-volatile memory cell with programmable unipolar switching element |
US7944730B2 (en) | 2008-10-31 | 2011-05-17 | Seagate Technology Llc | Write method with voltage line tuning |
JP5287197B2 (ja) | 2008-12-09 | 2013-09-11 | ソニー株式会社 | 半導体装置 |
US8159863B2 (en) * | 2009-05-21 | 2012-04-17 | Texas Instruments Incorporated | 6T SRAM cell with single sided write |
TWI455129B (zh) | 2010-07-16 | 2014-10-01 | Univ Nat Chiao Tung | 以史密特觸發器為基礎的鰭狀場效電晶體靜態隨機存取記憶體 |
KR101772019B1 (ko) | 2010-09-14 | 2017-08-28 | 삼성전자주식회사 | 저항성 메모리 장치 및 저항성 메모리 장치의 리프레시 제어 방법 |
US8451652B2 (en) | 2010-12-02 | 2013-05-28 | Lsi Corporation | Write assist static random access memory cell |
US8441842B2 (en) | 2010-12-21 | 2013-05-14 | Lsi Corporation | Memory device having memory cells with enhanced low voltage write capability |
US8942024B2 (en) | 2011-12-06 | 2015-01-27 | Agency For Science, Technology And Research | Circuit arrangement and a method of writing states to a memory cell |
US8760927B2 (en) | 2012-01-17 | 2014-06-24 | Texas Instruments Incorporated | Efficient static random-access memory layout |
US8817528B2 (en) | 2012-08-17 | 2014-08-26 | Globalfoundries Inc. | Device comprising a plurality of static random access memory cells and method of operation thereof |
US9047945B2 (en) | 2012-10-15 | 2015-06-02 | Marvell World Trade Ltd. | Systems and methods for reading resistive random access memory (RRAM) cells |
US9042159B2 (en) | 2012-10-15 | 2015-05-26 | Marvell World Trade Ltd. | Configuring resistive random access memory (RRAM) array for write operations |
US8885388B2 (en) | 2012-10-24 | 2014-11-11 | Marvell World Trade Ltd. | Apparatus and method for reforming resistive memory cells |
US9042162B2 (en) | 2012-10-31 | 2015-05-26 | Marvell World Trade Ltd. | SRAM cells suitable for Fin field-effect transistor (FinFET) process |
CN105190760B (zh) | 2012-11-12 | 2018-04-24 | 马维尔国际贸易有限公司 | 在存储器系统中并行地使用具有nmos通过门和pmos通过门两者的sram单元 |
-
2013
- 2013-10-30 CN CN201380067878.0A patent/CN105190760B/zh not_active Expired - Fee Related
- 2013-10-30 WO PCT/US2013/067454 patent/WO2014074362A1/en active Application Filing
- 2013-10-30 US US14/066,796 patent/US9142284B2/en active Active
- 2013-10-31 TW TW102139579A patent/TWI613650B/zh not_active IP Right Cessation
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0011448A1 (en) * | 1978-11-14 | 1980-05-28 | Fujitsu Limited | Semiconductor memory device |
US5706226A (en) * | 1996-12-31 | 1998-01-06 | Sgs-Thomson Microelectronics, Inc. | Low voltage CMOS SRAM |
US20090243652A1 (en) * | 2003-12-24 | 2009-10-01 | Nij Dorairaj | Incrementer based on carry chain compression |
CN1956098A (zh) * | 2005-08-02 | 2007-05-02 | 株式会社瑞萨科技 | 半导体存储装置 |
US20100157706A1 (en) * | 2008-12-19 | 2010-06-24 | Sun Microsystems, Inc. | Methods and apparatuses for improving reduced power operations in embedded memory arrays |
US20100296336A1 (en) * | 2009-05-21 | 2010-11-25 | Texas Instruments Incorporated | 8T SRAM Cell with Two Single Sided Ports |
Also Published As
Publication number | Publication date |
---|---|
CN105190760B (zh) | 2018-04-24 |
TW201432686A (zh) | 2014-08-16 |
TWI613650B (zh) | 2018-02-01 |
WO2014074362A1 (en) | 2014-05-15 |
US20140133217A1 (en) | 2014-05-15 |
US9142284B2 (en) | 2015-09-22 |
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C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
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TR01 | Transfer of patent right |
Effective date of registration: 20200429 Address after: Ford street, Grand Cayman, Cayman Islands Patentee after: Kaiwei international Co. Address before: Hamilton, Bermuda Patentee before: Marvell International Ltd. Effective date of registration: 20200429 Address after: Singapore City Patentee after: Marvell Asia Pte. Ltd. Address before: Ford street, Grand Cayman, Cayman Islands Patentee before: Kaiwei international Co. Effective date of registration: 20200429 Address after: Hamilton, Bermuda Patentee after: Marvell International Ltd. Address before: Babado J San Mega Le Patentee before: MARVELL WORLD TRADE Ltd. |
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CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180424 Termination date: 20211030 |