CN105140270B - 一种增强型hemt器件 - Google Patents

一种增强型hemt器件 Download PDF

Info

Publication number
CN105140270B
CN105140270B CN201510456018.7A CN201510456018A CN105140270B CN 105140270 B CN105140270 B CN 105140270B CN 201510456018 A CN201510456018 A CN 201510456018A CN 105140270 B CN105140270 B CN 105140270B
Authority
CN
China
Prior art keywords
layer
barrier layer
hemt device
contrapolarization
source electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510456018.7A
Other languages
English (en)
Other versions
CN105140270A (zh
Inventor
罗小蓉
熊佳云
杨超
魏杰
吴俊峰
彭富
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN201510456018.7A priority Critical patent/CN105140270B/zh
Publication of CN105140270A publication Critical patent/CN105140270A/zh
Priority to US14/979,488 priority patent/US9431527B1/en
Application granted granted Critical
Publication of CN105140270B publication Critical patent/CN105140270B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0646—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

本发明属于半导体技术领域，具体的说涉及一种增强型HEMT器件。本发明主要通过在栅漏之间的势垒层上表面生长一层反向极化层，反向极化层与势垒层产生反向极化并在异质结界面处形成二维空穴气(2DHG)，反向极化层/势垒层/缓冲层形成极化超结；同时，金属栅极不再位于源极和漏极之间而是通过刻蚀凹槽在远离漏极的源极边缘形成绝缘栅电极。一方面，2DHG夹断源极与二维电子气(2DEG)之间的纵向导电沟道，由凹槽栅电极上施加电压实现对导电沟道的电场控制，从而实现增强型，且可通过对导电沟道部分进行掺杂实现对阈值电压的调控；另一方面，栅漏之间的极化超结在阻断状态时辅助耗尽漂移区，优化器件的横向电场分布，提高器件耐压。

Description

一种增强型HEMT器件
技术领域
本发明属于半导体技术领域，具体的说涉及一种增强型HEMT(High ElectronMobility Transistor，高电子迁移率晶体管)器件。
背景技术
宽禁带半导体氮化镓(GaN)具有高临界击穿电场(～3.3×106V/cm)、高电子迁移率(～2000cm2/V·s)等特性，且基于GaN材料的异质结高电子迁移率晶体管(HEMT)还具有高浓度(～1013cm-2)的二维电子气(2DEG)，使得GaN HEMT器件具有反向阻断电压高、正向导通电阻低、工作频率高等特性，在大电流、低功耗、高压开关器件应用领域具有巨大的应用前景。
对于AlGaN/GaN HEMT器件而言，增强型(常关型)HEMT器件比耗尽型(常开型)HEMT器件具有更多的优势，其实现技术是研究者们极其关注的问题。文献(X.Hu,et.al.,“Enhancement mode AlGaN/GaN HFET with selectively grown pn junction gate,”Electron.Lett.vol.36,no.8,pp.753-754,Apr.2000)报道了采用P型GaN栅实现了一种增强型AlGaN/GaN HEMT器件，如图1所示，但是高浓度的P型掺杂在目前的工艺中还很难实现。文献(Li Yuan,Hongwei Chen,and Kevin J.Chen,“Normally Off AlGaN/GaN Metal–2DEGTunnel-Junction Field-Effect Transistors”IEEE Electron Device Letters,vol.32,no.3,pp.303-305,2011)报道了采用肖特基源极实现增强型，通过栅极上加压场控肖特基源极与势垒层之间的势垒高度和厚度，产生隧穿电流，如图2所示，但是该方式实现增强型的阈值电压难以调控，且隧穿电流限制了器件的最大饱和输出电流，肖特基栅极结构还使得阈值电压越大时栅压摆幅越小，影响器件的可靠性。文献(W.Saito,et.al.,“Recessed-gate structure approach toward normally off high-voltage AlGaN/GaN HEMT forpower electronics applications,”IEEE Trans.Electron Devices,vol.53,no.2,pp.356-362,Feb.2006)报道了采用槽栅结构实现了一种准增强型高压AlGaN/GaN HEMT，凹栅刻蚀能够有效地耗尽栅极下方2DEG浓度，极大地提高阈值电压，但是凹栅刻蚀需要精确地控制刻蚀深度和降低等离子体处理引起的刻蚀损伤。
功率开关器件的另一个关键是实现高击穿电压、低导通电阻和高可靠性。HEMT器件的击穿主要是由于栅肖特基结的泄漏电流和通过缓冲层的泄漏电流引起的，而栅靠漏端的高电场加剧了泄漏电流的产生。为了充分利用GaN材料的高临界击穿电场等优异特性，提高器件耐压，业内研究者进行了许多研究。其中场板技术是一种用来改善器件耐压的常用终端技术，文献(J.Li,et.al.“High breakdown voltage GaN HFET with field plate”IEEE Electron Lett.,vol.37,no.3,pp.196-197,February.2001.)采用了与栅短接的场板，如图3所示，场板的引入可以降低主结的曲率效应和电场尖峰，从而提高耐压。然而场板的引入会使器件寄生电容增大，影响器件的高频和开关特性。文献(Young-Shil Kim,et.al.“High Breakdown Voltage AlGaN/GaN HEMT by Employing Selective FluoridePlasma Treatment”,Proc.ISPSD,San Diego,CA,May 2011)在栅漏之间的势垒层中引入低浓度的氟离子，使势垒层荷电(具有负电荷)，带负电性的氟离子可有效调制器件表面电场，使器件横向电场分布更加均匀，从而提高器件的击穿电压，且不会引入附加寄生电容。但是在势垒层中注入氟离子，一方面会对势垒层材料造成损伤；另一方面，较薄的势垒层使得氟离子的分布难以控制，且位于势垒层的氟离子距离2DEG沟道很近，会减小沟道中电子的浓度和迁移率，最终都会较大的影响器件的电流能力，且会引起可靠性下降。文献(AkiraNakajima,et.al.“GaN-Based Super Heterojunction Field Effect Transistors Usingthe Polarization Junction Concept”IEEE Electron Device Letters,vol.32,no.4,pp.542-544,2011)采用极化超结的思想，在漂移区部分的AlGaN势垒层上方生长一层顶层GaN，并在其界面形成二维空穴气(2DHG)，2DHG与其下方的2DEG形成天然的“超结”，在阻断耐压时，辅助耗尽漂移区，优化器件横向电场，从而达到提高耐压的目的，如图4所示，但是顶层GaN与栅电极形成了空穴的欧姆接触，在正向导通时，栅压较大时会产生栅极泄漏电流，限制了栅压摆幅。
发明内容
本发明所要解决的，就是针对上述问题，提出一种增强型HEMT器件。
为实现上述目的，本发明采用如下技术方案：
一种增强型HEMT器件，如图5所示，包括衬底1、位于衬底1上层的缓冲层2和位于缓冲层2上层的势垒层3，所述缓冲层2与势垒层3的接触面形成具有二维电子气(2DEG)沟道的第一异质结；所述势垒层3上表面的一端具有与势垒层3形成欧姆接触的漏电极5；其特征在于，所述势垒层3上表面具有能与其产生反向极化的反极化半导体层4，所述反极化半导体层4与势垒层3的接触面形成具有二维空穴气(2DHG)的第二异质结；所述反极化半导体层4上表面远离漏电5的一端具有源电极6，所述源电极6与反极化半导体层4的连接界面形成电子的势阱；所述漏电极5与反极化半导体层4之间具有空穴阻断区9；所述源电极6远离漏电极5的一侧具有凹槽，所述凹槽的底部位于缓冲层2中，所述凹槽的底部与侧壁具有绝缘栅介质7，所述绝缘栅介质7沿源电极6上表面向靠近漏电极5的方向延伸，所述绝缘介质7与覆盖在绝缘介质7上的金属栅电极8构成绝缘栅极结构。
本发明总的技术方案，为了充分利用GaN基材料的高临界击穿电场和高电子饱和速度等特性，实现增强型且提升器件耐压，本发明提出一种双向极化增强型HEMT器件。本发明的方案通过在栅漏之间的势垒层上表面生长一层反向极化层，反向极化层与势垒层产生反向极化并在其界面处形成2DHG；此外，金属栅极不再位于源极和漏极之间而是通过刻蚀凹槽在远离漏极的源极边缘形成绝缘栅电极。一方面，2DHG夹断源极与2DEG之间的纵向导电沟道，由凹槽栅电极上施加的电压实现对导电沟道的电场控制，从而实现增强型，且可通过对导电沟道部分进行掺杂实现对阈值电压的调控；另一方面，源漏之间的2DHG与2DEG形成极化超结，阻断状态时辅助耗尽漂移区，优化器件的横向电场，提高器件耐压。与此同时，本发明所公布的器件制备工艺与传统工艺兼容，从而为GaN功率集成技术奠定了良好基础。
进一步的，所述空穴阻断区9为采用刻槽方式形成。
本方案所述的刻槽方式，是指采用刻蚀工艺将与漏电极连接的半导体层刻蚀掉，形成空槽从而实现物理阻断。
进一步的，所述空穴阻断区9为采用离子注入方式形成。
本方案所述的离子注入方式是指采用离子注入工艺在半导体层中注入能阻断二维空穴气的半导体杂质。
进一步的，所述反极化半导体层4采用阶梯掺杂或线性掺杂。
进一步的，所述反极化半导体层4靠近源电极5的一端掺杂有P型半导体杂质。
进一步的，所述空穴阻断区9为在反极化半导体层4中注入N型半导体杂质形成。
进一步的，所述源电极6与漏电极5之间的反极化半导体层4上表面具有介质钝化层10。
进一步的，所述反极化半导体层4采用的材料为Si、SiC、GaN、AlN、AlGaN、InGaN、InAlN中的一种或几种的组合。
进一步的，所述缓冲层2和势垒层3采用的材料为GaN、AlN、AlGaN、InGaN、InAlN中的一种或几种的组合。
进一步的，所述衬底1采用的材料为蓝宝石、Si、SiC、AlN、GaN、AlGaN中的一种或几种的组合。
本发明的有益效果为，
1.通常由于极化产生的2DEG使得AlGaN/GaN材料体系是常开型沟道，而本发明中采用反向极化，利用高浓度的2DHG形成电子的势垒实现了常关型沟道，使得器件更加利于控制。
2.为充分利用GaN材料的高临界击穿电场特性，本发明中采用反向极化层/势垒层/缓冲层形成双向极化(极化超结)结构，阻断状态时，2DHG辅助耗尽漂移区，获得极大的耐压提升。
3.本发明栅电极位于源极远离漏极的一侧，且与源极紧邻，使得栅电极不易受高电场的破坏，同时器件的有效面积得以缩小。
4.本发明双向极化增强型AlGaN/GaN HEMT可以与传统工艺兼容。
附图说明
图1是具有p型盖帽层的增强型HEMT器件结构示意图；
图2是具有肖特基源极的隧穿增强型HEMT器件结构示意图；
图3是栅场板的HEMT器件结构示意图；
图4是具有与栅电极电气相连的极化超结HEMT器件结构示意图；
图5是实施例1的HEMT器件结构示意图；
图6是实施例2的HEMT器件结构示意图；
图7是实施例3的HEMT器件结构示意图；
图8是实施例4的HEMT器件结构示意图；
图9是本发明提出的双向极化增强型HEMT器件结构IV曲线图；
图10是本发明提出的双向极化增强型HEMT器件结构转移特性曲线图。
具体实施方式
下面结合附图和实施例，详细描述本发明的技术方案：
实施例1
如图5所示，包括衬底1、位于衬底1上层的缓冲层2和位于缓冲层2上层的势垒层3，所述缓冲层2与势垒层3的接触面形成具有二维电子气(2DEG)沟道的第一异质结；所述势垒层3上表面的一端具有与势垒层3形成欧姆接触的漏电极5；其特征在于，所述势垒层3上表面具有能与其产生反向极化的反极化半导体层4，所述反极化半导体层4与势垒层3的接触面形成具有二维空穴气(2DHG)的第二异质结；所述反极化半导体层4上表面远离漏电5的一端具有源电极6，所述源电极6与反极化半导体层4的连接界面形成电子的势阱；所述漏电极5与反极化半导体层4之间具有空穴阻断区9；所述源电极6远离漏电极5的一侧具有凹槽，所述凹槽的底部位于缓冲层2中，所述凹槽的底部与侧壁具有绝缘栅介质7，所述绝缘栅介质7沿源电极6上表面向靠近漏电极5的方向延伸，所述绝缘介质7与覆盖在绝缘介质7上的金属栅电极8构成绝缘栅极结构。
本例的工作原理为：首先，本例提出了一种新的实现增强型的方法，采用反向极化，利用高浓度的2DHG形成电子的势垒实现了常关型沟道，栅电极加压时使源极与2DEG之间的纵向导电沟道导通；其次，本发明中采用反向极化层/势垒层/缓冲层形成2DHG与2DEG构成的极化超结结构，阻断状态时，2DHG辅助耗尽漂移区，优化器件横向电场分布，获得极大的耐压提升；最后，本发明栅电极位于源极远离漏极的一侧，且与源极紧邻，使得栅电极不易受高电场的破坏，同时器件的有效面积得以缩小。
实施例2
本例为采用离子注入阻断空穴的极化超结隧穿增强型HEMT器件，与实施例1相比，本例器件在反向极化层4与漏电极5之间采用高浓度的N型离子注入实现空穴阻断区9，避免源极与漏极之间形成空穴导电通道；同时，在源漏之间的部分反向极化层中形成P型掺杂区域，避免电子从源极到漏极的泄漏路径，其他结构与实施例1相同，如图6所示。漏电极与源电极之间形成的NP结在器件阻断状态时也起到承受耐压的作用。常规的HEMT器件中的隔离方式主要有槽隔离与离子注入隔离，相对于槽隔离，离子注入隔离更易实现，且对材料的损伤更小。
实施例3
本例为反向极化层位于源电极下方部分采用N型掺杂的增强型HEMT器件，与实施例1相比，本例器件在反向极化层4中位于源极下方的部分采用N型掺杂，其他结构与实施例1相同，如图7所示。源电极下方的N型掺杂部分，一方面可以使源极金属与反向极化层更好的形成欧姆接触；另一方面，N型掺杂调制2DHG浓度，从而对阈值电压进行调控；反向极化层中其他部分可以进行阶梯掺杂或线性掺杂，进一步优化器件漂移区横向电场分布，提高耐压。
实施例4
本例为具有介质钝化层的双向极化增强型HEMT器件，与实施例1相比，本例器件在源漏之间的反向极化层4上表面形成介质钝化层10，其他结构与实施例1相同，如图8所示。采用介质钝化层可以改善器件的表面态，抑制电流崩塌。所述介质钝化层材料可以采用与栅介质相同的材料且同时形成，或者采用SiNx、Al2O3、AlN等常用介质材料。
本发明的上述几种实施例所描述的双向极化增强型HEMT器件，可以采用蓝宝石、Si、SiC、AlN、GaN、AlGaN中的一种或几种的组合作为衬底层1的材料；可以采用GaN、AlN、AlGaN中的一种或几种的组合作为缓冲层2的材料；可以采用GaN、AlN、AlGaN、InGaN、InAlN中的一种或几种的组合作为势垒层3的材料；可以采用Si、SiC、GaN、AlN、AlGaN、InGaN、InAlN中的一种或几种的组合作为反极化半导体层4的材料；源电极6、漏电极5一般采用金属合金，常用的有Ti/Al/Ni/Au或Mo/Al/Mo/Au等；栅电极8一般采用功函数较大的金属合金，例如Ni/Au或Ti/Au等。
图9、图10分别是本发明提出的双向极化增强型HEMT器件结构阻断耐压时的IV曲线图与正向导通时的转移特性曲线图。采用Sentaurus TCAD软件进行仿真，器件结构横向尺寸为7μm，栅漏距离为5μm的条件下，本发明所提出的结构的阈值电压为2.5V，击穿电压可达690V。

Claims (9)

1.一种增强型HEMT器件，包括衬底(1)、位于衬底(1)上层的缓冲层(2)和位于缓冲层(2)上层的势垒层(3)，所述缓冲层(2)与势垒层(3)的接触面形成具有二维电子气沟道的第一异质结；所述势垒层(3)上表面的一端具有与势垒层(3)形成欧姆接触的漏电极(5)；其特征在于，所述势垒层(3)上表面具有能与其产生反向极化的反极化半导体层(4)，所述反极化半导体层(4)与势垒层(3)的接触面形成具有二维空穴气的第二异质结；所述反极化半导体层(4)上表面远离漏电极(5)的一端具有源电极(6)，所述源电极(6)与反极化半导体层(4)的连接界面形成电子的势阱；所述漏电极(5)与反极化半导体层(4)之间具有空穴阻断区(9)；所述源电极(6)远离漏电极(5)的一侧具有凹槽，所述凹槽的底部位于缓冲层(2)中，所述凹槽的底部与侧壁具有绝缘栅介质(7)，所述绝缘栅介质(7)沿源电极(6)上表面向靠近漏电极(5)的方向延伸，所述绝缘栅介质(7)与覆盖在绝缘栅介质(7)上的金属栅电极(8)构成绝缘栅极结构。
2.根据权利要求1所述的一种增强型HEMT器件，其特征在于，所述空穴阻断区(9)为采用刻槽方式形成。
3.根据权利要求1所述的一种增强型HEMT器件，其特征在于，所述空穴阻断区(9)为采用离子注入方式形成。
4.根据权利要求1所述的一种增强型HEMT器件，其特征在于，所述反极化半导体层(4)采用阶梯掺杂或线性掺杂。
5.根据权利要求1所述的一种增强型HEMT器件，其特征在于，所述反极化半导体层(4)位于源电极(5)下方掺杂有N型半导体杂质。
6.根据权利要求1～5任意一项所述的一种增强型HEMT器件，其特征在于，所述源电极(6)与漏电极(5)之间的反极化半导体层(4)上表面具有介质钝化层(10)。
7.根据权利要求6所述的一种增强型HEMT器件，其特征在于，所述反极化半导体层(4)采用的材料为Si、SiC、GaN、AlN、AlGaN、InGaN、InAlN中的一种或几种的组合。
8.根据权利要求7所述的一种增强型HEMT器件，其特征在于，所述缓冲层(2)和势垒层(3)采用的材料为GaN、AlN、AlGaN、InGaN、InAlN中的一种或几种的组合。
9.根据权利要求8所述的一种增强型HEMT器件，其特征在于，所述衬底(1)采用的材料为蓝宝石、Si、SiC、AlN、GaN、AlGaN中的一种或几种的组合。
CN201510456018.7A 2015-07-29 2015-07-29 一种增强型hemt器件 Active CN105140270B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201510456018.7A CN105140270B (zh) 2015-07-29 2015-07-29 一种增强型hemt器件
US14/979,488 US9431527B1 (en) 2015-07-29 2015-12-27 Enhancement mode high electron mobility transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510456018.7A CN105140270B (zh) 2015-07-29 2015-07-29 一种增强型hemt器件

Publications (2)

Publication Number Publication Date
CN105140270A CN105140270A (zh) 2015-12-09
CN105140270B true CN105140270B (zh) 2018-01-09

Family

ID=54725560

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510456018.7A Active CN105140270B (zh) 2015-07-29 2015-07-29 一种增强型hemt器件

Country Status (2)

Country Link
US (1) US9431527B1 (zh)
CN (1) CN105140270B (zh)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITUB20155862A1 (it) * 2015-11-24 2017-05-24 St Microelectronics Srl Transistore di tipo normalmente spento con ridotta resistenza in stato acceso e relativo metodo di fabbricazione
CN105428314A (zh) * 2015-12-26 2016-03-23 中国电子科技集团公司第十三研究所 GaN基HEMT器件制备方法
CN106340535A (zh) * 2016-08-01 2017-01-18 苏州捷芯威半导体有限公司 一种半导体器件及其制造方法
JP6593294B2 (ja) * 2016-09-28 2019-10-23 トヨタ自動車株式会社 半導体装置
US11145648B2 (en) * 2017-03-31 2021-10-12 Intel Corporation Enhancement/depletion device pairs and methods of producing the same
CN107093628B (zh) * 2017-04-07 2019-12-06 电子科技大学 一种极化掺杂增强型hemt器件
CN107248531B (zh) * 2017-07-07 2019-10-08 西安电子科技大学 基于实时监控开栅结构参数的阈值电压可控型GaN基增强型器件的制备方法
DE102018133325B4 (de) 2017-12-27 2024-04-18 Denso Corporation Halbleitervorrichtung
CN109065442A (zh) * 2018-04-17 2018-12-21 江南大学 一种利用氟离子注入实现氮化镓中诱导形成2dhg的方法
CN108649070A (zh) * 2018-05-14 2018-10-12 电子科技大学 一种GaN异质结电导调制场效应管
US11195945B2 (en) 2019-09-03 2021-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Cap structure coupled to source to reduce saturation current in HEMT device
US10840343B1 (en) * 2019-11-01 2020-11-17 Chih-Jen Huang Semiconductor structure for wide bandgap normally off MOSFET
CN113257912B (zh) * 2020-02-12 2024-04-26 苏州晶界半导体有限公司 一种增强型氮化物场效应晶体管
CN112185959B (zh) * 2020-08-28 2024-03-29 西安电子科技大学 一种与GaN HEMT电力电子器件单片集成的CMOS反相器及制备方法
CN113178485A (zh) * 2020-10-22 2021-07-27 西南交通大学 一种P型槽栅结合极化层结构的GaN HEMT器件
CN112510088B (zh) * 2020-12-01 2023-08-29 晶能光电股份有限公司 沟槽栅增强型GaN基HEMT器件及其制备方法
CN112614778B (zh) * 2020-12-18 2024-06-04 江苏能华微电子科技发展有限公司 一种在GaN HEMT器件中形成多功能p-GaN电极的方法及器件
CN112909077B (zh) * 2021-02-07 2022-03-29 电子科技大学 一种双异质结极化增强的准纵向GaN HEMT器件
CN113594243A (zh) * 2021-07-21 2021-11-02 电子科技大学 一种渐变极化掺杂的增强型GaN纵向场效应晶体管
US20230031437A1 (en) * 2021-08-02 2023-02-02 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device and method for manufacturing the same
CN113628964B (zh) * 2021-08-04 2024-03-12 苏州英嘉通半导体有限公司 Ⅲ族氮化物增强型hemt器件及其制造方法
CN116230744A (zh) * 2021-12-02 2023-06-06 华润微电子（重庆）有限公司 AlGaN/GaN功率HEMT器件及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130159A (zh) * 2011-01-06 2011-07-20 西安电子科技大学 高电子迁移率晶体管
CN104167445A (zh) * 2014-08-29 2014-11-26 电子科技大学 具有埋栅结构的氮化镓基增强耗尽型异质结场效应晶体管

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7985986B2 (en) * 2008-07-31 2011-07-26 Cree, Inc. Normally-off semiconductor devices
JP5487749B2 (ja) * 2009-06-17 2014-05-07 富士通株式会社 半導体装置及びその製造方法
JP5678485B2 (ja) * 2009-08-03 2015-03-04 ソニー株式会社 半導体装置
US20150255547A1 (en) * 2012-03-29 2015-09-10 Agency For Science, Technology And Research III-Nitride High Electron Mobility Transistor Structures and Methods for Fabrication of Same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130159A (zh) * 2011-01-06 2011-07-20 西安电子科技大学 高电子迁移率晶体管
CN104167445A (zh) * 2014-08-29 2014-11-26 电子科技大学 具有埋栅结构的氮化镓基增强耗尽型异质结场效应晶体管

Also Published As

Publication number Publication date
US9431527B1 (en) 2016-08-30
CN105140270A (zh) 2015-12-09

Similar Documents

Publication Publication Date Title
CN105140270B (zh) 一种增强型hemt器件
CN105097911B (zh) 一种具有结型半导体层的hemt器件
US10304931B2 (en) Polarization-doped enhancement mode HEMT
CN106920844B (zh) 一种具有n型浮空埋层的resurf hemt器件
CN104201201B (zh) 一种用于GaN基HEMT器件的自适应偏置场板
CN105118859A (zh) 一种隧穿增强型hemt器件
CN104538440B (zh) 一种缓冲层荷电resurf hemt器件
CN105845724B (zh) 一种积累型垂直hemt器件
CN107482059B (zh) 一种GaN异质结纵向逆导场效应管
CN109920854A (zh) Mosfet器件
CN102856373B (zh) 高电子迁移率晶体管
CN104393040A (zh) 一种具有荷电介质的hemt器件
CN102881716A (zh) 一种场致隧穿增强型hemt器件
CN106057868A (zh) 一种纵向超结增强型mis hemt器件
CN103579326B (zh) 一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管
CN106298911A (zh) 一种双结型栅氮化镓异质结场效应管
CN108598163A (zh) 一种GaN异质结纵向功率器件
CN105140302A (zh) 电荷补偿耐压结构垂直氮化镓基异质结场效应管
CN114447102A (zh) 具有衬底上复合半导体层的氮化镓异质结场效应晶体管
CN110828565B (zh) 一种具有p型埋层的双沟道高耐压氮化镓场效应晶体管
CN104851915B (zh) 槽栅型化合物半导体功率vdmos器件及提高其击穿电压的方法
CN108878524A (zh) 一种氮化镓基高电子迁移率晶体管
CN112864243B (zh) 一种具有钝化层渐变氟离子终端的GaN HMET器件
CN107393954B (zh) 一种GaN异质结纵向场效应管
CN105304707A (zh) 一种增强型hemt器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant