CN103579326B - 一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管 - Google Patents
一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管 Download PDFInfo
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Abstract
本发明公开了一种晶体管,属于半导体器件领域,尤其是一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管。该晶体管包括衬底、氮化铝成核层、氮化镓沟道层、氮化铝插入层、铝镓氮势垒层、p型掺杂氮化镓、源极、漏极以及和p型掺杂氮化镓接触的栅极,其中源极和漏极与势垒层形成欧姆接触,栅极与p型掺杂氮化镓形成肖特基接触,其特征在于,它还包括一层位于氮化镓沟道层和氮化铝成核层之间的p‑AlxGayN/n‑AlxGayN/……/p‑AlxGayN/n‑AlxGayN复合缓冲层,简称pn结复合缓冲层,其中p‑AlxGayN代表p型掺杂铝镓氮,n‑AlxGayN代表n型掺杂铝镓氮,以抑制电子在缓冲层内的输运,降低器件缓冲层泄漏电流,提升器件击穿电压。
Description
所属技术领域
本发明涉及一种晶体管,属于半导体器件领域,尤其是一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管,可以有效降低器件的泄漏电流和提高器件的击穿电压。
背景技术
氮化镓(GaN)材料具有禁带宽度大、临界击穿电场高、电子饱和速度高、导热性能好、耐高温、抗辐射和良好的化学稳定性等优异特性,同时氮化镓材料与铝镓氮(AlGaN)等材料形成的高电子迁移率晶体管(HEMT)器件具有高浓度和高迁移率的二维电子气,因此特别适用于高压、大功率和高温应用,是电力电子应用最具潜力的晶体管之一。
但是对于普通GaN HEMT而言[M.j.Wang et al.,“Source Injection InducedOff-State Breakdown and Its Improvement by Enhanced Back Barrier withFluorine Ion Implantation in AlGaN/GaN HEMTs”,in IEDM Tech.Dig.,2008,pp.149-152.],具体结构为,它包括衬底,氮化镓成核层,氮化镓缓冲层,铝镓氮势垒层,栅极,源极,漏极,其中源极和漏极与势垒层形成欧姆接触,栅极与势垒层形成肖特基接触。当这种普通器件承受耐压时,从源极注入的电子可以经过氮化镓缓冲层到达漏极,形成漏电通道,过大的缓冲层泄漏电流会导致器件提前击穿,使器件的击穿电压远低于理论预期,限制了GaNHEMT的输出能力。
在本发明提出以前,为降低器件缓冲层泄漏电流,提高器件击穿电压,通常使用以下方法来实现高阻态缓冲层设计:
1、在GaN缓冲层中掺碳、铁、锌等杂质[O.Hilt et al.,“Normally-off High-Voltage p-GaN Gate GaN HFET with Carbon-Doped Buffer”,ISPSD,IEEE(2011)]。碳、铁、锌等杂质会在氮化镓材料内引入深能级电子陷阱,俘获从源极注入缓冲层内的电子,提高缓冲层电阻,从而降低缓冲层的泄漏电流,但是该技术对器件击穿电压提升有限,无法充分发挥氮化镓材料的耐压优势,同时碳、铁等杂质引入的深能级陷阱同样会导致诸如器件输出电流下降、电流崩塌效应和反应速度下降等缺点,影响器件稳定性。
2、使用AlGaN等背势垒缓冲层结构[EldadBahat-Treidel et al.,“AlGaN/GaN/AlGaN DH-HEMTs Breakdown Voltage Enhancement Using Multiple Grating FieldPlates(MGFPs),”IEEE Trans.Electron Devices,Vol.57,No.6,pp.1208-1216,June2010]。AlGaN等背势垒的使用增大了缓冲层势垒高度,使得沟道二维电子气越过缓冲层变得困难,从而降低了器件缓冲层泄漏电流,但是该技术同样对器件击穿电压提升有限,未能充分体现氮化镓材料的耐压优势,同时AlGaN背势垒不仅在缓冲层和沟道之间由于晶格失配引入陷阱,而且缓冲层中AlGaN和势垒层中AlGaN具有相反的极化效应,会降低沟道二维电子气浓度,增大器件导通电阻。
3、使用AlGaN/GaN或AlN/GaN等复合缓冲层结构[S.L.Selvaraj,et al.,″Breakdown Enhancement of AlGaN/GaN HEMTs on 4-in Silicon by Improving the GaNQuality on Thick Buffer Layers,″Electron Device Letters,IEEE,Vol.30,No.6,pp.587-589,June 2009]。AlGaN/GaN或AlN/GaN复合结构在缓冲层内引入超晶格能带结构,相比缓冲层掺入陷阱和铝镓氮背势垒结构,该结构可以进一步抑制电子在缓冲层内的输运,提升器件击穿电压,但由于AlGaN和AlN材料与GaN材料的晶格失配同样会破坏缓冲层的晶体结构,引入陷阱和极化电荷,降低器件性能。
4、在[Saba Rajabi,et al.,“A Novel Double Field-Plate Power HighElectron Mobility Transistor based on AIGaN/GaN for Performance Improvement”,ICSCCN(2011)]中,使用三层PNP GaN缓冲层结构,但该方法是基于电荷平衡原理,在缓冲层中掺入的P型杂质和N型杂质浓度相等,掺杂厚度相同,并且该方法在缓冲层中掺杂只是辅助耗尽沟道中的二维电子气,该方法提高击穿电压的主要措施是源漏端的两个场板。
发明内容
本发明的目的是为了抑制电子在缓冲层内的输运,降低器件泄漏电流,从而使器件具有更高的击穿电压,本发明提出了一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管。
本发明解决其技术问题所采用的技术方案是:一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管,包括衬底(108)、氮化铝成核层(107)、氮化镓沟道层(109)、氮化铝插入层(106)、铝镓氮势垒层(105)、p型掺杂氮化镓(104)、源极(101)、漏极(102)以及和p型掺杂氮化镓(104)接触的栅极(103);其中源极(101)和漏极(102)与铝镓氮势垒层(105)形成欧姆接触,栅极(103)与p型掺杂氮化镓(104)形成肖特基接触;其特征在于:它还包括一层位于氮化镓沟道层(109)和氮化铝成核层(107)之间的p-AlxGayN/n-AlxGayN/……/p-AlxGayN/n-AlxGayN复合缓冲层,简称pn结复合缓冲层(110),其中p-AlxGayN代表p型掺杂铝镓氮,n-AlxGayN代表n型掺杂铝镓氮。
其中,所述的pn结复合缓冲层(110)是纵向排列。
其中,所述的pn结复合缓冲层(110)按p-AlxGayN/n-AlxGayN/……/p-AlxGayN/n-AlxGayN重复生长直到达到复合缓冲层所需的厚度1000nm~8000nm。
其中,所述的pn结复合缓冲层(110)中p-AlxGayN单层掺杂厚度为1nm~100nm,n-AlxGayN单层掺杂厚度为1nm~100nm。
其中,所述的pn结复合缓冲层(110)每层p-AlxGayN掺杂浓度范围为1016cm-3~1019cm-3,每层n-AlxGayN掺杂浓度范围为1014cm-3~1018cm-3。
其中,所述的pn结复合缓冲层(110)中AlxGayN式中x+y=1且0≤x<0.5,0.5<y≤1。
与以上方法相比,本发明的主要优点是:
(1)在缓冲层内引入纵向pn结,当pn结耗尽以后,形成电子势阱,能阻挡电子向缓冲层内部渗透,降低缓冲层泄漏电流。
(2)通过调节pn结掺杂浓度,当p型掺杂浓度高于n型掺杂浓度时,n型区域完全耗尽,形成电子势阱,而未耗尽的p型区域还可以有减小表面电场(RESURF)作用。
(3)避免了使用AlGaN/GaN或者AlN/GaN等复合缓冲层由于应力引入所造成的缺陷和陷阱。
附图说明
图1是本发明结构示意图;
图2是pn结复合缓冲层导带结构示意图;
图3是pn结复合缓冲层垂直结构示意图;
图4为图3所示垂直结构电流电压特性对比图;
图5是本发明转移特性仿真对比图;
图6是本发明泄漏电流仿真对比图。
具体实施方式
下面结合附图和实施例对本发明进一步说明。
如图1,一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管,包括衬底(108)、氮化铝成核层(107)、氮化镓沟道层(109)、氮化铝插入层(106)、铝镓氮势垒层(105)、p型掺杂氮化镓(104)、源极(101)、漏极(102)以及和p型掺杂氮化镓(104)接触的栅极(103);其中源极(101)和漏极(102)与铝镓氮势垒层(105)形成欧姆接触,栅极(103)与p型掺杂氮化镓(104)形成肖特基接触;其特征在于:它还包括一层位于氮化镓沟道层(109)和氮化铝成核层(107)之间的p-AlxGayN/n-AlxGayN/……/p-AlxGayN/n-AlxGayN复合缓冲层,简称pn结复合缓冲层(110),其中p-AlxGayN代表p型掺杂铝镓氮,n-AlxGayN代表n型掺杂铝镓氮。
其中,所述的pn结复合缓冲层(110)是纵向排列。
其中,所述的pn结复合缓冲层(110)按p-AlxGayN/n-AlxGayN/……/p-AlxGayN/n-AlxGayN重复生长直到达到复合缓冲层所需的厚度1000nm~8000nm。
其中,所述的pn结复合缓冲层(110)中p-AlxGayN单层掺杂厚度为1nm~100nm,n-AlxGayN单层掺杂厚度为1nm~100nm。
其中,所述的pn结复合缓冲层(110)每层p-AlxGayN掺杂浓度范围为1016m-3~1019cm-3,每层n-AlxGayN掺杂浓度范围为1014cm-3~1018cm-3。
其中,所述的pn结复合缓冲层(110)中AlxGayN式中x+y=1且0≤x<0.5,0.5<y≤1。
在本发明中p-AlxGayN型掺杂厚度,n-AlxGayN型掺杂厚度和pn结复合缓冲层(110)总厚度可根据具体器件指标要求,通过理论计算,使用SENTAURUS、MEDICI等器件仿真软件确定,以使器件在截止状态下的缓冲层泄漏电流达到最小,最大地提升器件的耐压能力。
为验证pn结复合缓冲层(110)结构抑制缓冲层泄漏电流的效果,对pn结复合缓冲层(110)垂直器件结构的电流-电压特性进行了仿真分析,图3是pn结复合缓冲层(110)的垂直结构。使用pn结复合缓冲层(110)的垂直结构中,pn结复合缓冲层(110)总厚度为2000nm,p型掺杂厚度为80nm,掺杂浓度为3.0×1016cm-3,n型掺杂厚度为20nm,掺杂浓度为1×1016cm-3。
器件仿真结果如图4所示,采用本征氮化镓缓冲层(即没有在氮化镓缓冲层中进行pn结掺杂)的泄漏电流很大(实线);而本发明pn结复合缓冲层(110)则有效地抑制了泄漏电流,当n型掺杂浓度为1×1016cm-3,p型掺杂浓度为3.0×1016cm-3时,泄漏电流减小4个数量级(虚线),说明pn结复合缓冲层结构能有效抑制泄漏电流。
为进一步验证本发明中所述的pn结复合缓冲层(110)结构提高击穿电压的效果,对pn结复合缓冲层(110)的GaN HEMT进行了仿真。使用pn结复合缓冲层(110)的GaN HEMT的仿真中,氮化镓沟道层(109)厚度为30nm,pn结复合缓冲层(110)厚度为2000nm,pn结复合缓冲层(110)内p型单层掺杂厚度为80nm,掺杂浓度为2.8×1016cm-3,n型单层掺杂厚度为20nm,掺杂浓度为1×1016cm-3;采用本征氮化镓缓冲层时缓冲层厚度为2000nm,其他参数值相同,具体如下:
器件参数 | 参数值 |
栅长 | 1400nm |
栅漏间距 | 6000nm |
栅源间距 | 1500nm |
Si衬底厚度 | 100nm |
AlN成核层厚度 | 10nm |
AlN插入厚度 | 1nm |
AlGaN势垒层厚度 | 15nm |
p-GaN厚度 | 110nm |
p-GaN掺杂浓度 | 3×1017cm-3 |
沟道二维电子气浓度 | 5×1012cm-2 |
图5为器件转移特性,当Vds=15V,从器件转移特性比较可以看出,使用pn结复合缓冲层(110)结构的GaN HEMT具有更好的夹断特性(阈值电压使用线性外推法得到,此时pn结复合缓冲层(110)结构的GaN HEMT的阈值电压为1.08V,而之前的GaN HEMT的阈值电压为0.87V),说明pn结复合缓冲层(110)结构具有更好的二维电子气限域性和更小的缓冲层泄漏电流。
图6为截止状态下,使用pn结复合缓冲层(110)的GaN HEMT击穿电压比较,从图中可以看出,在截止状态下,使用pn结复合缓冲层(110)的GaN HEMT击穿电压(虚线)比之前使用的GaN HEMT(实线)的击穿电压有了很大的提高,从原来的73V上升到880V,说明pn结复合缓冲层(110)有效地抑制了电子在缓冲层内的输运,从而降低缓冲层泄漏电流,达到提高器件击穿电压的目的。
虽然上述实施例结合了两个器件作了说明,对于本领域的技术人员而言,在不违背本发明的基本内涵下,可以将本发明做一定的修改,但在此基础上所做的修改及改进都在本发明保护范围之内。
Claims (5)
1.一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管,包括衬底(108)、氮化铝成核层(107)、氮化镓沟道层(109)、氮化铝插入层(106)、铝镓氮势垒层(105)、P型掺杂氮化镓(104)、源极(101)、漏极(102)以及和P型掺杂氮化镓(104)接触的栅极(103);其中源极(101)和漏极(102)与铝镓氮势垒层(105)形成欧姆接触,栅极(103)与P型掺杂氮化镓(104)形成肖特基接触;其特征在于:它还包括一层位于氮化镓沟道层(109)和氮化铝成核层(107)之间的p-AlxGayN/n-AlxGayN/....../p-AlxGayN/n-AlxGayN复合缓冲层,简称pn结复合缓冲层(110),pn结复合缓冲层(110)是纵向排列,其中p-AlxGayN代表p型掺杂铝镓氮,n-AlxGayN代表n型掺杂铝镓氮。
2.根据权利要求1所述的一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管,其特征在于,所述的pn结复合缓冲层(110)按p-AlxGayN/n-AlxGayN/....../p-AlxGayN/n-AlxGayN重复生长直到达到复合缓冲层所需的厚度1000nm~8000nm。
3.根据权利要求1所述的一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管,其特征在于,所述的pn结复合缓冲层(110)中p-AlxGayN单层厚度为1nm~100nm,n-AlxGayN单层厚度为1nm~100nm。
4.根据权利要求1所述的一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管,其特征在于,所述的pn结复合缓冲层(110)中每层p-AlxGayN掺杂浓度范围为1016cm-3~1019cm-3,每层n-AlxGayN掺杂浓度范围为1014cm-3~1018cm-3。
5.根据权利要求1所述的一种具有纵向复合缓冲层的氮化镓基高电子迁移率晶体管,其特征在于,所述的pn结复合缓冲层(110)中AlxGayN式中x+y=1且0≤x<0.5,0.5<y≤1。
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