CN104900606A - 超薄嵌入半导体装置封装及其制造方法 - Google Patents

超薄嵌入半导体装置封装及其制造方法 Download PDF

Info

Publication number
CN104900606A
CN104900606A CN201510095674.9A CN201510095674A CN104900606A CN 104900606 A CN104900606 A CN 104900606A CN 201510095674 A CN201510095674 A CN 201510095674A CN 104900606 A CN104900606 A CN 104900606A
Authority
CN
China
Prior art keywords
encapsulating structure
semiconductor device
dielectric layer
external circuit
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510095674.9A
Other languages
English (en)
Other versions
CN104900606B (zh
Inventor
A.V.高达
P.A.麦康奈利
S.S.乔汉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of CN104900606A publication Critical patent/CN104900606A/zh
Application granted granted Critical
Publication of CN104900606B publication Critical patent/CN104900606B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/366—Assembling printed circuits with other printed circuits substantially perpendicularly to each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2401—Structure
    • H01L2224/2402—Laminated, e.g. MCM-L type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/271—Manufacture and pre-treatment of the layer connector preform
    • H01L2224/2711—Shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H01L2224/32501—Material at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/43—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8036—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/80365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1052—Wire or wire-like electrical connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/1033—Gallium nitride [GaN]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/207—Diameter ranges
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/302—Bending a rigid substrate; Breaking rigid substrates by bending
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/301—Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/306—Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

本发明涉及超薄嵌入半导体装置封装及其制造方法。一种封装结构，包括第一电介质层、附接到第一电介质层的(多个)半导体装置，以及施加到第一电介质层以便将半导体装置嵌入在其中的嵌入材料，该嵌入材料包括一个或多个附加电介质层。通孔通过第一电介质层形成到至少一个半导体装置，其中，金属互联件形成在通孔中以形成对半导体装置的电互联。输入/输出(I/O)连接部在封装结构的一端位于其一个或多个面朝外的表面上，以提供对外部电路的第二级连接。封装结构与在外部电路上的连接器互相配合以垂直于外部电路安装封装，其中，I/O连接部电连接到连接器以形成对外部电路的第二级连接。

Description

超薄嵌入半导体装置封装及其制造方法
技术领域
本发明的实施例大体涉及用于封装半导体装置的结构和方法，以及更特别地涉及超薄功率装置封装结构，其具有形成结构中的所有电互联和热互联的功率覆盖(POL)互联件，其中封装结构具有减少的电感。
背景技术
功率半导体装置是用作功率电子电路中的开关或整流器的半导体装置，诸如，例如开关式功率源。在使用中，功率半导体装置典型地借助于封装结构而表面安装对外部电路，其中，封装结构提供对外部电路的电连接，且还提供移除通过装置生成的热的方法以及保护装置免于外部环境的危害。备选地，尤其对于更高的功率范围，功率模块封装结构可具有用于对外部电路的连接的大终端，其增加显著的电感且增加模块的大小。
大多数现有的功率装置封装结构使用丝焊、多层基质(例如，直接结合铜(DBC)基质)，且有引线(引线框等)或设有螺栓终端，用于提供对封装结构的电和热连接。丝焊实现从封装结构的一个表面到封装插脚的连接，其然后接合对外部电路，其中DBC连接到封装结构的另一表面(例如，软焊到其)。然而，从材料角度以及从处理角度来说，认识到DBC都对封装结构增加了显著的成本，例如，当在封装结构中包括DBC时，要求额外的处理步骤以及温度偏移，诸如要求软焊以及助焊剂清洗过程以用于将DBC连接到封装结构。还认识到丝焊和引线增加了显著的附加电感，其降低了封装的效率。丝焊还对封装增加了显著的高度。还进一步认识到，虽然在封装结构上的引线允许更高的热循环可靠性，且不经受严厉的湿气敏感等级(MSL)要求，但是在功率模块中的引线或终端可非常大且影响在PCB上的模块占用面积和厚度，且还由于高电感而负面地影响电性能。
因此，将期望提供一种半导体装置封装结构，其消除了对于多层DBC或PCB基质以及丝焊连接的需要，以便提供带有超低电感的非常薄的封装结构。还将期望这种封装结构具有高装置密度以及小的占用面积，以便使系统能够小型化，以改进封装的电性能和可靠性性能。
发明内容
根据本发明的一个方面，一种封装结构包括第一电介质层、附接到第一电介质层的至少一个半导体装置，以及嵌入材料，其施加到第一电介质层以便将至少一个半导体装置嵌入其中，嵌入材料包括一个或多个附加电介质层。封装结构还包括：多个通孔，其形成在形成到至少一个半导体装置的第一电介质层中；金属互联件，其形成在多个通孔中以及在封装结构的一个或多个面朝外的表面上，以形成对至少一个半导体装置的电互联；以及输入/输出(I/O)连接部，其在封装结构的一端位于其一个或多个面朝外的表面上，以提供对外部电路的第二级连接。封装结构构造成与形成在外部电路上的连接器互相配合(interfit)，以垂直于外部电路安装封装，其中，在封装结构的一端的I/O连接部电连接到连接器以形成对外部电路的第二级连接。
根据本发明的另一方面，制造半导体装置封装结构的方法包括借助于粘结剂将至少一个半导体装置附接到第一电介质层，将嵌入材料施加在第一电介质层上以便围绕至少一个半导体装置定位，以及执行层压过程以导致嵌入材料填充围绕至少一个半导体装置存在的任意空气间隙，且以便将至少一个半导体装置嵌入在其中，其中，第一电介质层在层压过程期间不熔化或流动。方法还包括形成到至少一个半导体装置的多个通孔，在多个通孔中以及在封装结构的一个或多个外侧表面的一部分上方形成金属互联件，以形成对至少一个半导体装置的电互联，以及在封装结构的面朝外的表面中的一个或多个上、在封装结构的仅一端处形成输入/输出(I/O)连接部，I/O连接部包括提供对外部电路的第二级连接的电引线。
根据本发明的又一方面，一种封装结构包括：第一电介质层，具有施加在其至少一部分上的粘结剂；借助于粘结剂附接到第一电介质层的一个或多个半导体装置；嵌入材料，其围绕一个或多个半导体装置定位在第一电介质层上以便将一个或多个半导体装置嵌入在其中；形成到至少一个半导体装置的多个通孔；金属互联件，其形成在多个通孔中以形成对一个或多个半导体装置以及在封装结构中的所有电互联和热互联；以及输入/输出(I/O)连接部，其形成在封装结构的至少一个外侧表面上，以提供对外部电路的第二级连接，其中，I/O连接部构造成与形成在外部电路中的插口或凹部互相配合，使得在封装结构的I/O连接部互相配合在插口或凹部中时封装结构部分地嵌入在外部电路中。
方案1：一种封装结构，包括：
第一电介质层；
附接到第一电介质层的至少一个半导体装置；
嵌入材料，其施加到第一电介质层以便将至少一个半导体装置嵌入在其中，嵌入材料包括一个或多个附加的电介质层；
形成到至少一个半导体装置的多个通孔，多个通孔通过第一电介质层形成；
金属互联件，其形成在多个通孔中以及在封装结构的一个或多个面朝外的表面上，以形成对至少一个半导体装置的电互联；以及
输入/输出(I/O)连接部，其在封装结构的一端位于封装结构的一个或多个面朝外的表面上，以提供对外部电路的第二级连接；
其中，封装结构构造成与形成在外部电路上的连接器互相配合以垂直于外部电路安装封装结构，其中，在封装结构的一端的I/O连接部电连接到连接器以形成对外部电路的第二级连接。
方案2：根据方案1的封装结构，其中，I/O连接部包括构造成形成对外部电路的第二级连接的电引线。
方案3：根据方案2的封装结构，其中，金属互联件包括形成在封装结构的一个或多个面朝外的表面上的电连接的镀铜功率覆盖(POL)互联件，以及其中，POL互联件的一部分形成了形成I/O连接部的电引线。
方案4：根据方案1的封装结构，其中，金属互联件包括形成在封装结构的面朝外的表面的一个或多个上的传热铜垫的镀铜功率覆盖(POL)互联件，以便提供对至少一个半导体装置的热互联。
方案5：根据方案4的封装结构，其中，还包括：
施加到传热铜垫的热接合材料(TIM)；以及
安装到TIM以引导热远离封装结构的散热部。
方案6：根据方案5的封装结构，其中，散热部还联接到外部电路，以便当垂直于外部电路安装封装结构时提供支承。
方案7：根据方案1的封装结构，其中，I/O连接部形成在封装结构的两个面朝外的表面上，在封装结构的一端。
方案8：根据方案1的封装结构，其中，还包括定位在封装结构的面朝外的表面上与第一电介质层相对的第二电介质层，其中，至少一个半导体装置和嵌入材料定位在第一电介质层和第二电介质层之间。
方案9：根据方案8的封装结构，其中，还包括施加在第一和第二电介质层中的至少一个的面朝内的表面上的粘结剂层，以将至少一个半导体装置紧固到其，其中，多个通孔延伸通过粘结剂层。
方案10：根据方案9的封装结构，其中，至少一个半导体装置包括功率半导体装置；以及
其中，多个通孔包括：
    通过第一电介质层和粘结剂层形成到功率半导体装置的前表面的通孔；以及
    通过一个或多个第二电介质层和粘结剂层形成到功率半导体装置的后表面的通孔；
    其中，通孔用作在封装结构中的热通孔和电通孔；以及
其中，金属互联件在通孔的每一个中形成到功率半导体装置的前表面和后表面。
方案11：根据方案9的封装结构，其中，还包括金属层，其定位在第一电介质层或第二电介质层的面朝内的表面上，以增加在封装结构中的路径选择。
方案12：根据方案1的封装结构，其中，外部电路的连接器包括外部电路插口，封装结构插入到其内，以将I/O连接部机械和电联接到外部电路。
方案13：根据方案1的封装结构，其中，还包括在金属互联件上方形成在封装结构的面朝外的表面上的软焊掩模，其中，软焊掩模不形成在I/O连接部上方。
方案14：根据方案1的封装结构，其中，封装结构垂直于外部电路的安装相比其沿平坦定向的安装降低了封装结构在外部电路上的占用面积。
方案15：根据方案1的封装结构，其中，嵌入材料的一个或多个附加电介质层包括一个或多个电介质片材，其构造成当经受层压过程时熔化和流动以填充围绕至少一个半导体装置存在的任意空气间隙。
方案16：根据方案15的封装结构，其中，嵌入材料还包括热连接到多个通孔的带有铜的金属层或电介质片材，以传播和引导热到外界环境，其中，带有铜的金属层或电介质片材当经受层压过程时不熔化和流动。
方案17：根据方案1的封装结构，其中，还包括定位在封装结构的面朝外的表面上的至少一个附加金属电路层，至少一个附加金属电路层构造成增加在封装结构中的路径选择。
方案18：一种制造半导体装置封装结构的方法，包括：
借助于粘结剂将至少一个半导体装置附接到第一电介质层；
在第一电介质层上施加嵌入材料，以便围绕至少一个半导体装置定位；
执行层压过程，以导致嵌入材料填充围绕至少一个半导体装置存在的任意空气间隙且以便将至少一个半导体装置嵌入在其中，其中，第一电介质层在层压过程期间不熔化或流动；
形成到至少一个半导体装置的多个通孔；
在多个通孔中以及在封装结构的一个或多个外侧表面的至少一部分的上方形成金属互联件，金属互联件形成对至少一个半导体装置的电互联；以及
在封装结构的面朝外的表面中的一个或多个上在封装结构的仅一端处形成输入/输出(I/O)连接部，I/O连接部包括提供对外部电路的第二级连接的电引线。
方案19：根据方案18的方法，其中，还包括将封装结构安装在外部电路在I/O连接部处的对应插口或凹部内，其中，封装结构在边缘处安装在插口或凹部中，以便相对于外部电路沿垂直方向定位。
方案20：根据方案19的方法，其中，还包括在封装结构安装在外部电路的插口或凹部内后弯曲封装结构，使得封装结构的高度降低。
方案21：根据方案18的方法，其中，还包括：
在封装结构的面朝外的表面中的一个或多个上在金属互联件的一部分的上方施加热接合材料(TIM)；
在封装结构的面朝外的表面中的一个或多个上贴附散热部到TIM，以引导热远离封装结构；以及
将在封装结构的面朝外的表面中的一个或多个上的散热部联接到外部电路上，以便当将封装结构在边缘安装在插口或凹部中时提供支承。
方案22：根据方案18的方法，其中，还包括将第二电介质层定位在一个或多个电介质片材上方，使得至少一个半导体装置和嵌入材料定位在第一和第二电介质层之间，其中，多个通孔的一部分通过第二电介质层形成。
方案23：根据方案18的方法，其中，施加嵌入材料包括：
形成一个或多个电介质片材；以及
在第一电介质层上施加一个或多个电介质片材，以便围绕至少一个半导体装置定位；
其中，在层压过程期间一个或多个电介质片材熔化和流动，以填充围绕至少一个半导体装置存在的任意空气间隙，以便将至少一个半导体装置嵌入在其中。
方案24：一种封装结构，包括：
第一电介质层，其具有施加在其至少一部分上的粘结剂；
一个或多个半导体装置，其借助于粘结剂附接到第一电介质层；
嵌入材料，其围绕一个或多个半导体装置定位在第一电介质层上，以便将一个或多个半导体装置嵌入在其中；
形成到至少一个半导体装置的多个通孔；
金属互联件，其形成在多个通孔中以形成对一个或多个半导体装置以及在封装结构中的所有的电互联和热互联；以及
输入/输出(I/O)连接部，其形成在封装结构的至少一个外侧表面上，以提供对外部电路的第二级连接；
其中，I/O连接部构造成与形成在外部电路中的插口或凹部互相配合，使得当封装结构的I/O连接部在插口或凹部中互相配合时封装结构部分地嵌入在外部电路中。
方案25：根据方案24的封装结构，其中，I/O连接部形成在封装结构的相对边缘的每一个处，且构造成形成对外部电路的第二级连接，I/O连接部包括如下中的一个：
形成为大体平行于封装结构的定向的电引线；以及
形成为垂直于封装结构的定向的电引线，其中，电引线弯曲以从封装结构朝外延伸；以及
其中，电引线与形成在外部电路中的插口或凹部互相配合，使得封装结构相对于外部电路沿平坦或平行定向配置。
方案26：根据方案24的封装结构，其中，I/O连接部在封装结构的一端形成于其至少一个外侧表面上，以形成对外部电路的第二级连接，其中，在一端的I/O连接部与形成在外部电路中的插口或凹部互相配合，以垂直于外部电路安装封装。
从结合附图提供的本发明的优选实施例的以下详细描述中，这些和其他优势和特征将更容易理解。
附图说明
附图图示了目前考虑用于实施本发明的实施例。
在附图中：
图1是根据本发明的实施例，功率覆盖(POL)封装结构的示意性截面侧视图。
图2是根据本发明的实施例，POL封装结构的示意性截面侧视图。
图3是根据本发明的实施例，POL封装结构的示意性截面侧视图。
图4A和4B是形成在图1和2的POL封装结构的一端的输入/输出(I/O)连接部的前视图和后视图。
图5A和5B是根据本发明的实施例，插入/嵌入到印刷电路板(PCB)的连接器内的图1和2的POL封装结构的前视图和侧视图。
图6是根据本发明的实施例，插入/嵌入到印刷电路板(PCB)的连接器内的POL封装结构的侧视图。
图7是根据本发明的实施例，插入/嵌入到印刷电路板的连接器内的图1和2的POL封装结构的侧视图，其中，散热部贴附到封装结构和PCB。
图8是根据本发明的实施例，安装/嵌入在PCB中的POL封装结构的示意性截面侧视图。
图9是根据本发明的实施例，安装/嵌入在PCB中的POL封装结构的示意性截面侧视图。
具体实施方式
本发明的实施例提供用于具有功率覆盖(POL)互联件的嵌入功率模块封装结构，其形成到功率模块中的半导体装置的所有电互联和热互联，以及用于形成这种封装结构的方法。封装结构构造成具有沿两个轴线的“超薄”构造，且可部分地嵌入在封装结构安装到其的外部电路(例如，PCB)中。
参考图1，根据本发明的实施例示出POL封装和连接器结构10。封装结构10包括一个或多个半导体装置12、13，其可具有大体描述为“功率装置”或者“非功率装置”的物品的形式，且因此可具有例如模具、二极管、MOSFET、晶体管、特定应用集成电路(ASIC)或处理器的形式。虽然在图1中示出了三个功率半导体装置12和单个非功率半导体装置13(即，门驱动器)，但是可认识到在POL结构10中可包括更少或者更多数量的半导体装置或电子构件。半导体装置12、13封装在封装结构10内，使得直接金属互联件形成对装置的所有的电和/或热互联。
如在图1中所示，根据示例实施例，封装结构10包括在封装结构10的每一个相对侧部上的电介质层(其中，半导体装置12、13定位在其间)，其中，该层大体称为第一电介质层14和第二电介质层16。虽然封装结构10包括第一电介质层14和第二电介质层16两者，但是可认识到本发明的实施例可仅包括第一电介质层14。在图1中，电介质层14、16以层压件或薄膜的形式提供且由如下材料形成，即该材料选择成在使用和框架处理期间对通孔提供机械和温度稳定性，以及为通孔形成和POL处理提供合适的电介质特性和电压击穿强度以及加工性能，且因此电介质层14、16可称为“POL电介质。”另外，电介质层14、16由其形成的材料选择成在在封装结构10上执行的层压过程期间保持稳定。即，电介质层14、16由合适的材料形成，使得其构造成在在封装结构10上执行的层压过程期间不流动。因此，根据本发明的实施例，电介质层14、16可由多种电介质材料，诸如Kapton?、Ultem?、聚四氟乙烯(PTFE)、Upilex?、聚砜类材料(例如，Udel?、Radel?)中的一种，或者另一聚合体薄膜，诸如液晶聚合体(LCP)或聚酰亚胺材料形成。为了清楚以及将电介质层14、16与在封装结构10中的其他电介质材料区分的目的，电介质层14、16此后称为聚酰亚胺层14、16，虽然该术语不意味着限制层14、16由具体的电介质材料形成。
如在图1中所示，聚酰亚胺层14、16提供在封装结构10的两个侧部上，即，在封装结构的前表面和后表面18、20上，以便提供在两个表面上形成通孔以及模式化的金属互联件的能力，如将在下文中进一步描述的。半导体装置12、13定位在聚酰亚胺层14、16之间，其中，装置12、13借助于粘结剂22附接到聚酰亚胺层14、16。根据本发明的实施例，嵌入材料24(即，密封剂)包括在提供在聚酰亚胺层14、16之间的封装结构10中，其用于填充在封装结构10内的空的间隙，该空隙可围绕半导体装置12、13以及在聚酰亚胺层14、16之间存在，以及，根据一个实施例，可将聚酰亚胺层14“粘”到装置12、13，且可因此由一种或多种材料形成。
根据本发明的一个实施例，以及如在图1中所示，嵌入材料24由一个或多个电介质层26构成，其以“薄膜”或“面板”或“片材”的形式提供，使得如果需要的话，多个电介质片材26可堆叠在彼此上到填充围绕半导体装置12、13以及在聚酰亚胺层14、16之间的区域所要求的要求高度/厚度。电介质片材26从诸如例如预浸处理材料、印刷电路板核心材料、聚合物树脂或其他合适的粘结剂的电绝缘材料形成。根据一个实施例，电绝缘电介质片材26可以以或者固化或者部分固化的形式提供(即，B阶段)，使得其可容易地堆叠成其预固化薄膜形式。根据另一实施例，电绝缘电介质片材26可提供为固化和非固化片材两者，诸如固化核心材料的片材和可流动预浸处理材料的片材或者聚酰亚胺和可流动粘结剂(例如，层22)的片材的混合物。还可使用其他绝缘材料，诸如陶瓷或玻璃。根据本发明的一个实施例，(多个)电介质片材26包括形成在其中的开口/切口28，以在其中接收半导体装置12、13且调节在其附近的(多个)片材26的定位。备选地，认识到电介质片材26的节段可围绕半导体装置12、13放置。
虽然嵌入材料24如上文中所述由以“薄膜”或“面板”或“片材”形式提供的一种或多种电介质层26构成，但是应当认识到嵌入材料24可包括其他材料。例如，为嵌入材料24的电介质堆叠可由金属层或带有厚铜的电介质薄膜(例如，其当经受层压过程时不熔化和流动)构成。在这种实施例中，这些层可根据需要与装置12、13电分离，但是有益地可用作传热嵌入结构，其可与通孔连接以传播热以及引导到环境。这些带有金属化的嵌入层还可模式化以及互联，以提供针对附加的电路密度的附加路径选择层。
为了填充在封装结构10内的空的空隙，(多个)电介质片材26经受层压/固化过程(典型地在真空环境中，处于升高的温度以及在机械压力之下)，其导致(多个)电介质片材26中的全部或一些“熔化”以及流动。(多个)电介质片材26因此失去其薄膜形式且流动以填充围绕半导体装置12、13以及在聚酰亚胺层14、16之间的任意空的空气间隙，使得电介质密封剂24提供成大体保护半导体装置12、13免于环境危害，且提供机械完整度以及电隔离。
现在参考图2，示出封装结构10的备选实施例，其中，嵌入材料24仅由粘结剂22形成。即，在其中半导体装置12、13非常薄的情形中，可不要求电介质层26来压缩半导体装置。相反，粘结剂22涂覆在聚酰亚胺层14的表面上，超出其中半导体装置12、13所附接的区域，且在层压期间，该粘结剂22足以填充围绕半导体装置12、13在聚酰亚胺层14、16之间的间隙。虽然聚酰亚胺层14、16在图2中示出为彼此平行，但是应当认识到，不要求聚酰亚胺层14、16的这种配置，因为在两个聚酰亚胺层14、16之间的间隙可在其中模具不存在的区域中更小，以便产生其中聚酰亚胺层14、16不平行的配置。
在图1和2中所示的封装结构10的每个实施例中，多个通孔30通过聚酰亚胺层14向下形成到半导体装置12、13的前表面32。对于功率半导体装置12，通孔30可都形成到半导体装置12的前表面32(例如，如用于GaN功率装置)，或可替代地形成到半导体装置12的前表面和后表面34两者，以满足电和热要求(例如，以制造所需的电连接，以及从功率半导体装置移除热)。金属互联件38随后形成在封装结构10中，以提供在其中的电和热连接/路径，其中，互联件38形成在通孔30中以及出来分别到聚酰亚胺层14、16的面朝外的前后表面18、20上，使得封装结构10的两个前和后表面18、20包括形成在其上的互联件。根据本发明的实施例，金属互联件38包括“POL互联件”，其形成为强健的电镀铜互联件，其在装置12、13中形成直接的电连接。取决于在装置上的金属化，在一些实施例中，溅射粘附层(钛、铬等)连同铜可镀在其上的溅射铜晶种层一起提供。如在图1和2中所示，金属互联件38模式化以及蚀刻成期望的形状，诸如以提供用于到封装结构10的电和热连接。根据一个实施例，金属互联件38模式化以及蚀刻以提供在封装结构10(即，铜垫)的前侧和/或后侧上的大区域热和电连接，其能够实现封装结构到散热部的附接，例如，如将在下文中进一步更详细解释地。
虽然图1和2的封装结构10示出为仅包括具有在其中形成的金属互联件38的电介质层14、16，应当认识到可执行封装的进一步构建。即，如在图3中所示，一个或多个附加金属电路层39(即，电介质层和模式化金属连接器)可施加到封装结构的前和后表面18、20中的每一个中，以增加在封装结构10中的路径选择。
根据另一实施例，相比对封装结构10(如在图3中所示)增加附加的金属电路层，可通过在电介质层14、16的朝内的侧部上(即，在装置12、13的侧部上)增加金属层(未示出)而在封装结构中增加路径选择。在这种实施例中，金属层可因此存在于每一个电介质层14、16的两个侧部上。
现在参考图1-3，根据本发明的实施例，电输入/输出连接部(I/O)40提供在封装结构10上，其用作“电引线”，其将封装结构10电连接至外部电路，诸如印刷电路板(PCB)，即，利用I/O连接部40以形成对外部电路的次级互连。I/O连接部40可形成为铜垫或镀铜轨迹，例如，其形成在封装结构的前和/或后表面18、20上。I/O连接部建立处于系统级的完全的电功能，使得在POL封装结构10中不需要附加/分离的引线、终端或引线框架，从而得到带有显著改进的电和机械性能的超薄、小型化的电封装。
根据本发明的示例实施例，提供对PCB的次级互连的I/O连接部40都位于封装结构的一端42上、在前和后表面18、20中的一个或两个处。I/O连接部40形成处的端42的详细视图在图4A和4B中的示出，其图示了在端42处的封装结构10的前和后表面18、20。如在图4A和4B中所示，形成I/O连接部40的引线44(在电介质层14、16上)的铜垫和/或镀铜轨迹在封装结构10的端42处形成。根据一个实施例，以及如在图1和2中最佳地可见，软焊掩模46可施加在前和/或后表面18、20的剩余部上方，即，在模式化的POL互联件38的上方，已提供对其铜的保护覆层，而留下在端42上的I/O连接部40无覆盖。另外，认识到焊接剂表面处理或其他金属表面处理(未示出)可施加在模式化的POL互联件38的暴露区域上(余下的通过软焊掩模暴露)或者模式化POL互联件38的整个表面。
通过在端42上提供全部封装结构10的I/O连接部40，封装结构10构造成在边缘连接到PCB。封装结构10与PCB 48的这种配置经由在图5A和5B中的前和侧视图示出，其中，封装结构10的端42插入在PCB 48上的连接器或插口50内，使得I/O连接部40形成与连接器50的直接电连接。封装结构10在边缘上相对于PCB 48沿垂直定向(即，垂直)的安装最小化封装结构10的占用面积且因此节省板面积，虽然其不用于增加PCB组件的高度。然而，根据本发明的一个实施例，封装结构10的高度可通过在插入到插口50内之后弯曲而减少，如在图6中所示。在弯曲后，封装结构10的一部分/大部分平行于PCB 48，其中，一个实施例构造成使得封装结构包括模具/半导体装置的部分平行于PCB。
现在参考图7，根据本发明的一个实施例，一个或多个散热部52在前和/或后表面18、20上联接到封装结构10，以帮助热移除且促进封装结构的热管理。虽然图7示出两个散热部52贴附到封装结构10，但是认识到仅单个散热部52可附接到封装结构，诸如到其后侧20。散热部52可诸如通过增加(多种)热接合材料(TIM)54到结构的后侧20(和/或前侧18)而联接到封装结构10。即，具有导热系数的TIM 54的层施加到POL结构10上且在POL互联件38(以及软焊掩模46)上方，以提供对散热部52的结合以及能量的热传递。合适的TIM的示例包括但不限于粘结剂、油脂、凝胶、衬垫、薄膜、液体金属、可压缩金属以及相变材料。液体金属TIM例如是典型地铟-镓合金，其在功率电子应用中遇到的典型温度以上处于液态。可压缩金属充分柔软以实现在散热部和POL匹配表面之间的亲密接触，以及可包括例如铟。
散热部52除了提升从封装结构10的热移除之外，散热部52还在其到PCB 48的边缘安装中提供对封装结构的机械支承。即，除了贴附到封装结构10(经由TIM 54)之外，散热部52还联接到PCB 48，使得其提供用于封装结构10的支撑。取决于一个或两个散热部52是否附接到封装结构10，散热部52可因此在其一个或两个侧部上提供附加结构支承到封装结构10，以帮助将封装结构10相对于PCB 48维持在其垂直方向中。
现在参考图8和9，根据本发明的附加实施例示出封装结构60、62，其中，封装结构构造成部分地嵌入封装结构安装到其的外部电路(例如，PCB)，其中，封装结构沿两个轴线具有“超薄”构造。关于将半导体装置嵌入在电介质层之间的嵌入材料中以及POL互联件的使用而言，在图8和9中示出的封装结构60、62具有与在图1和2中所示的封装结构10类似的构造，且因此在图8和9的封装结构60、62中与图1和2的封装结构10中的对应构件相同的构件类似的标识。
如在图8和9中所示，封装结构60、62中的每一个示出为包括定位在第一电介质层14和第二电介质层16(即，聚酰亚胺层)之间的半导体装置12、13，其中，装置12、13借助于粘结剂22附接到聚酰亚胺层14、16且通过从一种或多种电介质层26形成的嵌入材料密封。(多个)电介质层以可堆叠在彼此上以填充半导体装置12、13附近以及在聚酰亚胺层14、16之间的区域所要求的要求高度/厚度的“薄膜”或“面板”或“片材”的形式提供，其中，电介质片材26当经受层压/固化过程时引起熔化和流动，使得(多个)电介质片材26因此失去其薄膜形式且流动以填充围绕半导体装置12、13以及在聚酰亚胺层14、16之间的任意空的空气间隙。
在封装结构60、62中，多个通孔30通过聚酰亚胺层14向下形成到半导体装置12、13的前表面32。对于功率半导体装置12，通孔30还形成到半导体装置12的后表面34以满足电以及热要求。金属互联件38随后形成在封装结构10中，以提供在其中的电和热连接/路径，其中，互联件38形成在通孔30中以及出来分别到聚酰亚胺层14、16的面朝外的前和后表面18、20上，使得封装结构10的前和后表面18、20两者包括形成在其上的互联件。根据本发明的实施例，金属互联件38包括“POL互联件”，其形成为强健的电镀铜互联件，其在装置12、13中形成直接的电连接。金属互联件38模式化以及蚀刻到期望的形状，诸如提供用于到封装结构10的电和热连接。
参考图8，电输入/输出连接部(I/O)64在封装结构10上在结构的大体相对端66的每一个处提供，其用作将封装结构10电连接至外部电路48，诸如印刷电路板(PCB)的“电引线”。根据实施例，以及如在图8中所示，I/O连接部64形成在封装结构10的前表面18上。通孔68因此通过金属化的聚酰亚胺层14、16和(多个)电介质片材26(即，金属互联件38形成在通孔中/通过通孔68)以将电连接从后表面20重新分配到前表面18。虽然I/O连接部64示出为仅形成在封装结构10的前表面18上，但是认识到I/O连接部64可相反形成在封装的两个表面上，即，在前和后表面18、20上，其通孔68在这种实施例中不存在。
如在图8中所示，形成在封装结构10的前表面18上的I/O连接部64包括引线70，其中，引线70形成为铜垫或镀铜轨迹，例如，其大体平行于封装结构的表面18定向，且其用于形成对PCB 48的次级互连。软焊掩模46可施加在前表面18的剩余部上方，即，在模式化POL互联件38上方，以提供用于其铜的保护覆层，而留下在前表面18上的I/O连接部64的引线70无覆盖物。另外，认识到焊接剂表面处理或其他金属表面处理(未示出)可施加在模式化的POL互联件38的暴露区域上(余下的通过软焊掩模暴露)或者模式化POL互联件38的整个表面。如在图8中所示，封装结构60相对于PCB 48沿“平坦”或平行定向配置且经由封装结构到PCB 48的凹部52内的定位部分地嵌入到PCB 48内，其中，焊接剂72施加在引线70的位置处，以便建立在系统级上的完全电功能。以这种方式，在POL封装结构10中不需要附加/分离的引线、终端或引线框架，从而得到带有显著改进的电和机械性能的超薄、小型电封装。当封装结构60部分地嵌入到PCB 48内时，与其中封装结构安装到没有用于接收封装结构的凹部的大体平坦的PCB组件相比，PCB组件的高度减少。
现在参考图9，封装结构62包括形成在封装结构10的前表面18上的I/O连接部64，其包括引线74，其从前表面18垂直延伸出来，以便提供用于封装结构62的连接构造。即，在前表面18上的I/O连接部64的引线74并不如在图8的实施例中那样构造成平坦的铜垫/轨迹，而是I/O连接部64的引线74形成为铜线或轨迹(单独的或包括聚酰亚胺材料，即聚酰亚胺14)，其弯曲以便从封装结构62的前表面18垂直朝外延伸。如在图9中所示，I/O连接部64的弯曲引线74构造成插入/嵌入在形成在PCB中48中或其上的狭槽或插口76内。引线74可然后经由烧结、软焊或机械连接(例如，按压配合)紧固在狭槽/插口76中，以便建立在系统上(即，到PCB的次级互连)的完全的电功能。
有利地，本发明的实施例因此提供具有沿两个轴线的“超薄”构造的封装结构，其中，该构造使得封装结构能够部分地嵌入在封装结构安装到其的外部电路(例如，PCB)中。在封装结构10中使用POL互联件和I/O连接部消除了对于丝线结合和/或附加的多层基质(例如，DBC基质等)的需要，其可典型地用于电和热功能，因此通过提供小的电感回线和磁通相抵以及消除可增加电感的丝焊和/或较大引线/终端而提供具有超低电感的封装。在将功率装置封装在封装结构10中时丝线结合以及多层基质的这种消除还使得封装结构10能够具有非常小的形式因子，带有高装置密度以及小的占用面积，以便使得系统能够小型化以改进封装的电和可靠性性能。封装结构的I/O连接部允许封装结构部分地嵌入在外部电路中，其中本发明的实施例提供用于将封装结构在边缘/相对于PCB垂直(以便降低封装结构的板占用面积)或者在PCB的凹部内平坦地安装在PCB的连接器或凹部中(以降低PCB组件的全部高度)。
因此,根据本发明的一个实施例，一种封装结构包括第一电介质层、附接到第一电介质层的至少一个半导体装置，以及嵌入材料，其施加到第一电介质层以便将至少一个半导体装置嵌入其中，嵌入材料包括一个或多个附加电介质层。封装结构还包括多个通孔，其形成在形成到至少一个半导体装置的第一电介质层中、形成在多个通孔中以及在封装结构的一个或多个面朝外的表面上的金属互联件，以形成对至少一个半导体装置的电互联，以及输入/输出(I/O)连接部，其在封装结构的一端位于其一个或多个面朝外的表面上，以提供对外部电路的第二级连接。封装结构构造成与形成在外部电路上的连接器互相配合，以垂直于外部电路安装封装，其中，在封装结构的一端的I/O连接部电连接到连接器以形成对外部电路的第二级连接。
根据本发明的另一实施例，制造半导体装置封装结构的方法包括借助于粘结剂将至少一个半导体装置附接到第一电介质层，将嵌入材料施加在第一电介质层上以便围绕至少一个半导体装置定位，以及执行层压过程以导致嵌入材料填充围绕至少一个半导体装置存在的任意空气间隙，且以便将至少一个半导体装置嵌入在其中，其中，第一电介质层在层压过程期间不熔化或流动。方法还包括形成到至少一个半导体装置的多个通孔，在多个通孔中以及在封装结构的一个或多个外侧表面的一部分上方形成金属互联件，以形成对至少一个半导体装置的电互联，以及在封装结构的面朝外的表面中的一个或多个上、在封装结构的仅一端处形成输入/输出(I/O)连接部，I/O连接部包括提供对外部电路的第二级连接的电引线。
根据本发明的又一实施例，一种封装结构包括：第一电介质层，具有施加在其至少一部分上的粘结剂；借助于粘结剂附接到第一电介质层的一个或多个半导体装置；嵌入材料，其围绕一个或多个半导体装置定位在第一电介质层上以便将一个或多个半导体装置嵌入在其中；形成到至少一个半导体装置的多个通孔；金属互联件，其形成在多个通孔中以形成对一个或多个半导体装置以及在封装结构中的所有电互联和热互联；以及输入/输出(I/O)连接部，其形成在封装结构的至少一个外侧表面上，以提供对外部电路的第二级连接，其中，I/O连接部构造成与形成在外部电路中的插口或凹部互相配合，使得在封装结构的I/O连接部互相配合在插口或凹部中时封装结构部分地嵌入在外部电路中。
虽然已经结合仅有限数量的实施例详细描述了本发明，但是应当容易理解本发明不受限于这种公开的实施例。而是，本发明可修改以合并任意数量的先前没有描述但是与本发明的精神和范围相称的变型、备选项、替代物或等价配置。另外，虽然已经描述了本发明的各种实施例，但是应当理解本发明的方面可包括所述实施例中的仅仅一些。因此，本发明不视为由前述描述限制，而是仅由所附权利要求的范围限制。

Claims (10)

1. 一种封装结构，包括：
第一电介质层；
附接到所述第一电介质层的至少一个半导体装置；
嵌入材料，其施加到所述第一电介质层以便将所述至少一个半导体装置嵌入在其中，所述嵌入材料包括一个或多个附加的电介质层；
形成到所述至少一个半导体装置的多个通孔，所述多个通孔通过所述第一电介质层形成；
金属互联件，其形成在所述多个通孔中以及在所述封装结构的一个或多个面朝外的表面上，以形成对所述至少一个半导体装置的电互联；以及
输入/输出(I/O)连接部，其在所述封装结构的一端位于所述封装结构的一个或多个面朝外的表面上，以提供对外部电路的第二级连接；
其中，所述封装结构构造成与形成在所述外部电路上的连接器互相配合以垂直于所述外部电路安装所述封装结构，其中，在所述封装结构的一端的所述I/O连接部电连接到所述连接器以形成对所述外部电路的所述第二级连接。
2. 根据权利要求1所述的封装结构，其特征在于，所述I/O连接部包括构造成形成对所述外部电路的第二级连接的电引线。
3. 根据权利要求2所述的封装结构，其特征在于，所述金属互联件包括形成在所述封装结构的一个或多个面朝外的表面上的电连接的镀铜功率覆盖(POL)互联件，以及其中，所述POL互联件的一部分形成了形成所述I/O连接部的电引线。
4. 根据权利要求1所述的封装结构，其特征在于，所述金属互联件包括形成在所述封装结构的面朝外的表面的一个或多个上的传热铜垫的镀铜功率覆盖(POL)互联件，以便提供对所述至少一个半导体装置的热互联。
5. 根据权利要求4所述的封装结构，其特征在于，还包括：
施加到所述传热铜垫的热接合材料(TIM)；以及
安装到所述TIM以引导热远离所述封装结构的散热部。
6. 根据权利要求5所述的封装结构，其特征在于，所述散热部还联接到所述外部电路，以便当垂直于所述外部电路安装所述封装结构时提供支承。
7. 根据权利要求1所述的封装结构，其特征在于，所述I/O连接部形成在所述封装结构的两个面朝外的表面上，在所述封装结构的一端。
8. 根据权利要求1所述的封装结构，其特征在于，还包括定位在所述封装结构的面朝外的表面上与所述第一电介质层相对的第二电介质层，其中，所述至少一个半导体装置和所述嵌入材料定位在所述第一电介质层和所述第二电介质层之间。
9. 根据权利要求8所述的封装结构，其特征在于，还包括施加在所述第一和第二电介质层中的至少一个的面朝内的表面上的粘结剂层，以将所述至少一个半导体装置紧固到其，其中，所述多个通孔延伸通过所述粘结剂层。
10. 根据权利要求9所述的封装结构，其特征在于，所述至少一个半导体装置包括功率半导体装置；以及
其中，所述多个通孔包括：
    通过所述第一电介质层和所述粘结剂层形成到所述功率半导体装置的前表面的通孔；以及
    通过所述一个或多个第二电介质层和所述粘结剂层形成到所述功率半导体装置的后表面的通孔；
    其中，所述通孔用作在所述封装结构中的热通孔和电通孔；以及
其中，金属互联件在所述通孔的每一个中形成到所述功率半导体装置的前表面和后表面。
CN201510095674.9A 2014-03-04 2015-03-04 超薄嵌入半导体装置封装及其制造方法 Active CN104900606B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/195,930 US9806051B2 (en) 2014-03-04 2014-03-04 Ultra-thin embedded semiconductor device package and method of manufacturing thereof
US14/195930 2014-03-04

Publications (2)

Publication Number Publication Date
CN104900606A true CN104900606A (zh) 2015-09-09
CN104900606B CN104900606B (zh) 2019-10-22

Family

ID=52595211

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510095674.9A Active CN104900606B (zh) 2014-03-04 2015-03-04 超薄嵌入半导体装置封装及其制造方法

Country Status (5)

Country Link
US (3) US9806051B2 (zh)
EP (1) EP2916354A3 (zh)
JP (1) JP6496571B2 (zh)
KR (1) KR102332362B1 (zh)
CN (1) CN104900606B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108573880A (zh) * 2017-03-14 2018-09-25 英飞凌科技奥地利有限公司 管芯嵌入
CN110062982A (zh) * 2016-12-22 2019-07-26 京瓷株式会社 天线基板及其制造方法
CN110534435A (zh) * 2019-08-01 2019-12-03 广东佛智芯微电子技术研究有限公司 三维多芯片异质集成的扇出型封装结构的封装方法

Families Citing this family (165)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US11984445B2 (en) 2009-10-12 2024-05-14 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11984438B2 (en) 2010-10-13 2024-05-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US9786636B2 (en) * 2012-12-22 2017-10-10 Monolithic 3D Inc. Semiconductor device and structure
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US9357670B2 (en) * 2014-02-18 2016-05-31 Lockheed Martin Corporation Efficient heat transfer from conduction-cooled circuit cards
US9806051B2 (en) * 2014-03-04 2017-10-31 General Electric Company Ultra-thin embedded semiconductor device package and method of manufacturing thereof
US9681558B2 (en) * 2014-08-12 2017-06-13 Infineon Technologies Ag Module with integrated power electronic circuitry and logic circuitry
US9666730B2 (en) * 2014-08-18 2017-05-30 Optiz, Inc. Wire bond sensor package
US9613843B2 (en) 2014-10-13 2017-04-04 General Electric Company Power overlay structure having wirebonds and method of manufacturing same
US10211158B2 (en) 2014-10-31 2019-02-19 Infineon Technologies Ag Power semiconductor module having a direct copper bonded substrate and an integrated passive component, and an integrated power module
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
WO2017053329A1 (en) 2015-09-21 2017-03-30 Monolithic 3D Inc 3d semiconductor device and structure
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US12016181B2 (en) 2015-10-24 2024-06-18 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US11991884B1 (en) 2015-10-24 2024-05-21 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
TWI622937B (zh) * 2016-06-22 2018-05-01 致伸科技股份有限公司 電容式指紋辨識模組
US10660208B2 (en) 2016-07-13 2020-05-19 General Electric Company Embedded dry film battery module and method of manufacturing thereof
US10044390B2 (en) 2016-07-21 2018-08-07 Qualcomm Incorporated Glass substrate including passive-on-glass device and semiconductor die
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US10541153B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
JP2020013877A (ja) * 2018-07-18 2020-01-23 太陽誘電株式会社 半導体モジュール
US10957832B2 (en) 2018-10-22 2021-03-23 General Electric Company Electronics package for light emitting semiconductor devices and method of manufacturing thereof
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US11164804B2 (en) 2019-07-23 2021-11-02 International Business Machines Corporation Integrated circuit (IC) device package lid attach utilizing nano particle metallic paste
US11469164B2 (en) 2020-01-16 2022-10-11 Infineon Technologies Ag Space efficient and low parasitic half bridge
US11398445B2 (en) 2020-05-29 2022-07-26 General Electric Company Mechanical punched via formation in electronics package and electronics package formed thereby
CN112349690B (zh) * 2020-09-28 2023-06-16 中国电子科技集团公司第二十九研究所 一种六层布线任意层互联lcp封装基板、制造方法及多芯片系统级封装结构
EP3982404A1 (en) 2020-10-07 2022-04-13 Infineon Technologies Austria AG Semiconductor module
TWI822634B (zh) * 2022-07-20 2023-11-11 強茂股份有限公司 晶圓級晶片尺寸封裝方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066898A (ja) * 1983-09-24 1985-04-17 アンリツ株式会社 混成集積回路素子の実装構造
CN101244800A (zh) * 2007-02-13 2008-08-20 通用电气公司 功率覆盖结构及其制作方法
US20110069448A1 (en) * 2008-05-30 2011-03-24 Weichslberger Guenther Method for integrating at least one electronic component into a printed circuit board, and printed circuit board
US8040682B2 (en) * 2005-10-14 2011-10-18 Kabushiki Kaisha Toshiba Semiconductor device
US20130009325A1 (en) * 2010-03-18 2013-01-10 Nec Corporation Semiconductor element-embedded substrate, and method of manufacturing the substrate

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8322473D0 (en) * 1983-08-20 1983-09-21 Int Computers Ltd Printed circuit boards
FR2572849B1 (fr) 1984-11-06 1987-06-19 Thomson Csf Module monolithique haute densite comportant des composants electroniques interconnectes et son procede de fabrication
FR2599893B1 (fr) 1986-05-23 1996-08-02 Ricoh Kk Procede de montage d'un module electronique sur un substrat et carte a circuit integre
US5731633A (en) * 1992-09-16 1998-03-24 Gary W. Hamilton Thin multichip module
US5543657A (en) * 1994-10-07 1996-08-06 International Business Machines Corporation Single layer leadframe design with groundplane capability
US5644103A (en) * 1994-11-10 1997-07-01 Vlt Corporation Packaging electrical components having a scallop formed in an edge of a circuit board
JPH08330698A (ja) * 1995-05-31 1996-12-13 Sanyo Electric Co Ltd 混成集積回路装置
US5567657A (en) 1995-12-04 1996-10-22 General Electric Company Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
US6232151B1 (en) * 1999-11-01 2001-05-15 General Electric Company Power electronic module packaging
US6544103B1 (en) * 2000-11-28 2003-04-08 Speedfam-Ipec Corporation Method to determine optimum geometry of a multizone carrier
JP2002290087A (ja) * 2001-03-28 2002-10-04 Densei Lambda Kk オンボード実装型電子機器およびオンボード実装型電源装置
US6734371B2 (en) * 2001-09-28 2004-05-11 Intel Corporation Soldered heat sink anchor and method of use
US6930385B2 (en) 2002-12-20 2005-08-16 Ut-Battelle, Llc Cascaded die mountings with spring-loaded contact-bond options
US8704359B2 (en) * 2003-04-01 2014-04-22 Ge Embedded Electronics Oy Method for manufacturing an electronic module and an electronic module
US6979891B2 (en) * 2003-09-08 2005-12-27 Intel Corporation Integrated circuit packaging architecture
FI117814B (fi) * 2004-06-15 2007-02-28 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi
FI122128B (fi) * 2005-06-16 2011-08-31 Imbera Electronics Oy Menetelmä piirilevyrakenteen valmistamiseksi
US8101868B2 (en) * 2005-10-14 2012-01-24 Ibiden Co., Ltd. Multilayered printed circuit board and method for manufacturing the same
US7839642B2 (en) * 2008-04-04 2010-11-23 Liebert Corporation Heat-sink brace for fault-force support
US8358000B2 (en) 2009-03-13 2013-01-22 General Electric Company Double side cooled power module with power overlay
JP2011210916A (ja) * 2010-03-30 2011-10-20 Mitsumi Electric Co Ltd 半導体装置の製造方法
JP2011222555A (ja) * 2010-04-02 2011-11-04 Denso Corp 半導体チップ内蔵配線基板の製造方法
US8531027B2 (en) 2010-04-30 2013-09-10 General Electric Company Press-pack module with power overlay interconnection
US8310040B2 (en) 2010-12-08 2012-11-13 General Electric Company Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof
US8114712B1 (en) 2010-12-22 2012-02-14 General Electric Company Method for fabricating a semiconductor device package
EP2538761B1 (en) 2011-06-20 2014-01-29 STMicroelectronics Srl Intelligent Power Module and related assembling method
US8653635B2 (en) * 2011-08-16 2014-02-18 General Electric Company Power overlay structure with leadframe connections
CN103137613B (zh) 2011-11-29 2017-07-14 华进半导体封装先导技术研发中心有限公司 制备有源芯片封装基板的方法
US8658473B2 (en) * 2012-03-27 2014-02-25 General Electric Company Ultrathin buried die module and method of manufacturing thereof
US8907467B2 (en) * 2012-03-28 2014-12-09 Infineon Technologies Ag PCB based RF-power package window frame
US9806051B2 (en) * 2014-03-04 2017-10-31 General Electric Company Ultra-thin embedded semiconductor device package and method of manufacturing thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6066898A (ja) * 1983-09-24 1985-04-17 アンリツ株式会社 混成集積回路素子の実装構造
US8040682B2 (en) * 2005-10-14 2011-10-18 Kabushiki Kaisha Toshiba Semiconductor device
CN101244800A (zh) * 2007-02-13 2008-08-20 通用电气公司 功率覆盖结构及其制作方法
US20110069448A1 (en) * 2008-05-30 2011-03-24 Weichslberger Guenther Method for integrating at least one electronic component into a printed circuit board, and printed circuit board
US20130009325A1 (en) * 2010-03-18 2013-01-10 Nec Corporation Semiconductor element-embedded substrate, and method of manufacturing the substrate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110062982A (zh) * 2016-12-22 2019-07-26 京瓷株式会社 天线基板及其制造方法
CN110062982B (zh) * 2016-12-22 2020-12-11 京瓷株式会社 天线基板及其制造方法
CN108573880A (zh) * 2017-03-14 2018-09-25 英飞凌科技奥地利有限公司 管芯嵌入
CN108573880B (zh) * 2017-03-14 2022-04-15 英飞凌科技奥地利有限公司 管芯嵌入
CN110534435A (zh) * 2019-08-01 2019-12-03 广东佛智芯微电子技术研究有限公司 三维多芯片异质集成的扇出型封装结构的封装方法

Also Published As

Publication number Publication date
US11605609B2 (en) 2023-03-14
US20150255418A1 (en) 2015-09-10
US9806051B2 (en) 2017-10-31
EP2916354A2 (en) 2015-09-09
US10607957B2 (en) 2020-03-31
EP2916354A3 (en) 2016-06-22
KR102332362B1 (ko) 2021-12-01
US20180033762A1 (en) 2018-02-01
KR20150104033A (ko) 2015-09-14
JP6496571B2 (ja) 2019-04-03
CN104900606B (zh) 2019-10-22
US20200185349A1 (en) 2020-06-11
JP2015170855A (ja) 2015-09-28

Similar Documents

Publication Publication Date Title
CN104900606A (zh) 超薄嵌入半导体装置封装及其制造方法
US10186477B2 (en) Power overlay structure and method of making same
CN104051377B (zh) 功率覆盖结构及其制作方法
CN104425435B (zh) 具有散热器的重叠模塑的基板‑芯片布置
KR102295990B1 (ko) 임베딩된 반도체 디바이스 패키지 및 그 제조 방법
CN103515340B (zh) 电源模块封装和用于制造电源模块封装的方法
CN110517991B (zh) 金属陶瓷模块及其制造方法、电路板模块及其制造方法
US10064287B2 (en) System and method of providing a semiconductor carrier and redistribution structure
US20110088936A1 (en) Method for manufacturing an electronic assembly
CN102456638A (zh) 用于倒装芯片封装的顺应式散热器
US10249558B2 (en) Electronic part mounting heat-dissipating substrate
US10420204B2 (en) Wiring board having electrical isolator and moisture inhibiting cap incorporated therein and method of making the same
CN104377172A (zh) 具有嵌入式无源部件的芯片封装件
US20160211207A1 (en) Semiconductor assembly having wiring board with electrical isolator and moisture inhibiting cap incorporated therein and method of making wiring board
JP6945513B2 (ja) 電子制御装置
KR20090062070A (ko) 방열 특성이 우수한 금속 회로 기판 및 그 제조 방법
JP2002043510A (ja) 半導体パワーモジュールおよびその製造方法
JP2010103231A (ja) 電子装置
US20090126967A1 (en) Thermal packaging of transmission controller using carbon composite printed circuit board material
JP2024515155A (ja) 半導体デバイス用の半導体パワーモジュールおよび半導体パワーモジュールを製造する方法ならびに半導体デバイス
JP2024513524A (ja) 成形体を備えるパワー半導体モジュール、およびパワー半導体モジュールの製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant