CN104795337A - 电力用半导体装置及其制造方法 - Google Patents
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Abstract
本发明得到一种电力用半导体装置及其制造方法,能够使金属细线与引线框的接触不易发生,提高成品率。首先,在电力用芯片焊盘上安装电力用半导体元件。然后,在配置于比电力用芯片焊盘高的位置处的控制用芯片焊盘上,安装对电力用半导体元件进行控制的控制用半导体元件。然后,将电力用半导体元件与控制用半导体元件利用金属细线电连接。电力用芯片焊盘具有配置在金属细线下方并向上方弯曲的弯曲部(9)。然后,向由上模具(10)与下模具(11)构成的腔室(12)内放入电力用芯片焊盘、控制用芯片焊盘、电力用半导体元件、控制用半导体元件以及金属细线,利用树脂(8)封装。此时,从电力用芯片焊盘侧向控制用芯片焊盘侧注入树脂(8)。
Description
技术领域
本发明涉及一种利用树脂封装的电力用半导体装置及其制造方法。
背景技术
在半导体装置中,电力用半导体装置在铁路车辆、混合动力汽车、电动汽车等车辆、家电设备、工业用机械等方面,被利用于对比较大的电力进行控制、整流。在使用时,由于电力用半导体元件发热,因此对电力用半导体装置中元件的散热性提出了要求。另外,由于施加几百V以上的高电压,因此需要与装置外部绝缘。
在此,IPM(Intelligent Power Module)是电力用半导体元件与控制用半导体元件成为一体而形成的模块。在作为配线材料而使用引线框的情况下,电力用半导体元件与控制用半导体元件被安装在以物理形式分离的芯片焊盘上,并利用金属细线等电连接。由于电力用半导体元件会有大电流通过,因此发热较大,要求具有作为模块的散热性。作为散热构造的一种,存在下述构造,即,通过使用高导热的树脂薄薄地填充在模块的背面,从而进行散热。此时,通过将搭载电力用半导体元件的芯片焊盘的位置设为比搭载控制用半导体元件的芯片焊盘低,从而降低热阻。
高导热的树脂被高密度地填充了承担散热的填料,粘度高。可以想到,高粘度树脂的流动阻力变大,因此,由于该流动阻力而使例如金属细线等变形。
为了抑制与控制用半导体元件连接的金属细线的变形,通常大多使树脂从电力用半导体元件侧向控制用半导体元件侧流动(例如,参照专利文献1)。树脂在从电力用半导体元件的电力用芯片焊盘上表面向控制用半导体元件的控制用芯片焊盘流动时,会向控制用芯片焊盘上表面、下表面两个方向流动。此时,由于向控制用芯片焊盘的下表面流动的树脂具有向下的矢量,因此,对金属细线作用将其压倒的流动阻力,导致金属细线的变形变大,与引线框或元件发生短路,从而导致成品率变差。
对此,提出了下述方案,即,将树脂注入口的引线框弯曲而改变树脂的流动性,并预先使一部分树脂量经由电力用芯片焊盘下方而填充至控制用芯片焊盘下方。(例如,参照专利文献1)。
专利文献1:日本特开2014-172239号公报
专利文献2:日本特开平1-268159号公报
但是,由于电力用芯片焊盘的上表面、下表面的流量截面积不同,因此,大部分的树脂会向电力用芯片焊盘的上表面流动。因此,存在下述问题,即,相对于金属细线产生向下的流动,变形量变大。
发明内容
本发明就是为了解决上述课题而提出的,其目的在于,得到一种能够使金属细线与引线框的接触不易发生,提高成品率的电力用半导体装置及其制造方法。
本发明所涉及的电力用半导体装置的制造方法的特征在于,具有下述工序:在电力用芯片焊盘上安装电力用半导体元件的工序;在配置于比所述电力用芯片焊盘高的位置处的控制用芯片焊盘上,安装对所述电力用半导体元件进行控制的控制用半导体元件的工序;利用金属细线将所述电力用半导体元件与所述控制用半导体元件电连接的工序;以及在由上模具与下模具构成的腔室内放入所述电力用芯片焊盘、所述控制用芯片焊盘、所述电力用半导体元件、所述控制用半导体元件以及所述金属细线,并利用树脂进行封装的工序,所述电力用芯片焊盘具有配置在所述金属细线的下方并向上方弯曲的弯曲部,从所述电力用芯片焊盘侧向所述控制用芯片焊盘侧注入所述树脂。
发明的效果
在本发明中,电力用芯片焊盘具有配置在金属细线的下方并向上方弯曲的弯曲部。在模塑时,从电力用芯片焊盘侧向控制用芯片焊盘侧注入的树脂在通过弯曲部后,流动的矢量朝向上方,因此金属细线从下向上受到反作用力。因此,金属细线与引线框的接触不易发生,提高成品率。
附图说明
图1是表示本发明的实施方式1所涉及的电力用半导体装置的俯视图。
图2是沿图1的Ⅰ-Ⅱ线的剖面图。
图3是表示图1的装置内部的放大俯视图。
图4是将本发明的实施方式1所涉及的电力用半导体装置的弯曲部的前端部和控制用芯片焊盘的放大后的剖面图。
图5是表示本发明的实施方式1所涉及的电力用半导体装置的制造方法的剖面图。
图6是表示本发明的实施方式1所涉及的电力用半导体装置的变形例的剖面图。
图7是表示本发明的实施方式2所涉及的电力用半导体装置的俯视图。
图8是沿图7的Ⅰ-Ⅱ线的剖面图。
图9是表示本发明的实施方式2所涉及的电力用半导体装置的制造方法的剖面图。
图10是表示图9的装置内部的放大俯视图。
图11是表示可动销的动作的放大剖面图。
图12是表示本发明的实施方式3所涉及的电力用半导体装置的制造方法的剖面图。
图13是表示本发明的实施方式4所涉及的电力用半导体装置的制造方法的放大俯视图。
图14是表示本发明的实施方式5所涉及的电力用半导体装置的制造方法的放大俯视图。
标号的说明
1引线框,2电力用芯片焊盘,3控制用芯片焊盘,4电力用半导体元件,5绝缘片,6控制用半导体元件,7金属细线,8树脂,9弯曲部,10上模具,11下模具,12腔室,14套筒,15可动销
具体实施方式
参照附图,对本发明的实施方式所涉及的电力用半导体装置及其制造方法进行说明。有时对于相同或对应的构成要素,标注相同的标号,省略重复说明。
实施方式1.
图1是表示本发明的实施方式1所涉及的电力用半导体装置的俯视图。图2是沿图1的Ⅰ-Ⅱ线的剖面图。图3是表示图1的装置内部的放大俯视图。
引线框1具有外引线和内引线,内引线具有与外引线连接的引线、电力用芯片焊盘2以及配置在比电力用芯片焊盘2高的位置处的控制用芯片焊盘3。RC-IGBT(Reverse Conducting–Insulated GateBipolar Transistor)等电力用半导体元件4通过无铅焊料安装在电力用芯片焊盘2上。并不限定于无铅焊料,也可以是导电性粘接剂,只要使用具有导电性的接合材料即可。
由绝缘层和铜箔构成的绝缘片5粘接在电力用芯片焊盘2的背面。对电力用半导体元件4进行控制的控制用半导体元件6通过导电性粘接剂安装在控制用芯片焊盘3上。
金属细线7将电力用半导体元件4与控制用半导体元件6电连接。具体地说,在电力用半导体元件4的表面设置有源极电极与栅极电极,源极电极与引线通过Al导线电连接,栅极电极与控制用半导体元件6通过Au导线电连接,控制用半导体元件6与引线全部通过Au导线电连接。此外,Al导线也可以是包含Cu的导线,Au导线也可以是包含Cu的导线。
由树脂8对电力用芯片焊盘2、控制用芯片焊盘3、电力用半导体元件4、控制用半导体元件6以及金属细线7进行封装。树脂8为了兼顾绝缘性与散热性,是在环氧树脂等树脂中含有SiO2或BN等导热填料的树脂。利用树脂8封装的电力用半导体装置,是在背面使绝缘片5的铜箔露出,引线框1的外引线从两端部突出,除此之外的部分由树脂封装的构造的DIP型封装。在外引线中,一侧是功率外引线,另一侧是控制外引线。
在电力用半导体元件4与控制用半导体元件6之间,电力用芯片焊盘2具有配置在金属细线7的下方并向上方弯曲的弯曲部9。电力用芯片焊盘2和弯曲部9不与控制用芯片焊盘3物理接触。
图4是将本发明的实施方式1所涉及的电力用半导体装置的弯曲部的前端部和控制用芯片焊盘放大后的剖面图。弯曲部9的前端部位于比控制用芯片焊盘3的上表面低的位置。因此,金属细线7与引线框1的接触不易发生。
下面,对上述电力用半导体装置的制造方法进行说明。图5是表示本发明的实施方式1所涉及的电力用半导体装置的制造方法的剖面图。首先,在电力用芯片焊盘2上通过焊料安装电力用半导体元件4。在电力用芯片焊盘2的背面粘接绝缘片5。然后,在配置于比电力用芯片焊盘2高的位置处的控制用芯片焊盘3上,通过导电性粘接剂安装对电力用半导体元件4进行控制的控制用半导体元件6。
然后,利用金属细线7将电力用半导体元件4与控制用半导体元件6电连接。具体地说,通过Al导线将电力用半导体元件4与引线连接,通过Au导线将电力用半导体元件4与控制用半导体元件6连接,且将控制用半导体元件6与引线连接。
然后,向由上模具10与下模具11构成的腔室12内,放入电力用芯片焊盘2、控制用芯片焊盘3、电力用半导体元件4、控制用半导体元件6以及金属细线7,并进行合模。然后,将熔融的具有热固化性的树脂8挤入到腔室12内,使其热固化、成型并进行封装。在该传递模塑时,为了抑制由树脂8引起Au导线漂移,因而从电力用芯片焊盘2侧向控制用芯片焊盘3侧注入树脂8。在树脂8遍布于腔室12内后,经由熔融的树脂8向腔室12内施加流体静压。施加流体静压后,在树脂8已硬化的定时,打开模具取出成型品,传递模塑完成。通过该传递模塑将电力用芯片焊盘2与绝缘片5压固而形成封装体。然后,将外引线加工成规定的尺寸、形状,制造工序完成。
在本实施方式中,电力用芯片焊盘2具有配置在金属细线7的下方并向上方弯曲的弯曲部9。在模塑时,从电力用芯片焊盘2侧向控制用芯片焊盘3侧注入的树脂8通过弯曲部9后,由于流动的矢量朝向上方,因此金属细线7从下向上受到反作用力。因此,即使作为树脂8使用高粘度的高导热树脂,金属细线7与引线框1的接触也不易发生,使成品率提高。并且,由于金属细线7变得不易变形,所以能够提高树脂8的流速,提高生产率。另外,通过使用高导热且高粘度的树脂8,并且将电力用半导体元件4小型化,从而能够实现产品的小型化。
另外,在利用树脂8进行封装时,在电力用芯片焊盘2的背面粘接绝缘片5。并且,通过树脂8与弯曲部9碰撞而在电力用芯片焊盘2上产生反作用,从而能够使电力用芯片焊盘2与绝缘片5的粘接性提高,将绝缘片5以均匀的厚度压固,因此得到良好的绝缘性与散热性,使品质稳定。
图6是表示本发明的实施方式1所涉及的电力用半导体装置的变形例的剖面图。通过金属细线7将电力用半导体元件4的上表面与控制用半导体元件6的上表面直接连接。并且,将弯曲部9配置在电力用半导体元件4与控制用半导体元件6之间。由此,金属细线7与引线框1的接触变得更加不易发生。并且,通过使用较细的金属细线7而使成本降低。
实施方式2.
图7是表示本发明的实施方式2所涉及的电力用半导体装置的俯视图。图8是沿图7的Ⅰ-Ⅱ线的剖面图。没有如实施方式1所示的绝缘片5,取而代之,在电力用芯片焊盘2下方填充有树脂8。在弯曲部9的下方,在树脂8的底面设置有凹陷13。其他结构与实施方式1相同。
下面,对上述电力用半导体装置的制造方法进行说明。图9是表示本发明的实施方式2所涉及的电力用半导体装置的制造方法的剖面图。图10是表示图9的装置内部的放大俯视图。图11是表示可动销的动作的放大剖面图。
在腔室12的底面与弯曲部9之间配置套筒14。在可动销15从该套筒14向弯曲部9突出,将电力用芯片焊盘2与下模具11分离而实施支撑的状态下,向腔室12内注入树脂8,在电力用芯片焊盘2与下模具11之间填充树脂8。
另外,使可动销15从配置在弯曲部9下方的套筒14向弯曲部9突出。由此,在模塑时,即使由于碰到弯曲部9后的树脂8将电力用芯片焊盘2向下按压,也能够将电力用芯片焊盘2与下模具11分离而实施支撑。因此,能够维持电力用芯片焊盘2与下模具11的间隔,因此树脂8能够充分地遍布于电力用芯片焊盘2的下方,能够确保绝缘性。
并且,在将树脂8填充至电力用芯片焊盘2的下方,并即将施加流体静压之前,将可动销15向下侧移动并拔出。在施加流体静压后,在树脂8已硬化的定时,打开模具,取出成型品,传递模塑完成。此时,套筒14被转印在电力用半导体装置的背面而留下凹陷13。此外,套筒14是为了防止在拔出可动销15时产生的毛刺而设置的。
另外,能够预想到在将树脂8填充至电力用芯片焊盘2下方时,电力用芯片焊盘2向上方偏移的情况。为了防止这种情况,当前是在上模具10上也设置可动销,从上方也压住电力用芯片焊盘2。与此相对,在本实施方式中,如果树脂8与弯曲部9碰撞,则电力用芯片焊盘2因反作用而受到向下方的力,因此,能够防止电力用芯片焊盘2向上方偏移。因此,无需在上模具10上设置可动销等,因此,能够提高上模具10的维护性,并降低成本。
另外,在没有弯曲部9的情况下,设置在电力用芯片焊盘2与下模具11之间的套筒14的高度,会制约电力用芯片焊盘2下方的树脂8的厚度。但是,通过在弯曲部9的下方配置套筒14,由此能够使电力用芯片焊盘2下方的树脂8变薄而降低热阻。由于套筒14的高度必须至少大于或等于0.1mm,因此能够使电力用芯片焊盘2下方的树脂8的厚度变薄至少大于或等于0.1mm。因此,散热性变得良好,因此能够提高产品的寿命,实现与电力用半导体元件4的小型化相伴的电力用半导体装置的小型化。
实施方式3.
图12是表示本发明的实施方式3所涉及的电力用半导体装置的制造方法的剖面图。弯曲部9具有2个弯曲部分,弯曲部9的前端部与腔室12的底面平行。可动销15与该弯曲部9的前端部接触。由此,可动销15相对于弯曲部9的接触由点变成面,因此电力用芯片焊盘2的固定位置的厚度方向的偏移变得不易发生,因此能够减少电力用芯片焊盘2下的树脂8的厚度波动。
实施方式4.
图13是表示本发明的实施方式4所涉及的电力用半导体装置的制造方法的放大俯视图。利用2个可动销15对电力用芯片焊盘2进行支撑。如上述所示,通过包含上模具10与下模具11在内由3个点对电力用芯片焊盘2进行支撑,从而能够在平面方向上稳定地固定电力用芯片焊盘2,因此能够减少电力用芯片焊盘2下的树脂8的厚度波动。
实施方式5.
图14是表示本发明的实施方式5所涉及的电力用半导体装置的制造方法的放大俯视图。可动销15跨越多个电力用芯片焊盘2中的相邻2个进行支撑。由此,能够利用较少的可动销15实现稳定的固定,使模具的维护性提高。
此外,电力用半导体元件4并不限定于由硅形成,也可以由与硅相比带隙较大的宽带隙半导体形成。宽带隙半导体是例如碳化硅、氮化镓类材料或者金刚石。由这种宽带隙半导体形成的电力用半导体元件4,由于耐电压性、容许电流密度高,因此能够小型化。通过使用该小型化后的元件,能够将组装有该元件的电力用半导体装置也小型化。另外,由于元件的耐热性高,因此能够使散热装置的散热片小型化,能够使用空气冷却代替水冷部,因此,能够使电力用半导体装置进一步小型化。另外,由于元件的电力损失低、效率高,因此能够使电力用半导体装置高效率化。
Claims (12)
1.一种电力用半导体装置的制造方法,其特征在于,
具有下述工序:
在电力用芯片焊盘上安装电力用半导体元件的工序;
在配置于比所述电力用芯片焊盘高的位置处的控制用芯片焊盘上,安装对所述电力用半导体元件进行控制的控制用半导体元件的工序;
利用金属细线将所述电力用半导体元件与所述控制用半导体元件电连接的工序;以及
在由上模具与下模具构成的腔室内放入所述电力用芯片焊盘、所述控制用芯片焊盘、所述电力用半导体元件、所述控制用半导体元件以及所述金属细线,并利用树脂进行封装的工序,
所述电力用芯片焊盘具有配置在所述金属细线的下方并向上方弯曲的弯曲部,
从所述电力用芯片焊盘侧向所述控制用芯片焊盘侧注入所述树脂。
2.根据权利要求1所述的电力用半导体装置的制造方法,其特征在于,
在利用所述树脂进行封装时,在所述电力用芯片焊盘的背面粘接绝缘片。
3.根据权利要求1所述的电力用半导体装置的制造方法,其特征在于,
在所述腔室的底面与所述弯曲部之间配置套筒,
在可动销从所述套筒向所述弯曲部突出,将所述电力用芯片焊盘与所述下模具分离而对所述电力用芯片焊盘实施支撑的状态下,向所述腔室内注入所述树脂,在所述电力用芯片焊盘与所述下模具之间填充所述树脂。
4.根据权利要求3所述的电力用半导体装置的制造方法,其特征在于,
所述弯曲部具有2个弯曲部分,所述弯曲部的前端部与所述腔室的底面平行,
所述可动销与所述弯曲部的所述前端部接触。
5.根据权利要求3或4所述的电力用半导体装置的制造方法,其特征在于,
利用大于或等于2个所述可动销对所述电力用芯片焊盘进行支撑。
6.根据权利要求3或4所述的电力用半导体装置的制造方法,其特征在于,
所述电力用芯片焊盘具有多个芯片焊盘,
所述可动销跨越所述多个芯片焊盘中的相邻的2个进行支撑。
7.根据权利要求1~4中任一项所述的电力用半导体装置的制造方法,其特征在于,
所述弯曲部的前端部位于比所述控制用芯片焊盘的上表面低的位置处。
8.根据权利要求1~4中任一项所述的电力用半导体装置的制造方法,其特征在于,
利用所述金属细线将所述电力用半导体元件的上表面与所述控制用半导体元件的上表面直接连接,
将所述弯曲部配置在所述电力用半导体元件与所述控制用半导体元件之间。
9.一种电力用半导体装置,其特征在于,具有:
引线框,其具有电力用芯片焊盘、以及配置于比所述电力用芯片焊盘高的位置处的控制用芯片焊盘;
电力用半导体元件,其安装在所述电力用芯片焊盘上;
控制用半导体元件,其安装在所述控制用芯片焊盘上,控制所述电力用半导体元件;
金属细线,其将所述电力用半导体元件与所述控制用半导体元件电连接;以及
树脂,其对所述电力用芯片焊盘、所述控制用芯片焊盘、所述电力用半导体元件、所述控制用半导体元件以及所述金属细线进行封装,
所述电力用芯片焊盘具有配置在所述金属细线的下方并向上方弯曲的弯曲部。
10.根据权利要求9所述的电力用半导体装置,其特征在于,
还具有绝缘片,该绝缘片粘接在所述电力用芯片焊盘的背面。
11.根据权利要求9所述的电力用半导体装置,其特征在于,
所述弯曲部的前端部位于比所述控制用芯片焊盘的上表面低的位置处。
12.根据权利要求9所述的电力用半导体装置,其特征在于,
所述金属细线将所述电力用半导体元件的上表面与所述控制用半导体元件的上表面直接连接,
所述弯曲部配置在所述电力用半导体元件与所述控制用半导体元件之间。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108604578A (zh) * | 2016-02-09 | 2018-09-28 | 三菱电机株式会社 | 电力用半导体装置及其制造方法 |
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JP6416055B2 (ja) * | 2015-08-24 | 2018-10-31 | 三菱電機株式会社 | 半導体装置 |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05278077A (ja) * | 1992-04-02 | 1993-10-26 | Fuji Electric Co Ltd | トランスファモールド金型 |
JPH05299454A (ja) * | 1992-04-24 | 1993-11-12 | Matsushita Electron Corp | 半導体製造装置 |
US5750423A (en) * | 1995-08-25 | 1998-05-12 | Dai-Ichi Seiko Co., Ltd. | Method for encapsulation of semiconductor devices with resin and leadframe therefor |
JP2000138343A (ja) * | 1998-10-30 | 2000-05-16 | Mitsubishi Electric Corp | 半導体装置 |
JP2003142510A (ja) * | 2001-11-02 | 2003-05-16 | Mitsubishi Electric Corp | 半導体デバイスの製造方法 |
JP2007165425A (ja) * | 2005-12-12 | 2007-06-28 | Mitsubishi Electric Corp | 半導体装置 |
JP2012236404A (ja) * | 2011-04-27 | 2012-12-06 | Panasonic Corp | 樹脂封止成形品の製造方法 |
CN102820288A (zh) * | 2011-06-10 | 2012-12-12 | 三菱电机株式会社 | 功率模块及其制造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6466959A (en) * | 1987-09-07 | 1989-03-13 | Nec Corp | Resin seal type semiconductor device |
JP4146785B2 (ja) * | 2003-11-19 | 2008-09-10 | 三菱電機株式会社 | 電力用半導体装置 |
JP4469654B2 (ja) * | 2004-05-13 | 2010-05-26 | パナソニック株式会社 | 半導体装置及び半導体装置の製造方法 |
-
2014
- 2014-01-17 JP JP2014006992A patent/JP6183226B2/ja active Active
-
2015
- 2015-01-16 CN CN201510023708.3A patent/CN104795337A/zh active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05278077A (ja) * | 1992-04-02 | 1993-10-26 | Fuji Electric Co Ltd | トランスファモールド金型 |
JPH05299454A (ja) * | 1992-04-24 | 1993-11-12 | Matsushita Electron Corp | 半導体製造装置 |
US5750423A (en) * | 1995-08-25 | 1998-05-12 | Dai-Ichi Seiko Co., Ltd. | Method for encapsulation of semiconductor devices with resin and leadframe therefor |
JP2000138343A (ja) * | 1998-10-30 | 2000-05-16 | Mitsubishi Electric Corp | 半導体装置 |
JP2003142510A (ja) * | 2001-11-02 | 2003-05-16 | Mitsubishi Electric Corp | 半導体デバイスの製造方法 |
JP2007165425A (ja) * | 2005-12-12 | 2007-06-28 | Mitsubishi Electric Corp | 半導体装置 |
JP2012236404A (ja) * | 2011-04-27 | 2012-12-06 | Panasonic Corp | 樹脂封止成形品の製造方法 |
CN102820288A (zh) * | 2011-06-10 | 2012-12-12 | 三菱电机株式会社 | 功率模块及其制造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108604578A (zh) * | 2016-02-09 | 2018-09-28 | 三菱电机株式会社 | 电力用半导体装置及其制造方法 |
CN108604578B (zh) * | 2016-02-09 | 2021-07-16 | 三菱电机株式会社 | 电力用半导体装置及其制造方法 |
US11107746B2 (en) | 2016-02-09 | 2021-08-31 | Mitsubishi Electric Corporation | Power semiconductor apparatus and manufacturing method therefor |
CN112041984A (zh) * | 2018-05-09 | 2020-12-04 | 三菱电机株式会社 | 功率半导体装置及其制造方法以及电力变换装置 |
CN112041984B (zh) * | 2018-05-09 | 2023-12-22 | 三菱电机株式会社 | 功率半导体装置及其制造方法以及电力变换装置 |
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