CN104756615A - 印刷电路板 - Google Patents
印刷电路板 Download PDFInfo
- Publication number
- CN104756615A CN104756615A CN201380056949.7A CN201380056949A CN104756615A CN 104756615 A CN104756615 A CN 104756615A CN 201380056949 A CN201380056949 A CN 201380056949A CN 104756615 A CN104756615 A CN 104756615A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- printed circuit
- pcb
- insulating barrier
- electronic installation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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- 239000012790 adhesive layer Substances 0.000 claims abstract description 34
- 230000004888 barrier function Effects 0.000 claims description 82
- 238000009434 installation Methods 0.000 claims description 66
- 238000009422 external insulation Methods 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 9
- 229920005989 resin Polymers 0.000 claims description 9
- 239000003365 glass fiber Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 239000011889 copper foil Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 238000010276 construction Methods 0.000 description 5
- 239000011247 coating layer Substances 0.000 description 4
- 238000009413 insulation Methods 0.000 description 3
- 239000011435 rock Substances 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 208000034189 Sclerosis Diseases 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 229920002313 fluoropolymer Polymers 0.000 description 1
- 239000004811 fluoropolymer Substances 0.000 description 1
- 229910003471 inorganic composite material Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H05K1/00—Printed circuits
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- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
- H05K3/305—Affixing by adhesive
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H05K1/00—Printed circuits
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- H05K1/00—Printed circuits
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- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
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- H05K2201/10007—Types of components
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Abstract
提供了一种印刷电路板,其包括:绝缘层;嵌入绝缘层中的电子装置;以及用于固定电子装置的粘合层。
Description
技术领域
本发明涉及印刷电路板。
背景技术
印刷电路板(PCB)是通过使用导电材料例如Cu在电绝缘基板上印刷电路线图案而形成的,并且指的是仅在电子部件安装之前的板。也就是,PCB指的是这样的板:其被配置成使得在平板上密集安装各种电子装置,每个部件的安装位置固定,并且通过在平板的表面上印刷用于连接部件的电路图案使电路板固定。
近来,已经提供了一种嵌入式印刷电路板,其中每个部件嵌入并且安装在嵌入式印刷电路板中。
图1示出了一种通用嵌入式印刷电路板。
参照图1,通用嵌入式印刷电路板10配置成使得电子装置4、5嵌入在多个绝缘层1、2、3中,并且形成有用于向多个绝缘层1、2、3施加电力的嵌入式电路图案以及用于使不同层的电路彼此连接的通孔。
嵌入式电子装置4、5具有形成在其上部中的钎料或缓冲体。
电子装置4、5布置在绝缘层1、2、3的腔中,然后绝缘层1、2、3被施压以固定电子装置1、2、3。
然而,当绝缘层1、2、3被施压时,电子装置4、5移动并且转动,从而造成设计上的偏差(d)。
发明内容
技术问题
本发明的一个方面提供了一种可以防止电子装置移动的嵌入式印刷电路板。
问题的解决方案
根据本发明的一个方面,提供了一种印刷电路板,其包括:绝缘层;嵌入在绝缘层中的电子装置;以及用于固定电子装置的粘合层。
发明的有益效果
根据本发明,在嵌入有电子装置的印刷电路板中,当安装电子装置时,因为形成了与电子装置的厚度无关的绝缘层,所以可以形成具有与电子装置的尺寸无关的期望厚度的印刷电路板。
附图说明
包括附图以提供对本发明的进一步的理解,并且将附图合并到本说明书中且构成本说明书的一部分。附图示出了本发明的示例性实施例,附图与描述一起用于说明本发明的原理。在附图中:
图1是根据常规技术的印刷电路板的截面图;
图2是根据本发明的示例性实施例的印刷电路板的截面图;以及
图3至图21是示出了一种制造图2的印刷电路板的方法的截面图。
具体实施方式
下文中,将参照附图以本发明能够被本发明所属技术领域的普通技术人员容易实施的方式对本发明的优选实施例进行详细描述。然而,本发明可以以不同形式实施,并且不应该将其理解为仅限于本文中所陈述的实施例。相反,提供这些实施例使得本公开内容更加全面和完整,并且将本发明的全部范围传达给本领域的普通技术人员。本文中所使用的术语仅用于描述具体实施例的目的,而非意在限制示例性实施例。
还应该理解,术语“包括”或“包含”当用于本说明书中时指明了所陈述的特征、整体、步骤、操作、元件和/或部件的存在,但是不排除一个或更多个其它特征、整体、步骤、操作、元件、部件和/或其组合的存在或增加。
为了清楚地说明本发明,省略了与说明无关的部分,并且为了清楚地表示各个层和区域,将其厚度放大。此外,在整个附图的描述中,相似的附图标记可以指代相似的元件。
当提及一个部件例如层、膜、区域和板等在另一部件“之上”时,这包括其中该部件刚好在另一部件之上的情况以及其中在该部件与另一部件之间存在又一部件的情况。相反,当提及一个部件刚好在另一部件之上时,这意味着在一个部件与另一部件的中间不存在又一部件。
本发明提供了一种有关其中嵌入并且安装有电子装置200的嵌入式印刷电路板的印刷电路板,电子装置200可以在没有任何移动的情况下安装至该印刷电路板。
下文中,将参照图2至图21说明根据本发明的示例性实施例的印刷电路板。
图2是根据本发明的示例性实施例的印刷电路板的截面图。
参照图2,根据本发明的印刷电路板100包括:第一绝缘层110;形成在第一绝缘层110上和形成在第一绝缘层110之下的内部电路图案121;布置在第一绝缘层110与内部电路图案121之间的引导层104;形成在第一绝缘层110的上部和下部中的第二绝缘层160和第三绝缘层165;形成在第二绝缘层160和第三绝缘层165之上的外部电路图案175和盖层(cover lay)180;以及嵌入在印刷电路板100中的多个电子装置。
形成绝缘板的第一绝缘层110、第二绝缘层160、第三绝缘层165可以是热固性或热塑性聚合物基板、陶瓷基板、有机无机复合材料基板或玻璃纤维浸渍基板。在该层包括聚合物树脂的情况下,可以包括环氧基绝缘树脂。然而,与此不同,可以包括聚酰亚胺基树脂。
第一绝缘层110、第二绝缘层160和第三绝缘层165可以由彼此不同的材料形成。作为一个示例,第一绝缘层110可以是包括玻璃纤维的浸渍基板,并且第二绝缘层160和第三绝缘层165可以由仅由树脂形成的绝缘板构造。
第一绝缘层110可以形成为比第二绝缘层160和第三绝缘层165厚。
第一绝缘层110可以包括用于安装电子装置200的装置布置部,在第一绝缘层110的上部和下部中可以分别形成内部电路图案,并且在第一绝缘层110的上部和下部中还可以形成用于连接上部和下部的内部电路图案121的导电通路120。
引导层104布置在第一绝缘层110与内部电路图案121之间,并且用于引导电子装置200的布置。
更具体地对其进行说明,引导层104形成其中布置有电子装置的并且具有开口形状的装置区域,并且引导层104的装置区域形成为具有比电子装置200的宽度大的宽度。
此时,引导层104可以配置成仅布置在第一绝缘层110的一个表面上,并且可以配置成布置在第一绝缘层110与外部绝缘层之间。例如,如图2所示,引导层104可以布置在第一绝缘层110与作为外部绝缘层的第二绝缘层160之间。
同时,引导层104可以由包括树脂材料的绝缘层形成。
外部电路图案175可以形成在第二绝缘层160和第三绝缘层165的上部中,第二绝缘层160和第三绝缘层165分别形成在第一绝缘层110的上部和下部中。
外部电路图案175的一部分可以连接至电子装置220的端子。
在外部电路图案175与电子装置200之间形成有穿过第二绝缘层160和穿过第三绝缘层165的通路173。
通路173可以仅形成在电子装置200的一个表面上,或者可以形成在上部和下部两者中。
通过第一绝缘层110、第二绝缘层160和第三绝缘层165而嵌入的电子装置200可以是无源元件或有源元件。例如,电子装置200可以是电阻器、电感器、电容器、或集成电路(IC)。在电子装置的上表面或下表面上形成有用于接收从外部提供的电流或压力的端子210。
在其中电子装置200的端子210形成的方向上形成有覆盖电子装置200的端子210的粘合层220。粘合层220可以形成为具有与电子装置200的宽度相同的宽度,或者可以形成为具有比电子装置200的宽度大的宽度。
粘合层220可以配置成使得在干膜的两个表面上涂覆有粘合糊,并且端子210接触其上涂覆有粘合糊的一个表面。
粘合层220的厚度可以根据压力而变化,并且粘合层200可以由绝缘材料形成。
电子装置200布置在第一绝缘层110中,并且利用粘合层220接合至作为外部绝缘层的第二绝缘层160的一个表面。粘合层220的一个表面接触电子装置200,并且粘合层220的另一表面接触作为外部绝缘层的第二绝缘层160。
由此,如图2所示,粘合层的另一表面和第一绝缘层110的一个表面布置在一个平面中。粘合层220还包括将内部电路图案121与电子装置220的端子210连接的通路123。
与导电通路120不同,通路123可以配置成使得其内部部分嵌入有导电材料。通路123和外部电路图案175通过通路173连接。
连接至通路173的焊盘175可以延伸至第二绝缘层160和第三绝缘层165的上表面。
内部电路图案121和外部电路图案175可以由包括Cu的合金形成,并且内部电路图案121和外部电路图案175可以形成为至少两层。
外部电路图案175由盖层180保护与外部隔绝。
盖层180可以由干膜或通用阻焊剂形成,并且可以形成为打开外部电路图案175的一部分作为焊盘。
在打开的焊盘的上表面上形成有表面处理层181。
表面处理层181可以是镀覆处理层181或有机膜处理层。
在以上说明中,说明了电路图案121、175形成为两层。然而,与此不同,电路图案可以形成为多个层。
在印刷电路板100中,由于引导层104和粘合层220形成为使得待嵌入的电子装置200未移动,所以可以改进激光通路173与装置端子210之间的阵列的偏差。另外,由于粘合层220的厚度可变,所以通过控制激光通路173的尺寸,端子的间距可以减小至小于150μm。
另外,粘合层220使得能够执行层中的连接,从而使得能够执行非对称连接。
下文中,将参照图3至图21说明制造印刷电路板100的方法。
图3至图21是示出了制造根据本发明的一个示例性实施例的印刷电路板100的方法的截面图。
首先,如图3所示,制备基底板。
基底板是用于印刷电路板的层叠的支承板,可以通过在绝缘载板101上层叠铜箔层102形成。
接着,如图4所示,通过使用钻机在基底板的边缘中形成沟槽103来限定有源区域。
在作为其中形成有装置和图案的区域的有源区域中,同时形成多个印刷电路板,之后通过切割印刷电路板将多个印刷电路板分成各个印刷电路板。
接着,在铜箔层102上形成引导层104。
引导层104形成其中布置有电子装置200的并且具有开口形状的装置区域105。引导层104用于引导电子装置200的布置,并且引导层104的装置区域105形成为具有比所布置的电子装置的宽度大的宽度。
引导层104可以由包括树脂材料的绝缘层形成。通过引导层104打开的装置区域105可以形成为具有比电子装置200的尺寸大的尺寸。
引导层104可以形成为覆盖沟槽103。
接着,将电子装置200安装至装置区域105。
电子装置200可以是无源元件或有源元件。例如,电子装置200可以是电阻器、电感器、或电容器。
首先,如图6所示,通过将粘合层220接合在其上形成有电子装置200的端子的表面上来执行装置的安装。
可以使用其中在干膜的两个表面上涂覆有粘合糊的绝缘膜来形成粘合层220,并且粘合层220可以形成为具有与电子装置200的宽度相等的宽度或具有大于电子装置200的宽度的宽度。
将粘合层220的一个粘合表面布置为接触端子210,并且将另一粘合表面布置为接触装置区域105。相应地,将粘合层220配置成覆盖端子210。
接着,通过硬化粘合层220将电子装置200固定至装置区域105。
如图7所示,将电子装置200布置成以预定距离与引导层104间隔开。
接着,形成图8的第一绝缘层110。
第一绝缘层110可以形成为具有多个绝缘层的层叠结构,并且可以为在其内部部分中具有玻璃纤维的预浸料。
第一绝缘层110可以形成为下层和上层。下层可以包括预浸料,并且上层可以仅由绝缘树脂形成。
下层可以形成为具有打开电子装置200的开口111,并且上层可以形成为覆盖电子装置200的上部。还将铜箔层130接合在第一绝缘层110上。
接着,通过在高温下对图8的层叠结构施压并且对其硬化来形成图9的层叠结构。
由于施压过程,树脂从第一绝缘层渗入电子装置200和绝缘层中的间隔的空隙中,从而使得电子装置200能够如图9所示固定。
当第一绝缘层110的硬化完成时,通过移除载板101露出铜箔层。
接着,如图11所示,在将基板翻转使得电子装置200的端子210看上去向上之后,如图12所示,从上铜箔层102至下铜箔层130形成穿过第一绝缘层110的通过孔131。
可以通过激光钻孔工艺形成通过孔131。然而,与此不同,可以执行机加工工艺或钻孔工艺。
另外,通过蚀刻从上铜箔层102至粘合层220的区域来形成露出电子装置200的端子210的通孔132。
可以通过物理钻孔工艺形成通孔132。与此不同,可以使用激光来形成通孔132。当使用激光来形成通孔132时,可以使用YAG激光或CO2激光来打开铜箔层102和粘合层220。
接着,如图13所示,形成镀覆层122以覆盖通过孔131的侧表面以及上部和下部的铜箔层102。在形成镀覆层122以嵌入通孔132之后,如图14所示,通过图案化镀覆层122形成内部电路图案121,并且形成覆盖通路123和通过孔131的导电通路120。
然后,如图15所示,在待施压的第一绝缘层的上表面和下表面上布置第二绝缘层160、第三绝缘层165以及下铜箔层171,从而形成图16的层叠结构。
然后,如图17所示,通过同时蚀刻具有层叠结构的第二绝缘层160和第三绝缘层165、铜箔层171来形成其中露出内部电路图案121或通路120、123的上通孔172。
接着,如图18所示,通过执行镀覆来嵌入上通孔172。如图19所示,通过图案化上部和下部的镀覆层来形成外部电路图案175和通路173。
此时,将上通路173部分连接至通路123使得电子装置200的端子210电暴露于外部。
接着,如图20所示,在形成打开通路焊盘的阻焊剂180之后,通过镀覆在露出的焊盘上形成表面处理层181,使得如图21所示,完成印刷电路板100。
像这样,在其中嵌入有电子装置200的嵌入式印刷电路板100中,当安装电子装置200时,在其上形成有电子装置200的端子的表面上形成粘合层220使得端子210固定,然后将粘合层220用作绝缘层,从而可以减小板的厚度并且可以通过固定电子装置200来减小阵列的偏差。
如前所述,在本发明的详细描述中,已经描述了本发明的详细示例性实施例,明显地是,本领域技术人员在不脱离本发明的精神或范围的情况下可以做出修改和变化。因此,应该理解,前述是用于说明本发明的,而不应被解释为限于所公开的具体实施例,并且对所公开的实施例做出的修改方案以及其他实施例意在包括在所附权利要求及其等同内容的范围内。
Claims (19)
1.一种印刷电路板,包括:
绝缘层;
嵌入所述绝缘层中的电子装置;以及
用于固定所述电子装置的粘合层。
2.根据权利要求1所述的印刷电路板,还包括覆盖所述绝缘层的外部绝缘层,其中所述粘合层的一个表面接触所述电子装置,并且所述粘合层的另一表面接触所述外部绝缘层。
3.根据权利要求2所述的印刷电路板,其中所述粘合层的所述另一表面和所述绝缘层的一个表面布置在一个平面中。
4.根据权利要求1所述的印刷电路板,还包括用于引导所述电子装置的布置的引导层。
5.根据权利要求4所述的印刷电路板,其中所述引导层形成装置区域,所述电子装置布置在所述装置区域中并且所述装置区域具有开口形状。
6.根据权利要求5所述的印刷电路板,其中所述引导层的所述装置区域形成为具有比所述电子装置的宽度大的宽度。
7.根据权利要求4所述的印刷电路板,其中所述引导层布置在所述绝缘层与覆盖所述绝缘层的所述外部绝缘层之间。
8.根据权利要求4所述的印刷电路板,其中所述引导层仅布置在所述绝缘层的所述一个表面上。
9.根据权利要求1所述的印刷电路板,其中所述绝缘层包括其中布置有所述电子装置的装置布置部。
10.根据权利要求2所述的印刷电路板,其中所述电子装置布置在所述绝缘层中并且所述电子装置通过所述粘合层接合至所述外部绝缘层的一个表面。
11.根据权利要求1所述的印刷电路板,其中所述电子装置为无源元件或有源元件。
12.根据权利要求1所述的印刷电路板,其中所述绝缘层包括其中浸渍有玻璃纤维的树脂材料。
13.根据权利要求1所述的印刷电路板,其中所述绝缘层的厚度形成为大于包括所述电子装置和所述粘合层的宽度。
14.根据权利要求1所述的印刷电路板,其中所述粘合层配置成使得在干膜的两个表面上涂覆有粘合糊。
15.根据权利要求1所述的印刷电路板,其中所述粘合层形成为具有与所述电子装置的宽度相等或具有比所述电子装置的宽度大的宽度。
16.根据权利要求1所述的印刷电路板,其中所述粘合层配置成覆盖所述电子装置的端子。
17.根据权利要求1所述的印刷电路板,还包括形成在所述绝缘层上的内部电路图案。
18.根据权利要求17所述的印刷电路板,还包括通孔,所述通孔形成为穿过所述绝缘层使得所述内部电路图案和所述电子装置的所述端子彼此连接。
19.根据权利要求2所述的印刷电路板,还包括形成在所述外部绝缘层上的外部电路图案。
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KR10-2012-0123386 | 2012-11-02 | ||
KR20120123386A KR101438915B1 (ko) | 2012-11-02 | 2012-11-02 | 인쇄회로기판 및 그의 제조 방법 |
PCT/KR2013/004112 WO2014069734A1 (en) | 2012-11-02 | 2013-05-09 | Printed circuit board |
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CN104756615A true CN104756615A (zh) | 2015-07-01 |
CN104756615B CN104756615B (zh) | 2018-09-04 |
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US (1) | US9781835B2 (zh) |
EP (1) | EP2915415A4 (zh) |
KR (1) | KR101438915B1 (zh) |
CN (1) | CN104756615B (zh) |
TW (1) | TWI549579B (zh) |
WO (1) | WO2014069734A1 (zh) |
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KR20200070773A (ko) | 2018-12-10 | 2020-06-18 | 엘지이노텍 주식회사 | 인쇄회로기판 및 이의 제조 방법 |
US11587881B2 (en) * | 2020-03-09 | 2023-02-21 | Advanced Semiconductor Engineering, Inc. | Substrate structure including embedded semiconductor device |
US11335646B2 (en) | 2020-03-10 | 2022-05-17 | Advanced Semiconductor Engineering, Inc. | Substrate structure including embedded semiconductor device and method of manufacturing the same |
KR20230049373A (ko) * | 2021-10-06 | 2023-04-13 | 삼성전기주식회사 | 회로기판 |
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Also Published As
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US20150296625A1 (en) | 2015-10-15 |
TW201419961A (zh) | 2014-05-16 |
WO2014069734A1 (en) | 2014-05-08 |
TWI549579B (zh) | 2016-09-11 |
KR101438915B1 (ko) | 2014-09-11 |
EP2915415A1 (en) | 2015-09-09 |
KR20140056916A (ko) | 2014-05-12 |
CN104756615B (zh) | 2018-09-04 |
US9781835B2 (en) | 2017-10-03 |
EP2915415A4 (en) | 2016-10-05 |
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