TWI549579B - 印刷電路板 - Google Patents

印刷電路板 Download PDF

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Publication number
TWI549579B
TWI549579B TW102118459A TW102118459A TWI549579B TW I549579 B TWI549579 B TW I549579B TW 102118459 A TW102118459 A TW 102118459A TW 102118459 A TW102118459 A TW 102118459A TW I549579 B TWI549579 B TW I549579B
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Taiwan
Prior art keywords
layer
insulating layer
printed circuit
circuit board
electronic device
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TW102118459A
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English (en)
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TW201419961A (zh
Inventor
鄭元席
李圭洹
安允鎬
李又英
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Ｌｇ伊諾特股份有限公司
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Publication of TW201419961A publication Critical patent/TW201419961A/zh
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Publication of TWI549579B publication Critical patent/TWI549579B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H05K1/0298—Multilayer circuits
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    • H05K1/115—Via connections; Lands around holes or via connections
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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Description

印刷電路板
本發明係主張關於2012年11月2日申請之韓國專利申請字號第10-2012-0123386號之優先權，以引用的方式併入本文參考。
本發明係有關一種印刷電路板。
使用導電材料(例如銅)在一電性絕緣基板上印刷一電路線圖案以形成一印刷電路板(Printed Circuit Board，PCB)，意即一用以固定電子裝置的基板。也就是說，一電路板為具有緊密安裝各種電子裝置在一平面基板上的結構，每個元件安裝的位置是固定的，並藉由印刷用來將該些電子裝置固定於該平面基板的電路圖案將該電路板固定。
近來，已經有嵌入並安裝各元件的嵌入式印刷電路板。
圖1繪示一般嵌入式印刷電路板。
對照圖1，一般嵌入式印刷電路板10結構係為：嵌入在絕緣層1、2、3之間的電子裝置4、5，一嵌入式電路圖案係用以施加電力至該些絕緣層1、2、3，及形成一貫孔使得不同層的電路彼此連接。
嵌入式電子裝置4、5具有一焊料或緩衝區形成在其上部。
嵌入式電子裝置4、5配置在絕緣層1、2、3的孔穴中，然後對絕緣層1、2、3施加壓力以固定電子裝置4、5。
然而，當對絕緣層1、2、3施加壓力時，電子裝置4、5的移動及轉動造成一設計上的誤差d。
本發明之一目的在於提供一種嵌入式印刷電路板以防止電子裝置移動。
根據本發明之一目的，提供一嵌入式印刷電路板，包括：一 絕緣層；多個電子裝置嵌入在該絕緣層中；以及一黏著層用以固定該些電子裝置。
根據本發明，在嵌入該電子裝置的印刷電路板中，當安裝該些電子裝置時，可以無需考量該些電子裝置的厚度來形成該絕緣層，所以可形成一具有預定厚度的印刷電路板而無需考量該些電子裝置的尺寸。
1、2、3‧‧‧絕緣層
4、5‧‧‧電子裝置
100‧‧‧印刷電路板
101‧‧‧載板
102‧‧‧銅箔層
103‧‧‧溝槽
104‧‧‧引導層
105‧‧‧裝置區域
110‧‧‧第一絕緣層
111‧‧‧開口
120‧‧‧導孔
121‧‧‧內部電路圖案
122‧‧‧電鍍層
123‧‧‧介層窗
130‧‧‧銅箔層
131‧‧‧貫穿孔
132‧‧‧貫孔
160‧‧‧第二絕緣層
165‧‧‧第三絕緣層
171‧‧‧銅箔層
172‧‧‧上貫孔
173‧‧‧上通孔
175‧‧‧外部電路圖案
180‧‧‧覆蓋膜
181‧‧‧表面處理層
200‧‧‧電子裝置
210‧‧‧端子
220‧‧‧黏著層
d‧‧‧誤差
所附圖式係提供對本發明之深入理解，並且併入及構成本說明書的一部份。所附圖式配合說明書說明本發明之實施例以解釋本發明之原理。圖式中：
圖1係根據一習知技術繪示一印刷電路板剖面圖。
圖2係根據本發明之一實施例繪示一印刷電路板剖面圖。
圖3至圖21係說明圖2之印刷電路板製造方法之剖面圖。
以下將配合所附圖式，詳細說明本發明之實施例，使本發明可以很容易地被熟習本領域技術人員實施。然而本發明可以不同形式實施，並且不應被解釋為限制於此處之實施例。相反地，該些實施例係用以使本發明詳盡及完整，並將本發明的範疇充份地傳達給熟習本技術的領域人士。此處所用之術語僅用於描述特定實施例，而非用以限縮示例性實施例。
「包括」及「包含」在本說明書中使用時，指出表示特徵、整數、步驟、操作、元件及/或組件的存在，但不排除一個或多個其它特徵、整數、步驟、操作、元件、組件及/或組合的存在或增加。
用以清楚解釋本發明時，與說明無關的部份將被省略，而用以清楚地表達各層及各區域時，其厚度將被放大。同樣地，在整個說明書圖式中，相同的數字代表相同的元件。
當提及某一部份如一層、膜、區域、平面等位於另一部份”上方”時，此處包含兩種情形，其中該部份位於該另一部份之上，及兩者之間仍有另外一部份存在。相反地，當提及一部份位於另一部份”之上”， 表示兩者之間沒有其它部份存在。
關於嵌入並安裝有電子裝置200的一嵌入式印刷電路板中，本發明提供一印刷電路板，於其上安裝電子裝置200時不會有任何的移動。
以下，根據本發明的示例性實施例的印刷電路板將配合圖2至圖21詳細說明。
圖2係根據本發明之一實施例繪示一印刷電路板剖面圖。
對照圖2，根據本發明之印刷電路板100包括：一第一絕緣層110；一內部電路圖案121形成於第一絕緣層110之上及第一絕緣層110之下；一引導層104配置於第一絕緣層110及內部電路圖案121之間；一第二絕緣層160及一第三絕緣層165形成於第一絕緣層110之上部及下部；一外部電路圖案175及一覆蓋膜180形成於第二絕緣層160及第三絕緣層165之上；以及複數個電子裝置嵌入印刷電路板100中。
形成一絕緣平面之第一絕緣層110、第二絕緣層160及第三絕緣層165可為一熱固性或熱塑性聚合物基板、一陶瓷基板、一有機-無機複合材料基板或一玻璃纖維預浸(glass fiber-impregnated)基板。當一聚合樹脂被包括其中時，可包含一環氧基(epoxy-based)絕緣樹脂。然而，與此不同的是，可包含一聚酰亞胺基(polymide-based)樹脂。
第一絕緣層110、第二絕緣層160及第三絕緣層165可以彼此不同材料形成。舉例來說，第一絕緣層110可為包含玻璃纖維之一預浸基板，而第二絕緣層160及第三絕緣層165可被配置為僅由樹脂形成之一絕緣片。
第一絕緣層110的厚度可形成為大於第二絕緣層160及第三絕緣層165的厚度。
第一絕緣層110可包括一裝置配置部以安裝電子裝置200，內部電路圖案121可分別形成於第一絕緣層110之上部及下部，一導孔(conductive via)120用以連接上部的內部電路圖案121，而下部的內部電路圖案121同樣可形成於第一絕緣層110的上部及下部。
引導層104配置於第一絕緣層110及內部電路圖案121之 間，而引導層104用以引導電子裝置200之配置。
更清楚地說明，引導層104在配置電子裝置處形成一裝置區域，並具有一開口形狀，而引導層104之裝置區域以大於電子裝置200的寬度形成。
同時，引導層104僅被配置在第一絕緣層110之一表面上，並被配置於第一絕緣層110及一外部絕緣層之間。例如，如圖2所示，引導層104可配置於第一絕緣層110及第二絕緣層160之間，而第二絕緣層160即為一外部絕緣層。
同時，引導層104可由包含一樹脂材料之絕緣層形成。
外部電路圖案175可形成在第二絕緣層160及第三絕緣層165之上部，而第二絕緣層160及第三絕緣層165分別形成於第一絕緣層110之上部及下部。
外部電路圖案175的一部份係連接至電子裝置200的一端。
通孔(via)173形成於外部電路圖案175及電子裝置200之間，並通過第二絕緣層160及第三絕緣層165。
通孔173可僅形成於電子裝置200之一表面或同時形成於電子裝置200之上部及下部。
嵌入第一絕緣層110、第二絕緣層160及第三絕緣層165的電子裝置200可為一被動元件或一主動元件。例如，電子裝置200可為一電阻器、一電感器、一電容器或一積體電路(integrated circuit，IC)。端子210形成於電子裝置200之上表面或下表面以接收外部施加的電流或壓力。
覆蓋電子裝置200之端子210的黏著層220與電子裝置200之端子210形成於同一方向。黏著層220形成一具有與電子裝置200相同之寬度，或具有一大於電子裝置200之寬度。
黏著層220可為將一黏著劑塗覆在一乾膜之兩表面的方式，而端子210與塗覆有黏著劑之一表面接觸。
黏著層220之厚度可依壓力而變化，而且黏著層220可由一絕緣材料形成。
電子裝置200配置於第一絕緣層110中並與第二絕緣層160 之一面黏合，第二絕緣層160為一外部絕緣層，且藉由黏著層220與第一絕緣層110黏合。黏著層220之一表面與電子裝置200接觸，而黏著層220之另一表面與第二絕緣層160接觸，第二絕緣層160為一外部絕緣層。
因此，如圖2所示，黏著層220之另一表面及第一絕緣層110之一表面係配置於同一平面上。黏著層220更包含一介層窗(via)123，介層窗123連接內部電路圖案121及電子裝置200之端子210。
與導孔120不同的是，介層窗123可被配置為內部嵌入一導電材料。介層窗123及外部電路圖案175係透過通孔173連接。
與通孔173連接的外部電路圖案175可延伸至第二絕緣層160及第三絕緣層165之上表面。
內部電路圖案121與外部電路圖案175可由包含銅(Cu)的合金形成，而內部電路圖案121及外部電路圖案175可由至少兩層形成。
外部電路圖案175係被覆蓋膜180從外部保護。
覆蓋膜180可由一乾膜或一般阻焊劑所形成，並可被形成以開放外部電路圖案175之一部份做為一焊墊。
表面處理層181形成於開放焊墊之上部。
表面處理層181可為一電鍍處理層或一有機薄膜處理層。
於上述說明，已說明電路圖案121及175係形成為兩層。然而，與此不同的，電路圖案係形成為複數層。
在印刷電路板100中，由於引導層104及黏著層220的形成，而使得被嵌入的電子裝置200不會移動，並可改善雷射通孔173及裝置端子210之間配置上的偏向。同時，當黏著層220的厚度可調變，藉由控制雷射通孔173的尺寸可將端子的間距(pitch)減少至小於150um。
同樣地，黏著層220使得層與層之間的連接得以進行，因此得以進行非對稱連接。
以下，將參照圖3至圖21說明製造印刷電路板100方法。
圖3至圖21為根據本發明之一實施例之製造印刷電路板100方法剖面圖。
首先，如圖3所示，準備一基板(base board)。
基板為由層壓一銅箔層102於一絕緣載板101上而形成之一支撐板，用以層壓印刷電路板。
接下來，如圖4所示，利用鑽頭(drill)在基板邊緣形成一溝槽103以界定出一作動區(active area)。
作動區為裝置及圖案形成之區域，並同時形成多個印刷電路板，然後藉由切割印刷電路板而被分為各個印刷電路板。
接著，引導層104形成於銅箔層102之上。
引導層104形成一配置有電子裝置200的裝置區域105，並具有一開口形狀。引導層104之功用係引導電子裝置200之配置，而引導層104的裝置區域105以具有一大於被配置的電子裝置之寬度形成。
引導層104由包含樹脂材料的絕緣層形成。由引導層104之開口形成的裝置區域105以具有一大於電子裝置200之尺寸形成。
引導層104形成以覆蓋溝槽103。
接下來，電子裝置200被安裝於裝置區域105。
電子裝置200可為一被動裝置或一主動裝置。例如，電子裝置200可為一電阻、一電感器或一電容器。
首先，如圖6所示，將黏著層220黏著於形成電子裝置200端子之一表面上而進行裝置之安裝。
黏著層220係使用一絕緣薄膜形成，該絕緣薄膜為將黏著劑塗覆覆於一乾膜之兩個表面上，而黏著層220可形成為具有一寬度大於或等於電子裝置200之寬度。
黏著層220之一黏著面係配置為與端子210接觸，而黏著層220之另一黏著面係配置與裝置區域105接觸。因此，黏著層220配置以覆蓋端子210。
接著，電子裝置200藉由硬化的黏著層220固定於裝置區域105。
如圖7所示，電子裝置200與引導層104配置為間隔一預定距離。
接著，形成圖8中的第一絕緣層110。
第一絕緣層110形成為一疊層結構而具有多個絕緣層，而其內部為一具有玻璃纖維之預浸(prepreg)材料。
第一絕緣層110可由一下層及一上層形成。下層可包含預浸材料，而上層可僅由一絕緣樹脂形成。
下層形成具有一開口111以容納電子裝置200，而上層形成以覆蓋電子裝置200的上部。銅箔層130亦黏合於第一絕緣層110上。
接著，如圖9所示之疊層結構藉由在高溫下對圖8中的疊層結構加壓硬化而形成。
由於加壓製程，樹脂從第一絕緣層110滲透入電子裝置200與絕緣層的間隙中，使得電子裝置200得以如圖9所示被固定。
當第一絕緣層110硬化完成，藉由移除載板101來露出銅箔層。
接著，如圖11所示，當基板被翻轉後使得電子裝置200的端子210朝上，如圖12所示，通過第一絕緣層110的貫穿孔131係由上銅箔層102形成至下銅箔層130。
貫穿孔131可由雷射鑽孔製程形成。然而，與此不同的，同樣可進行機械加工製程(machining process)及鑽孔製程。
同樣地，暴露出電子裝置200之端子210的貫孔132係由蝕刻上銅箔層102至黏著層220而形成。
貫孔132可由實體鑽孔製程形成。與此不同的，同樣可由雷射形成。當貫孔132由雷射形成，銅箔層102及黏著層220可使用釔鋁石榴石雷射(Yttrium aluminum garnet laser，YAG laser)或二氧化碳雷射(CO2 laser)形成。
接著，如圖13所示，電鍍層122形成以覆蓋貫穿孔131之一側面及銅箔層102之上部及下部。在電鍍層122形成以嵌入貫孔132後，如圖14所示，內部電路圖案121由將電鍍層122圖案化形成，而導孔120形成以覆蓋介層窗123及貫穿孔131。
如圖15所示，第二絕緣層160及第三絕緣層165及銅箔層171之下層配置於第一絕緣層110之上下表面而進行加壓，進而形成如圖16 所示之疊層結構。
如圖17所示，於上貫孔172中暴露出內部電路圖案121或導孔120、介層窗123，而上貫孔172係由同時蝕刻銅箔層171及具有疊層結構的第二絕緣層160及第三絕緣層165而形成。
接著，如圖18所示，上貫孔172藉由進行電鍍而嵌入。如圖19所示，藉由圖案化電鍍層的上部及下部，形成外部電路圖案175及通孔173。
同時，上通孔173與介層窗123部份連接使得電子裝置200的端子210電性地暴露於外部。
接著，如圖20所示，在開放貫孔墊的阻焊層180形成後，表面處理層181透過電鍍形成於暴露出來的貫孔墊上，如圖21所示，印刷電路板製作完成。
如同嵌入有電子裝置200的嵌入式印刷電路板100，當安裝電子裝置200，黏著層220在電子裝置200之端子形成的表面上形成，使端子210被固定，然後黏著層220可作為絕緣層用，因此而減少印刷電路板的厚度並藉由固定電子裝置200而減少配置的偏向。
如前所述，在本發明的詳細說明中，已詳細說明本發明的示範性實施例，在不脫離本發明之精神和範圍內，熟習此類技藝者可據此而做出修改及變化。因此，前述內容為本發明之示例而非用以限定本發明於特定揭露之實施例，根據本發明已揭露之實施例所做之修改及等效替換，仍於本發明之專利保護範圍之內。
100‧‧‧印刷電路板
104‧‧‧引導層
110‧‧‧第一絕緣層
120‧‧‧導孔
121‧‧‧內部電路圖案
123‧‧‧介層窗
160‧‧‧第二絕緣層
165‧‧‧第三絕緣層
173‧‧‧通孔
175‧‧‧外部電路圖案
180‧‧‧覆蓋膜
181‧‧‧表面處理層
200‧‧‧電子裝置
210‧‧‧端子
220‧‧‧黏著層

Claims (17)

  1. 一種印刷電路板，包括：一絕緣層；一電子裝置，其嵌入該絕緣層中；一黏著層，用以固定該電子裝置；以及一引導層，其位於該絕緣層上，用以引導該電子裝置之排列。
  2. 如申請專利範圍第1項所述之印刷電路板，更包括一外部絕緣層以覆蓋該絕緣層，其中該黏著層之一表面與該電子裝置接觸，而該黏著層之另一表面與該外部絕緣層接觸。
  3. 如申請專利範圍第2項所述之印刷電路板，其中該黏著層之該另一表面及該絕緣層之一表面配置於同一平面上。
  4. 如申請專利範圍第1項所述之印刷電路板，其中該引導層形成一裝置區域以設置該電子裝置，而該裝置區域具有一開口形狀。
  5. 如申請專利範圍第4項所述之印刷電路板，其中該引導層之該裝置區域以具有大於該電子裝置之寬度而形成。
  6. 如申請專利範圍第1項所述之印刷電路板，其中該引導層配置於該絕緣層及該外部絕緣層之間以覆蓋該絕緣層。
  7. 如申請專利範圍第1項所述之印刷電路板，其中該引導層僅配置於該絕緣層之一表面上。
  8. 如申請專利範圍第2項所述之印刷電路板，其中該電子裝置配置於該絕緣層中，並藉由該黏著層黏合至該外部絕緣層之一表面。
  9. 如申請專利範圍第1項所述之印刷電路板，其中該電子裝置為一被動裝置或一主動裝置。
  10. 如申請專利範圍第1項所述之印刷電路板，其中該絕緣層包括一預浸玻璃纖維的樹脂材料。
  11. 如申請專利範圍第1項所述之印刷電路板，其中該絕緣層以大於包含該電子裝置及該黏著層之厚度形成。
  12. 如申請專利範圍第1項所述之印刷電路板，其中該黏著層為以塗覆一黏著劑於一乾膜之兩表面的配置。
  13. 如申請專利範圍第1項所述之印刷電路板，其中該黏著層以具有一大於或等於該電子裝置之寬度而形成。
  14. 如申請專利範圍第1項所述之印刷電路板，其中該黏著層配置以覆蓋該電子裝置之端子。
  15. 如申請專利範圍第1項所述之印刷電路板，其中更包括一內部電路圖案形成於該絕緣層上。
  16. 如申請專利範圍第15項所述之印刷電路板，更包括一介層窗以穿透該黏著層而形成，使該內部電路圖案及該電子裝置之端子彼此連接。
  17. 如申請專利範圍第2項所述之印刷電路板，更包括一外部電路圖案形成於該外部絕緣層上。
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