CN104737286B - 接触凸块连接以及接触凸块和用于建立凸块接触连接的方法 - Google Patents

接触凸块连接以及接触凸块和用于建立凸块接触连接的方法 Download PDF

Info

Publication number
CN104737286B
CN104737286B CN201380042531.0A CN201380042531A CN104737286B CN 104737286 B CN104737286 B CN 104737286B CN 201380042531 A CN201380042531 A CN 201380042531A CN 104737286 B CN104737286 B CN 104737286B
Authority
CN
China
Prior art keywords
contact
space
joint face
squeezing
contact tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201380042531.0A
Other languages
English (en)
Other versions
CN104737286A (zh
Inventor
卡斯滕·尼兰
弗兰克·克里贝尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Si Maida Science And Technology Ltd Co
Original Assignee
Si Maida Science And Technology Ltd Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Si Maida Science And Technology Ltd Co filed Critical Si Maida Science And Technology Ltd Co
Publication of CN104737286A publication Critical patent/CN104737286A/zh
Application granted granted Critical
Publication of CN104737286B publication Critical patent/CN104737286B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/301Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/116Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1162Manufacturing methods by patterning a pre-deposited material using masks
    • H01L2224/11622Photolithography
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13006Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13011Shape comprising apertures or cavities, e.g. hollow bump
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16113Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81205Ultrasonic bonding
    • H01L2224/81206Direction of oscillation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134Bonding interfaces of the bump connector
    • H01L2224/81345Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81897Mechanical interlocking, e.g. anchoring, hook and loop-type fastening or the like
    • H01L2224/81898Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9211Parallel connecting processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/1059Connections made by press-fit insertion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/0415Small preforms other than balls, e.g. discs, cylinders or pillars
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49016Antenna or wave energy "plumbing" making
    • Y10T29/49018Antenna or wave energy "plumbing" making with other electrical component
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Multi-Conductor Connections (AREA)
  • Manufacturing Of Electrical Connectors (AREA)
  • Measuring Leads Or Probes (AREA)

Abstract

本发明涉及一种接触凸块连接(24)和一种用于在设有至少一个第一连接面(11)的电子器件和与所述器件接触的具有至少一个第二连接面(25)的接触衬底(26)之间建立接触凸块连接(24)的方法,其中所述第一连接面设有接触凸块(10),所述接触凸块具有边缘突出部(15)和在由所述边缘突出部至少部分地围绕的并且朝向所述接触凸块的头端部敞开的挤入空间(18)中具有至少一个挤入销(16),并且所述第二连接面在与所述第一连接面的接触区域(31)中具有通过将所述第二连接面的接触材料(29)挤入所述挤入空间中而构成的围绕所述挤入销的接触凸起部(30),所述接触凸起部具有朝向所述挤入空间的底部(17)的并且相对于所述第二连接面的围绕所述接触区域的平坦的接触表面(32)凸起的凸冠(33)。

Description

接触凸块连接以及接触凸块和用于建立凸块接触连接的方法
技术领域
本发明涉及一种在设有至少一个第一连接面的电子器件和与所述器件接触的具有至少一个第二连接面的接触衬底之间的接触凸块连接以及一种用于建立接触凸块连接的接触凸块和一种用于建立接触凸块连接的方法。
背景技术
开头所提到的类型的接触凸块连接通常用于芯片的连接面与接触衬底的连接面的接触。尤其是,这类接触凸块连接(其中芯片借助于所谓的“倒装芯片”法用其与接触衬底的连接面相对的连接面设置在接触衬底上)用于制造所谓的“无接触的芯片卡”,所述无接触的芯片卡借助于与接触衬底的连接面接触的天线实现在芯片和数据读取设备之间无接触的数据传输。
一般而言,芯片的“倒装芯片”接触需要预备芯片的具有接触凸块的连接面,所述接触凸块在专业术语上也通常称为“Bump(凸块)”。借助于接触凸块可能的是,使芯片的连接面与接触衬底的连接面能导电地接触,而不需要电线导体或者其他与芯片无关的接触装置。
从DE 101 57 205 A1中已知一种用于制造接触凸块的方法,所述方法实现了接触凸块的构成,所述接触凸块具有特别的表面形貌,所述表面形貌具有接触凸块的上部分,所述上部分具有隆起部,所述隆起部例如柱状或者星状地构成并且要实现对连接材料的改进的容纳,所述连接材料(例如粘合材料或者焊接材料)要实现建立设置在芯片的连接面上的接触凸块与接触衬底的连接面之间的能导电的连接。此外,接触凸块的已知的表面形貌要实现使接触衬底的连接面上的氧化层破裂并且最终也通过接触凸块的隆起部的接合建立与接触衬底的连接面的机械连接。
对此,提出接触凸块的表面形貌,所述表面形貌具有在接触凸块的接触底座上不同地构成的或者不同地设置的隆起部,其中所述隆起部要么位于接触底座的中央区域中要么位于边缘底座的边缘区域中并且要通过接合到接触衬底的连接面的接触材料中实现与接触衬底的接触材料化部的局部咬合。
在试验中现已证明:具有上文所描述的类型的接触凸块的接触凸块连接的特征在于高剪切强度。然而,在芯片与接触衬底分离的试验中所达到的抗拉强度并不令人满意,使得在已知的接触凸块连接中为了足够的机械保护除了接触凸块和接触衬底的接触材料化部之间的机械连接外还需要在芯片和接触衬底之间使用粘合剂。
基本上在使用粘合剂用于机械上可保持或者可受载地接触接触衬底上的芯片时已证实不利的是:由于粘合剂连接的硬化通常需要的反应时间在建立这类连接时可实现的产品数量是有限的。
发明内容
因此,本发明基于下述目的:提出一种接触凸块连接,所述接触凸块连接在不使用附加的连接材料如尤其是粘合剂的情况下已实现建立可持久保持的、耐受实际中出现的机械负荷的机械连接。
该目的通过具有根据本发明的实施例的特征的接触凸块连接实现。
在根据本发明的接触凸块连接中,第一连接面设有接触凸块,所述接触凸块具有边缘突出部和在通过边缘突出部包入的并且朝向接触凸块的头端部敞开的挤入空间中具有至少一个挤入销,并且第二连接面在与第一连接面的接触区域中具有通过将第二连接面的接触材料挤入到挤入空间中而构成的围绕挤入销的接触凸起部,所述接触凸起部具有朝向挤入空间的底部的并且相对于第二连接面的围绕接触区域的平坦的接触表面凸起的凸冠。
根据本发明的接触凸块连接因此具有设置在第一连接面上的接触凸块和第二连接面的接触材料之间的形状配合,其中挤入空间通过接触销具有内部的限界部并且通过边缘突出部具有外部的限制部,即在接触凸块的挤入空间内显著地进行接触材料挤入,使得构成朝向挤入空间的底部延伸的凸冠并且在接触凸块与接触材料之间得到相应地伸至远处的轴向侵入部。由于挤入空间通过挤入销和边缘突出部不仅径向在内部而且径向在外部限界,接触材料不仅被加载有径向向内而且被加载有径向向外的压力,使得一方面在接触材料与挤入销之间的并且另一方面在接触材料与边缘突出部之间的接触面上实现接触材料对边缘突出部的表面形貌的贴合,其中通过接触材料填充挤入空间的壁的表面形貌中的可能的不平坦部或者凹处并且填满挤入空间的壁中的可能的侧凹部。
由此结果是:不仅提供电子器件(即例如芯片)的接触凸块和接触衬底的接触材料之间的轴向侵入部,而且除此之外也提供接触凸块和接触材料的径向侵入部或者径向的彼此接合部,使得能够由接触凸块连接吸收对接触凸块连接起分离作用的拉伸负荷。
这样的拉伸负荷例如在芯片卡受到弯曲负荷的情况下出现,所述弯曲负荷实际中是危害芯片卡的功能的决定性负荷。
在接触凸块连接的一个优选的实施方式中,边缘突出部环绕地构成并且在周边对挤入空间限界,使得实现特别强的挤入效果。
已证实对于实现接触凸块连接的大抗拉强度特别有利的是,挤入销的自由端设置在边缘突出部的上边缘之下,即挤入空间被划分为从挤入销的自由端延伸直至边缘突出部的上边缘的无挤入阻挡的挤入空间部段和从挤入空间的底部延伸直至挤入销的自由端部的设有挤入销作为挤入阻挡的带挤入阻挡的挤入空间部段。
无挤入阻挡的挤入空间部段在建立这类接触凸块连接时首先以接触材料来填充,其中在建立连接时的压入阻挡在该第一阶段期间由于在该无挤入阻挡的空间中不存在挤入阻挡的事实能够以比较小的压入力来执行。在压入过程继续时首先随着接触材料继续挤入到带挤入阻挡的挤入空间部段中出现由带挤入阻挡的空间中的内压提高引起的压入力升高。由此可能的是,在对接触材料的机械接触开始时,已经用尽可能小的压入力建立接触凸块的目标明确的定位并且在实现接触之后才提高压入力,以便最后通过在挤入空间中构成凸冠来结束机械可受载的形状配合的连接的建立。
尤其有利的是,带挤入阻挡的挤入空间部段构成为环形空间,使得在接触凸块和接触材料之间的接触平面中得到对称的压力负荷。
尤其有利的是,第一连接面由芯片或者芯片模块的连接面形成并且第二连接面由天线导体的连接端部形成,使得用于构成天线导体的材料同时形成接触衬底的连接面的接触材料并因此实现了接触凸块和在接触衬底上构成的电子器件(即天线导体)之间的特别直接的接触。
根据本发明的接触凸块具有根据本发明的实施例的特征。
根据本发明,接触凸块具有边缘突出部和在由边缘突出部围绕的并且朝向接触凸块的头端部敞开的挤入空间中具有至少一个挤入销,所述挤入销与通过边缘突出部径向在外侧限界的挤入空间组合地具有已经在上文中详细阐述的优点。
优选地,边缘突出部环绕地构成并且在周边对挤入空间限界,使得边缘突出部围绕挤入空间并且实现了特别强的挤入效果。
优选地,挤入销的自由端部设置在边缘突出部的上边缘之下,使得接触凸块具有已经在上文中所阐述的将挤入空间划分为挤入销之上的无挤入阻挡的挤入空间部段和带挤入阻挡的挤入空间部段的构造,所述带挤入阻挡的挤入空间部段从挤入空间的底部伸展直至挤入销的自由端。
优选地,通过在挤入空间中设置挤入销,在边缘突出部和挤入销之间构成环形空间。
根据本发明的方法具有根据本发明的实施例的特征。
根据本发明,为了建立连接面的机械连接,将设置在第一连接面上的接触凸块压入到第二连接面的接触材料的接触表面中,即在接触凸块的挤入空间中第二连接面的接触材料在侵入边缘突出部和挤入销中期间关于压入方向不仅通过边缘突出部径向向内而且通过挤入销径向向外以压力来加载,以便实现已经在上文中详细阐述的接触材料对挤入空间的通过挤入空间中的边缘突出部径向在外部限界的壁面和挤入空间的径向在内侧通过挤入销形成挤入空间的壁面的有利的径向贴合或者到其中的有利的侵入。
优选地,在建立连接的第一阶段中,第二连接面的接触材料在接触凸块的挤入空间中通过接触凸块的边缘突出部径向向内以压力来加载直至达到连接销的自由端部,并且在建立连接的第二阶段中在接触凸块继续侵入第二连接面的接触材料中的情况下接触材料通过边缘突出部和连接销不仅径向向内而且径向向外以压力来加载。
如果第一连接面的接触凸块到第二连接面的接触材料中的压入叠加有振动,那么能够进一步促进接触材料到挤入空间的壁面中的侵入深度。
优选地,叠加振动在横向于压入方向的平面中进行,其中尤其能够使用本身已知的超声装置来在背侧上横向于压入方向给芯片加载压入力和振动。
替选地或者还是补充地,叠加振动也能够沿着压入方向进行。
已证实特别有利的是,应用所述方法来建立设有第一连接面的构成为芯片的电子器件和与所述器件接触的构成为天线衬底的接触衬底之间的接触凸块连接,其中天线导体的连接端部同时构成接触衬底的连接面。
附图说明
接下来,参照附图详细阐述了接触凸块的以及借助于接触凸块所建立的接触凸块连接的优选的实施方式。
附图示出:
图1以剖视图示出接触凸块;
图2示出在图1中所示的接触凸块按照图1中的剖面线II-II的横截面视图;
图3以剖视图示出接触凸块连接;
图4至图6示出建立接触凸块连接的不同的阶段。
具体实施方式
图1示出接触凸块10,所述接触凸块设置在芯片12的连接面11上,其中与接触凸块相邻的芯片表面设有钝化部13。
在图1和图2中示出的接触凸块10具有接触凸块基底14,所述接触凸块基底设有在此闭合的环形环绕的边缘突出部15和中央的挤入销16,所述挤入销设置在通过边缘突出部15径向向外限界的挤入空间18的底部17上。
在图1和图2中示出的接触凸块10基本上能够以不同的方式和方法来制造,其中借助于在芯片12的连接面11上与光刻法组合的无电流的钯沉积或者钯合金的沉积的制造尤其适合于制造接触凸块10,如例如在WO 2000/048242 A1中所描述的那样,其内容通过引用结合到本申请文件中。
借助于沉积法能够制造在图1中示出的接触凸块10的表面的形貌,其中径向在外部对挤入空间18限界的基本上朝向挤入空间开口19锥形地扩宽的外壁20和挤入空间的通过挤入销16限定的锥形地朝向挤入空间开口19渐缩的内壁21设有不均匀部,所述不均匀部构成凸起22和凹处23。
图3示出接触凸块连接24,其中设置在芯片12的连接面11上的接触凸块10与接触衬底26的连接面25连接,其中在当前情况下连接面25通过天线导体27的连接端部形成,所述连接端部线状地或者以例如通过涂层产生的印制导线结构的形式设置在这里构成为载体膜28的衬底上。
为了建立在图3中示出的接触凸块连接24,将接触凸块10从上方压入到通过天线导体27的连接端部形成的连接面25中,其中在当前情况下通过天线导体27形成的接触材料29挤入到挤入空间18中,直至最后在压入过程结束时产生接触材料29的变形,如在图3中所示出的那样,即在挤入空间18内构成围绕挤入销16的接触凸起部30,所述接触凸起部具有朝向挤入空间18的底部17的并且相对于围绕在接触凸块10与连接面25之间的接触区域31的接触表面32凸起的凸冠33。
在图4至图6中示意性地示出在其不同的阶段中的压入过程,其中图4示出在刚要侵入连接面25的仍平坦地构成的接触表面32中之前的接触凸块10。图5示出第一挤入阶段,其中接触材料29通过挤入空间开口19侵入挤入空间部段34中,所述挤入空间部段不具有挤入体,使得接触材料29到挤入空间部段34中的挤入主要由于在径向上从外部通过挤入空间18的外壁20作用到接触材料29上的挤入压力Fa产生。
在压入过程继续时,被挤入到挤入空间18中的接触材料29如在图6中所示出的那样到达具有挤入销16作为挤入体的挤入空间部段35,使得在挤入空间部段35中向内的挤入压力Fi不仅从径向在外部通过挤入空间18的外壁20而且从径向在内部通过由挤入销16形成的内壁21作用于接触材料,由此在构成在图3中示出的凸冠33的情况下加速地并且结合有对于压入所需的力的升高地来进行挤入。
由于作用于接触材料29的外压力Fa和作用于接触材料29的内压力Fi,实现接触材料29贴合挤入空间18的外壁20和内壁21,其中接触材料遵循外壁20和内壁21中的凸起22的轮廓并且同样被压入到外壁20和内壁21的凹处23中,使得不仅在接触凸块10与接触材料29之间沿着压入方向36而且横向于或者径向于压入方向36进行轴向接合。
对于期望附加地加强电子器件(即例如芯片)与接触衬底之间的机械连接的情况,可以在接触凸块的周围环境中和/或在接触衬底的连接面的周围环境中建立接触凸块连接之前或者之后将聚合物粘合剂施加到电子器件和/或接触衬底上。
尤其是,在使用压敏性粘合剂的情况下,可以在建立接触凸块连接期间进行粘合剂的交联。在使用温度敏感性粘合剂的情况下,在建立接触凸块连接之后可以通过事后的温度加载进行交联。
基本上,在没有附加的粘接连接的情况下也提供了在机械上可充分受负荷的接触凸块连接,使得用于粘合剂的交联或硬化的可能的反应时间对建立接触凸块连接所需的时间没有影响。在建立接触凸块连接的情况下连接时间仅由压入过程的持续时间来确定。

Claims (15)

1.一种在电子器件和与所述电子器件接触的接触衬底(26)之间的接触凸块连接(24),所述电子器件设有至少一个第一连接面(11),所述接触衬底(26)具有至少一个第二连接面(25),
其特征在于,
所述第一连接面设有接触凸块(10),所述接触凸块具有边缘突出部(15),所述边缘突出部环形地围绕挤入空间(18),所述挤入空间朝向所述接触凸块的头端部敞开,和所述接触凸块在挤入空间(18)中在所述挤入空间的底部(17)处具有至少一个挤入销(16),并且
其中所述第二连接面在与所述接触凸块(10)的接触区域(31)中通过接触材料(29)挤入所述挤入空间中而构成围绕所述挤入销的接触凸起部(30),所述接触凸起部具有朝向所述挤入空间的底部(17)的并且相对于所述第二连接面的围绕所述接触区域(31)的部分凸起的凸冠(33)。
2.根据权利要求1所述的接触凸块连接,
其特征在于,
所述边缘突出部(15)环绕地构成并且在周边对所述挤入空间(18)限界。
3.根据权利要求1或2所述的接触凸块连接,
其特征在于,
所述挤入销(16)的自由端部设置在所述边缘突出部(15)的上边缘之下,即所述挤入空间(18)被划分为从所述挤入销的自由端部延伸直至所述边缘突出部的上边缘的无挤入阻挡的挤入空间部段(34)和从所述挤入空间的底部(17)延伸直至所述挤入销的自由端部的带挤入阻挡的挤入空间部段(35),所述带挤入阻挡的挤入空间部段(35)设有所述挤入销作为挤入阻挡。
4.根据权利要求3所述的接触凸块连接,
其特征在于,
所述带挤入阻挡的挤入空间部段(35)构成为环形空间。
5.根据权利要求1或2所述的接触凸块连接,
其特征在于,
所述第一连接面(11)由芯片(12)或者芯片模块的连接面形成并且所述第二连接面(25)由天线导体(27)的连接端部形成。
6.一种用于建立根据权利要求1至5中任一项所述的接触凸块连接(24)的接触凸块(10),
其特征在于,
所述接触凸块具有边缘突出部(15),所述边缘突出部环形地围绕挤入空间(18),所述挤入空间朝向所述接触凸块的头端部敞开,和所述接触凸块在挤入空间(18)中在所述挤入空间的底部(17)处具有至少一个挤入销(16)。
7.根据权利要求6所述的接触凸块,
其特征在于,
所述边缘突出部(15)环绕地构成并且在周边对所述挤入空间(18)限界。
8.根据权利要求6或7所述的接触凸块,
其特征在于,
所述挤入销(16)的自由端部设置在所述边缘突出部(15)的上边缘之下。
9.根据权利要求6或7所述的接触凸块,
其特征在于,
通过在所述挤入空间(18)中设置所述挤入销(16),在所述边缘突出部(15)和所述挤入销(16)之间构成环形空间。
10.一种用于在电子器件和与所述电子器件接触的接触衬底(26)之间建立根据权利要求1至5中任一项所述的接触凸块连接(24)的方法,所述电子器件设有至少一个第一连接面(11),所述接触衬底(26)具有至少一个第二连接面(25),
其特征在于,
为了建立连接面(11,25)的机械连接,将设置在所述第一连接面(11)上的接触凸块(10)压入所述第二连接面(25)的接触材料(29) 的接触表面(32)中,即在所述接触凸块的挤入空间(18)中对所述第二连接面的接触材料在所述边缘突出部(15)和所述挤入销(16)侵入所述第二连接面的接触材料中期间关于压入方向(36)不仅通过所述边缘突出部径向向内而且通过所述挤入销径向向外以压力来加载。
11.根据权利要求10所述的方法,
其特征在于,
在建立连接的第一阶段中,对所述第二连接面(25)的接触材料(29)在所述接触凸块(10)的挤入空间(18)中通过所述接触凸块的边缘突出部(15)径向向内以压力来加载,直至达到所述连接销(16)的自由端部,并且在建立连接的第二阶段中在所述接触凸块继续侵入到所述第二连接面的接触材料中时对所述接触材料通过所述边缘突出部和所述连接销不仅径向向内而且径向向外以压力来加载。
12.根据权利要求10或11所述的方法,
其特征在于,
所述第一连接面(11)的所述接触凸块(10)到所述第二连接面(25)的所述接触材料(29)中的压入与振动叠加。
13.根据权利要求12所述的方法,
其特征在于,
所述与振动叠加在横向于所述压入方向(36)的平面中进行。
14.根据权利要求12所述的方法,
其特征在于,
所述与振动叠加沿着压入方向(36)进行。
15.一种将根据权利要求10至14中任一项所述的方法用于制造包括芯片(12)和天线的收发器的应用,即设置在芯片衬底上的所述芯片的设有接触凸块(10)的第一连接面(11)与设置在天线衬底上的天线的连接面接触,所述连接面通过天线导体(27)的连接端部形成,其中所述接触凸块具有边缘突出部(15),所述边缘突出部环形地围绕挤入空间(18),所述挤入空间朝向所述接触凸块的头端部敞开,和所述接触凸块在挤入空间(18)中在所述挤入空间的底部(17)处具有至少一个挤入销(16)。
CN201380042531.0A 2012-08-10 2013-08-09 接触凸块连接以及接触凸块和用于建立凸块接触连接的方法 Active CN104737286B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102012015811 2012-08-10
DE102012015811.4 2012-08-10
PCT/DE2013/000451 WO2014023287A2 (de) 2012-08-10 2013-08-09 Kontakthöckerverbindung sowie kontakthöcker und verfahren zur herstellung einer kontakthöckerverbindung

Publications (2)

Publication Number Publication Date
CN104737286A CN104737286A (zh) 2015-06-24
CN104737286B true CN104737286B (zh) 2018-09-25

Family

ID=49303671

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380042531.0A Active CN104737286B (zh) 2012-08-10 2013-08-09 接触凸块连接以及接触凸块和用于建立凸块接触连接的方法

Country Status (12)

Country Link
US (1) US10292270B2 (zh)
EP (1) EP2883245B1 (zh)
JP (1) JP6347781B2 (zh)
KR (1) KR20150053902A (zh)
CN (1) CN104737286B (zh)
BR (1) BR112015002759B1 (zh)
CA (1) CA2880408A1 (zh)
DE (1) DE102013215771B4 (zh)
IN (1) IN2015MN00491A (zh)
MX (1) MX349946B (zh)
MY (1) MY172360A (zh)
WO (1) WO2014023287A2 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640052A (en) * 1993-03-10 1997-06-17 Nec Corporation Interconnection structure of electronic parts
JP2005197488A (ja) * 2004-01-08 2005-07-21 Sony Corp 突起電極及びボンディングキャピラリ並びに半導体チップ
JP2006310477A (ja) * 2005-04-27 2006-11-09 Akita Denshi Systems:Kk 半導体装置及びその製造方法
CN101295692A (zh) * 2007-04-06 2008-10-29 株式会社日立制作所 半导体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483741A (en) * 1993-09-03 1996-01-16 Micron Technology, Inc. Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice
JPH0870019A (ja) * 1994-08-30 1996-03-12 Casio Comput Co Ltd 電子部品の接続構造および接続方法
US5929521A (en) * 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
JPH11163036A (ja) * 1997-09-17 1999-06-18 Tamura Seisakusho Co Ltd バンプ形成方法、はんだ接合用前処理方法、はんだ接合方法、バンプ形成装置、はんだ接合用前処理装置およびはんだ接合装置
US6028436A (en) * 1997-12-02 2000-02-22 Micron Technology, Inc. Method for forming coaxial silicon interconnects
US6045026A (en) * 1998-02-23 2000-04-04 Micron Technology, Inc. Utilize ultrasonic energy to reduce the initial contact forces in known-good-die or permanent contact systems
JP2000114314A (ja) * 1998-09-29 2000-04-21 Hitachi Ltd 半導体素子実装構造体およびその製造方法並びにicカード
DE19905807A1 (de) 1999-02-11 2000-08-31 Ksw Microtec Ges Fuer Angewand Verfahren zur Herstellung elektrisch leitender Verbindungen
JP2001148401A (ja) * 1999-11-18 2001-05-29 Seiko Epson Corp 半導体装置およびその製造方法
DE10157205A1 (de) 2001-11-22 2003-06-12 Fraunhofer Ges Forschung Kontakthöcker mit profilierter Oberflächenstruktur sowie Verfahren zur Herstellung
US7214569B2 (en) 2002-01-23 2007-05-08 Alien Technology Corporation Apparatus incorporating small-feature-size and large-feature-size components and method for making same
US7015590B2 (en) 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
DE102004006457A1 (de) * 2004-02-04 2005-08-25 Bielomatik Leuze Gmbh + Co Kg Verfahren und Vorrichtung zum kontinuierlichen Herstellen elektronischer Folienbauteile
DE102005012496B3 (de) * 2005-03-16 2006-10-26 Technische Universität Berlin Vorrichtung mit einem auf einem Montageteil montierten elektronischen Bauteil und Verfahren
US8102021B2 (en) * 2008-05-12 2012-01-24 Sychip Inc. RF devices
US8766450B2 (en) * 2009-09-22 2014-07-01 Samsung Electro-Mechanics Co., Ltd. Lead pin for package substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640052A (en) * 1993-03-10 1997-06-17 Nec Corporation Interconnection structure of electronic parts
JP2005197488A (ja) * 2004-01-08 2005-07-21 Sony Corp 突起電極及びボンディングキャピラリ並びに半導体チップ
JP2006310477A (ja) * 2005-04-27 2006-11-09 Akita Denshi Systems:Kk 半導体装置及びその製造方法
CN101295692A (zh) * 2007-04-06 2008-10-29 株式会社日立制作所 半导体装置

Also Published As

Publication number Publication date
MX2015001754A (es) 2015-09-16
DE102013215771A1 (de) 2014-02-13
BR112015002759B1 (pt) 2021-11-03
JP2015532780A (ja) 2015-11-12
KR20150053902A (ko) 2015-05-19
JP6347781B2 (ja) 2018-06-27
US10292270B2 (en) 2019-05-14
CN104737286A (zh) 2015-06-24
EP2883245A2 (de) 2015-06-17
DE102013215771B4 (de) 2019-06-13
MY172360A (en) 2019-11-21
WO2014023287A3 (de) 2014-04-03
MX349946B (es) 2017-08-22
CA2880408A1 (en) 2014-02-13
IN2015MN00491A (zh) 2015-09-04
US20150208508A1 (en) 2015-07-23
BR112015002759A2 (pt) 2017-07-04
EP2883245B1 (de) 2020-09-30
WO2014023287A2 (de) 2014-02-13

Similar Documents

Publication Publication Date Title
JP5039058B2 (ja) 半導体素子の実装構造体
US7109574B2 (en) Integrated circuit package with exposed die surfaces and auxiliary attachment
CN106169463B (zh) 形成电磁干扰屏蔽层的方法和用于所述方法的基带
CN105731354B (zh) 用于mems传感器器件的晶片级封装及对应制造工艺
EP2816590A2 (en) Semiconductor device with anchor means for the sealing resin
US20080064208A1 (en) System and method for increasing the strength of a bond made by a small diameter wire in ball bonding
CN106067457B (zh) 集成电路封装体及其制造方法与所使用的封装基板
US11408791B2 (en) Pressure sensor with a cap structured with an inner receiving section that prevents excessive spreading of a conductive adhesive
CN109801894A (zh) 芯片封装结构和封装方法
CN107564878B (zh) 凸点增强型封装结构
CN104737286B (zh) 接触凸块连接以及接触凸块和用于建立凸块接触连接的方法
CN105720019B (zh) 具有盖帽的图像感测装置和相关方法
WO2017106825A1 (en) Semiconductor package having a leadframe with multi-level assembly pads
US6700190B2 (en) Integrated circuit device with exposed upper and lower die surfaces
CN105489581B (zh) 半导体结构及其制作方法
CN207038516U (zh) 硅通孔芯片的二次封装体
US7732934B2 (en) Semiconductor device having conductive adhesive layer and method of fabricating the same
CN106653727A (zh) 用于封装集成电路的基板阵列
JP4915380B2 (ja) モールドパッケージの製造方法
JP6172058B2 (ja) 半導体装置の製造方法
JP4141450B2 (ja) 非接触データ伝送用のチップカードおよびその製造方法
CN108288608B (zh) 芯片封装体及其制备方法
TW201819090A (zh) 銲針
TWI744869B (zh) 封裝結構及其製造方法
JPH11204572A (ja) 半導体装置の実装構造体及びその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant