CN104716104B - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

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CN104716104B
CN104716104B CN201410452964.XA CN201410452964A CN104716104B CN 104716104 B CN104716104 B CN 104716104B CN 201410452964 A CN201410452964 A CN 201410452964A CN 104716104 B CN104716104 B CN 104716104B
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substrate
wiring layer
ground connection
semiconductor device
layer
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CN104716104A (zh
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涩谷克则
井本孝志
本间庄
本间庄一
渡部武志
高野勇佑
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

本发明提供一种能够谋求减少无用电磁波泄漏的半导体装置及其制造方法。实施方式的半导体装置包含包括上部及侧部的导电性屏蔽层，所述上部以覆盖密封树脂层的上表面的方式设置，所述侧部以覆盖密封树脂层的侧面及基板的侧面的方式设置。配线层的一部分包含露出于基板的侧面且沿着基板的厚度方向被切断的切断面。配线层的切断面中的接地配线的切断面与屏蔽层电连接。接地配线的切断面的面积大于与接地配线的切断面平行的接地配线的截面面积。

Description

半导体装置以及半导体装置的制造方法
[相关申请案]
本申请案享受以日本专利申请案2013-258493号(申请日：2013年12月13日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
本发明涉及一种半导体装置以及半导体装置的制造方法。
背景技术
例如，在用于移动通信设备的半导体装置中，为了防止对于通信特性造成的不良影响，而要求抑制无用电磁波向外部泄漏。因此，应用了具有屏蔽功能的半导体封装。作为具有屏蔽功能的半导体封装，有具有如下构造的半导体封装，即，沿着密封搭载在基板上的半导体芯片的密封树脂层的外表面设置着导电性屏蔽层。
发明内容
本发明提供一种能够谋求减少无用电磁波泄漏的半导体装置以及半导体装置的制造方法。
实施方式的半导体装置包括基板，该基板包括包含接地配线的配线层，且设置着焊垫电极。半导体装置包括半导体芯片，该半导体芯片搭载于所述基板。半导体装置包括接合线，该接合线将所述半导体芯片与所述焊垫电极电连接。半导体装置包括密封树脂层，该密封树脂层密封所述半导体芯片及所述接合线。半导体装置包括导电性屏蔽层，该导电性屏蔽层覆蓋所述基板的側面與所述密封樹脂層。
所述配线层的側面与所述屏蔽层电连接。所述接地配线包含一部分，该部分具有在所述基板的厚度方向比所述側面的面積小的截面積。
附图说明
图1是表示第一实施方式的半导体装置10的构成的一例的剖视图。
图2(a)及图2(b)是表示图1所示的半导体装置10的区域X附近的配线层的截面与切断面的一例的剖视图。
图3是表示图1所示的半导体装置10的制造方法的各步骤的一例的流程图。
图4(a)及图4(b)是表示切断基板2前的配线层的各截面的一例的剖视图。
图5(a)及图5(b)是表示切断基板2后的配线层的截面与切断面的一例的剖视图。
图6(a)及图6(b)是表示图1所示的半导体装置10的区域X附近的配线层的截面与切断面的另一例的剖视图。
图7(a)及图7(b)是表示切断基板2前的配线层的各截面的另一例的剖视图。
图8(a)及图8(b)是表示切断基板2后的配线层的截面与切断面的另一例的剖视图。
图9是表示配线层的切断面的SEM(Scanning Electron Microscope，扫描电子显微镜)图像的一例的图。
具体实施方式
下面，根据附图对实施方式进行说明。另外，在下面的实施方式中，有如下情况，即，基板的上下方向表示以设置半导体芯片一面为上方时的相对方向，不同于遵循重力加速度的上下方向。
而且，虽然在下面的实施方式中对应用于BGA(Ball Grid Array，球形阵列)的半导体装置(半导体封装)的一例进行说明，但也可以同样地适用于LGA(Land Grid Array，平台栅格阵列)。
[第一实施方式]
图1是表示第一实施方式的半导体装置10的构成的一例的剖视图。
如图1所示，半导体装置10包括基板2、外部连接端子3、半导体芯片1a～1h、11、接合线4a、4b、5a、5b、12、密封树脂层(模制树脂)6、以及导电性屏蔽层8。
基板2具有包含接地配线的配线层。该基板2在上表面设置着与配线层电连接的焊垫电极4a1、4b1、5a1、5b1、12a。进而，在基板2的上表面设置着配线层的信号配线或接地配线等(未图示)。
例如，如图1所示，该基板2的配线层包含第一配线层2a、第二配线层2b以及第三配线层2c。
第一配线层2a设置在基板2的上表面，并与各焊垫电极电连接。
第二配线层2b设置在基板2的下表面。
第三配线层2c设置在第一配线层2a与第二配线层2b之间。并且，该第三配线层2c的一部分(端部)具有露出于基板2的侧面且沿着基板2的厚度方向被切断的切断面。另外，如后文所述，该第三配线层2c的切断面为利用切割锯切断基板2所得之面的一部分。
另外，在图1的例中，接地配线设置在该第三配线层2c上。该接地配线例如使用金属材料。并且，该金属材料例如使用金、银、铜、铝、镍、钯、钨中的任一种。
而且，基板2进而具有第一绝缘层9a及第二绝缘层9b。
第一绝缘层9a设置在第一配线层2a与第三配线层2c之间。
并且，第二绝缘层9b设置在第二配线层2b与第三配线层2c之间。
而且，基板2以将各配线层2a、2b、2c电连接的方式设置着贯通基板2的通孔15。通孔15具有：导体层13，形成在贯通基板2的贯通孔的内表面；以及填孔材料14，填充在导体层13的内侧的中空部。
半导体芯片1a～1h搭载在基板2的上表面。
此处，例如，如图1所示，半导体芯片1a～1h依序堆叠在基板2的上表面。位于最下方的半导体芯片1a隔着阻焊层(未图示)而配置在基板2的上表面。
并且，半导体芯片1a～1e利用接合线4a、5a而与焊垫电极4a1、5a1电连接。而且，半导体芯片1f～1h利用接合线4b、5b而与焊垫电极4b1、5b1电连接。
这些半导体芯片1a～1h例如为NAND(NotAND，与非)型闪速存储器。
而且，半导体芯片11隔着阻焊层(未图示)而配置在基板2的上表面。并且，半导体芯片11利用接合线12而与焊垫电极12a电连接。
该半导体芯片11例如为NAND型闪速存储器的控制器。
而且，密封树脂层6以密封半导体芯片1a～1h、11及接合线4a、4b、5a、5b、12的方式设置在基板2的上表面上。
在该密封树脂层6的上表面形成着凹部7。
而且，在该密封树脂层6的表面设置着屏蔽层8。屏蔽层8具有导电性。例如，如图1所示，该屏蔽层8具有：上部8，以覆盖密封树脂层6的上表面的方式设置；以及侧部8b、8c，以覆盖密封树脂层6的侧面及基板2的侧面的方式设置。
并且，所述第三配线层2c的切断面中的接地配线的切断面与该屏蔽层8的侧部8c电连接。
而且，屏蔽层8在上部8a形成着识别标记M，该识别标记M具有对应于密封树脂层6的凹部7而凹陷的形状。
此处，由于从半导体芯片1a～1h、11或基板2的配线层放射出的无用电磁波的至少一部分被覆盖密封树脂层6及基板2的侧面的屏蔽层8遮断，因此无用电磁波向外部泄漏的情况得到抑制。
就抑制从密封树脂层6内的半导体芯片1a～1h、11或基板2的配线层放射出的无用电磁波的泄漏的方面来看，此种屏蔽层8优选由低电阻率的金属层形成。因此，屏蔽层8选择例如包含铜、银或镍的金属层。
而且，外部连接端子3设置在基板2的下表面，并与基板2的配线层(第二配线层2b)电连接。该外部连接端子3例如为焊球。
另外，所述第三配线层2c的接地配线是通过该外部连接端子3而与半导体装置10的外部的接地电连接。
由此，可将无用电磁波传送至接地而抑制无用电磁波的泄漏。
此处，图2是表示图1所示的半导体装置10的区域X附近的配线层的截面与切断面的一例的剖视图。另外，图2(a)是表示图1的区域X附近的剖视图。而且，图2(b)是图1的区域X的基板2与屏蔽层8的侧部8c的交界处的从屏蔽层8的侧部8c观察的剖视图。而且，在图2(b)中，配置着两个接地配线GND，但也可以配置大于等于3个，而且，也可以只配置一个宽幅的接地配线GND。
如图2所示，第三配线层2c(接地配线GND)的一部分(端部)具有露出于基板2的侧面且沿着基板2的厚度方向被切断的切断面2c1。并且，该接地配线GND的切断面与屏蔽层8的侧部8c连接(图2(a))。也就是说，屏蔽层8与接地配线GND经由接地配线GND的切断面2c1而电连接。
并且，接地配线GND的切断面的面积大于与接地配线GND的切断面(屏蔽层8的侧部8c的内表面)平行的接地配线GND的截面面积(图2(a)、图2(b))。因此，可提高屏蔽层8与接地配线GND的连接状态。也就是说，可使屏蔽层8与接地配线GND的接触电阻降低。由此，可进一步减少无用电磁波的泄漏。
接下来，对具有如上构成的半导体装置10的制造方法的一例进行说明。图3是表示图1所示的半导体装置10的制造方法的各步骤的一例的流程图。而且，图4是表示切断基板2前的配线层的各截面的一例的剖视图。而且，图5是表示切断基板2后的配线层的截面及切断面的一例的剖视图。另外，图4(a)、图5(a)表示所述图2(a)所示的配线层的区域所对应的区域。而且，图4(b)、图5(b)表示所述图2(b)所示的配线层的区域所对应的区域。
如图3所示，首先，制造包含复数个基板2的集合基板，该基板2具有包含接地配线的配线层且在其上表面设置着焊垫电极(步骤101)。
接着，在各基板2上搭载半导体元件(步骤102)。
也就是说，在基板2上搭载半导体芯片11。接着，利用接合线12而将半导体芯片11与焊垫电极12a电连接。其后，搭载(装载)半导体芯片1a～1d。接着，利用接合线4a、5a而将半导体芯片1a～1d与焊垫电极4a1、5a1电连接。其后，搭载(装载)半导体芯片1e～1h。接着，利用接合线4b、5b而将半导体芯片1e～1h与焊垫电极4b1、5b1电连接。
接着，利用密封树脂层(模制树脂)6密封各基板上的半导体元件(步骤103)。也就是说，以密封半导体芯片1a～1h、11及接合线4a、4b、5a、5b、12的方式在各基板2的上表面上形成密封树脂层6。
接着，利用切割锯一并切断各基板2及配线层，由此分离成各个半导体装置(半导体封装)10(步骤104)。
此处，如图5所示，被切割锯切断而形成的第三配线层2c(接地配线GND)的切断面2c1的面积变得大于切断前的接地配线GND的截面面积(图4)。
为了以面积大于切断前的接地配线GND的截面面积的方式利用切割锯以切断设置配线GND，除了可通过调整切断刀片的研磨粒的尺寸或刀片的宽度、刀片的材质来实现以外，也可以通过调整切断速度或切断所需的次数(一次性切断或进行两个步骤以上的分段切断)等切断条件来实现。
接着，利用激光照射对密封树脂层6的上表面进行标记(形成凹部7)(步骤105)。
接着，通过金属镀敷等形成屏蔽层8(步骤106)。
也就是说，例如，应用由无电电镀法或电镀法成膜铜或镍等的方法、由溅镀法成膜铜等的方法，以覆盖密封树脂层6的上表面且覆盖密封树脂层6的侧面及基板2的侧面的方式形成导电性屏蔽层8。并且，在该屏蔽层8的上部8a具有对应于密封树脂层6的上表面的凹部7而凹陷的识别标记M。
此处，如上所述，该接地配线GND的切断面2c1的面积变得大于与接地配线GND的切断面(屏蔽层8的侧部8c的内表面)平行的接地配线GND的截面面积(图5(a)、图5(b))。
因此，可提高屏蔽层8与接地配线GND的连接状态。也就是说，可使屏蔽层8与接地配线GND的接触电阻降低。由此，可进一步减少无用电磁波的泄漏。
另外，屏蔽层8例如也可以通过利用转印法、网版印刷法、喷雾涂布法、喷射点胶法、喷墨法、气溶胶法等涂布导电膏而形成。在此情况下，导电膏例如包含银或铜及树脂作为主成分，较理想为低电阻率。
如上所述，根据本实施方式的半导体装置，可谋求减少无用电磁波的泄漏。
[第二实施方式]
在所述第一实施方式中，对配线层的接地配线仅由主配线构成的情况的一例进行了说明。
在本第二实施方式中，对配线层的接地配线还包括围绕主配线且具有高耐氧化性的保护金属膜的构成的一例进行说明。另外，该第二实施方式的半导体装置的整体构成与图1所示的第一实施方式的半导体装置10相同。而且，第二实施方式的半导体装置的制造方法的步骤与图3所示的步骤相同。
此处，图6是表示图1所示的半导体装置10的区域X附近的配线层的截面与切断面的另一例的剖视图。
如图6所示，第三配线层2c中所含的接地配线GND具有主配线2cx及保护金属膜2cy。
主配线2cx使用第一金属材料。该第一金属材料例如选自银、铜、铝、钨中的任一种。
保护金属膜2cy以覆盖主配线2cx的方式设置。保护金属膜2cy尤其覆盖主配线2cx的上表面及侧面。
该保护金属膜2cy使用耐氧化性高于第一金属材料的第二金属材料。该第二金属材料例如选自金、镍、钛、钯、铂中的任一种。
此处，在第三配线层2c(接地配线GND)的切断面2c1中，主配线2cx的切断面2cx1被保护金属膜2cy覆盖(图6(a))。也就是说，主配线2cx的切断面2cx1经由保护金属膜2cy而与屏蔽层8的侧部8c电连接。
另外，如上所述，该第三配线层2c的切断面为利用切割锯切断基板2所得一面的一部分。保护金属膜2cy在利用切割锯加以切断时被拉长，而如图6所示那样覆盖主配线2cx的切断面2cx1。
接下来，对具有如上构成的半导体装置10的制造方法的一例进行说明。图7是表示切断基板2前的配线层的各截面的另一例的剖视图。而且，图8是表示切断基板2后的配线层的截面与切断面的另一例的剖视图。另外，图7(a)、图8(a)表示所述图2(a)所示的配线层的区域所对应的区域。而且，图7(b)、图8(b)表示所述图2(b)所示的配线层的区域所对应的区域。
如所述图3所示，与第一实施方式同样地实施步骤101～103。
接着，利用切割锯一并切断各基板2及配线层，由此分离成各个半导体装置(半导体封装)10(步骤104)。
此处，如图8所示，通过被切割锯切断而形成的第三配线层2c(接地配线GND)的切断面2c1的面积变得大于切断前的接地配线GND的截面面积(图7)。
并且，保护金属膜2cy在利用切割锯加以切断时被拉长，而如图8所示那样覆盖主配线2cx的切断面2cx1。也就是说，成为由切割锯而形成的主配线2cx的截面被高耐氧化性的金属材料覆盖的状态。
此处，图9是表示配线层的切断面的SEM图像的一例的图。另外，在该图9中，构成主配线2cx的第一金属材料为Cu，构成保护金属层2cy的第二金属材料为Ni。
如图9所示，成为由切割锯而形成的主配线2cx的截面被高耐氧化性的保护金属层2cy覆盖的状态。
这样一来，可以防止在切晶后到形成屏蔽层8的期间，由切割锯而形成的主配线2cx的截面腐蚀(氧化)。
接着，利用激光照射对密封树脂层6的上表面进行标记(形成凹部7)(步骤105)。
接着，利用金属镀敷等而形成屏蔽层8(步骤106)。
也就是说，例如，应用由无电电镀法或电镀法成膜铜或镍等的方法、由溅镀法成膜铜等的方法，以覆盖密封树脂层6的上表面且覆盖密封树脂层6的侧面及基板2的侧面的方式形成导电性屏蔽层8。并且，在该屏蔽层8的上部8a具有对应于密封树脂层6的上表面的凹部7而凹陷的识别标记M。
此处，如上所述，该接地配线GND的切断面的面积变得大于与接地配线GND的切断面(屏蔽层8的侧部8c的内表面)平行的接地配线GND的截面2c1面积(图8(a)、图8(b))。
因此，可以提高屏蔽层8与接地配线GND的连接状态。也就是说，可使屏蔽层8与接地配线GND的接触电阻降低。由此，可进一步减少无用电磁波的泄漏。
如上所述，根据本实施方式的半导体装置，可谋求减少无用电磁波的泄漏。
另外，在所述实施方式中，尤其在图1中着眼于配线层2的接地配线与屏蔽层8的侧部8c的电连接进行了说明。
但是，在图1中，也同样地说明配线层2的接地配线与屏蔽层8的相反侧的侧部8b电连接的情况。进而，也同样地说明配线层2的接地配线与平行于图1的纸面的屏蔽层8的两个侧部(未图示)电连接的情况。
虽然对本发明的一些实施方式进行了说明，但这些实施方式是作为示例而提出的，并非意欲限定发明的范围。这些实施方式能以其他各种方式加以实施，且可在不脱离发明的主旨的范围内进行各种省略、替换、变更。这些实施方式或其变形包含在发明的范围或主旨中，同样地包含在权利要求所记载的发明及其均等的范围内。
[符号的说明]
1a～1h、11 半导体芯片
2 基板
2a 第一配线层
2b 第二配线层
2c 第三配线层
3 外部连接端子
4a、4b、5a、5b、12 接合线
4a1、4b1、5a1、5b1、12a 焊垫电极
6 密封树脂层
7 凹部
8 屏蔽层
9a 第一绝缘层
9b 第二绝缘层
10 半导体装置

Claims (6)

1.一种半导体装置，其特征在于包括：
基板，包括包含接地配线的配线层，且设置着焊垫电极；
半导体芯片，搭载在所述基板；
外部连接端子，设置在所述基板；
接合线，将所述半导体芯片与所述焊垫电极电连接；
密封树脂层，密封所述半导体芯片及所述接合线；以及
导电性屏蔽层，覆盖所述基板的侧面与所述密封树脂层；
所述配线层的侧面与所述屏蔽层电连接，
所述接地配线包含一部分，该部分具有在所述基板的厚度方向比所述侧面的面积小的截面积；
所述接地配线包含：
主配线，使用第一金属材料；以及
保护金属膜，使用耐氧化性高于所述第一金属材料的第二金属材料，并覆盖所述主配线；并且
在所述接地配线的所述侧面中，所述主配线的侧面被所述保护金属膜覆盖。
2.根据权利要求1所述的半导体装置，其特征在于：
所述主配线的所述侧面经由所述保护金属膜而与所述屏蔽层电连接。
3.根据权利要求1所述的半导体装置，其特征在于：
所述保护金属膜覆盖所述主配线的上表面及侧面。
4.根据权利要求1所述的半导体装置，其特征在于：
所述接地配线与所述半导体装置的外部的接地电连接。
5.根据权利要求1所述的半导体装置，其特征在于：
所述配线层包含：
第一配线层，设置在所述基板的上表面，并与所述焊垫电极电连接；
第二配线层，设置在所述基板的下表面；以及
第三配线层，设置在所述第一配线层与所述第二配线层之间；并且
所述接地配线设置在所述第三配线层。
6.一种半导体装置的制造方法，其特征在于：
在基板上搭载半导体芯片，该基板包括包含接地配线的配线层且设置着焊垫电极，
利用接合线将所述半导体芯片与所述焊垫电极电连接，
形成密封所述半导体芯片及所述接合线的密封树脂层，
利用切割锯一并切断所述基板及所述配线层，
形成覆盖所述基板的侧面與所述密封树脂层的导电性屏蔽层，
所述配线层的侧面与所述屏蔽层电连接，
所述接地配线包含一部分，该部分具有在所述基板的厚度方向比所述侧面的面积小的截面积；
所述接地配线包含：
主配线，使用第一金属材料；以及
保护金属膜，使用耐氧化性高于所述第一金属材料的第二金属材料，并覆盖所述主配线；并且
在所述接地配线的所述侧面中，所述主配线的侧面被所述保护金属膜覆盖。
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