CN208706644U - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN208706644U
CN208706644U CN201821258040.6U CN201821258040U CN208706644U CN 208706644 U CN208706644 U CN 208706644U CN 201821258040 U CN201821258040 U CN 201821258040U CN 208706644 U CN208706644 U CN 208706644U
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Prior art keywords
substrate
layer
wiring layer
ground connection
semiconductor device
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CN201821258040.6U
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Inventor
佐野雄
佐野雄一
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Kioxia Corp
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Toshiba Memory Corp
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Abstract

实施方式提供一种能够抑制在封装内部产生的电磁波噪音泄漏的半导体装置。本实施方式的半导体装置具备衬底。半导体芯片搭载在衬底上。第1与第2接地配线设置在衬底的内部。密封树脂层以将半导体芯片密封的方式设置在衬底上。导电性的屏蔽层设置在密封树脂层的上表面、密封树脂层的侧面、及衬底的侧面，且在衬底的侧面连接于第1与第2接地配线。第1与第2接地配线通过在与屏蔽层的接触面附近展开而相互连接。

Description

半导体装置
[相关实用新型]
本实用新型享有以日本专利申请2018-48308号(申请日：2018年3月15日)作为基础实用新型的优先权。本实用新型通过参照该基础实用新型而包含基础实用新型的全部内容。
技术领域
本实施方式涉及一种半导体装置。
背景技术
有在半导体封装的上表面或侧面设置着屏蔽层的情况。该屏蔽层是为了抑制在半导体封装内部产生的电磁波噪音向外部漏出而经由设置在安装衬底的接地配线接地。然而，期望进一步减少电磁波噪音的泄漏。
实用新型内容
实施方式提供一种能够抑制在封装内部产生的电磁波噪音泄漏的半导体装置。
本实施方式的半导体装置具备衬底。半导体芯片搭载在衬底上。第1与第2接地配线设置在衬底的内部。密封树脂层以将半导体芯片密封的方式设置在衬底上。导电性的屏蔽层设置在密封树脂层的上表面、密封树脂层的侧面、及衬底的侧面，且在衬底的侧面连接于第1与第2接地配线。第1与第2接地配线通过在与屏蔽层的接触面附近展开而相互连接。
此外，较理想的是第1与第2接地配线彼此在衬底的侧面与所述屏蔽层之间相互连接。
另外，较理想的是第1与第2接地配线与屏蔽层的接触面积在衬底内的与衬底的侧面大致平行的截面中，大于第1与第2接地配线的截面面积的和。
另外，较理想的是第1与第2接地配线间的间隔为衬底的侧面中的接地配线的扩展宽度的2倍以下。
另外，较理想的是第1与第2接地配线在衬底的侧面沿相对于衬底的上表面大致平行的方向排列，且相互连接。
另外，较理想的是第1与第2接地配线在衬底的侧面沿相对于衬底的上表面大致垂直的方向排列，且相互连接。
附图说明
图1是表示第1实施方式的半导体装置的构成的一例的剖视图。
图2是图1所示的安装衬底的侧面中的配线层的剖视图。
图3是表示第2实施方式的半导体装置的构成例的剖视图。
图4是表示按照变化例而得的半导体装置的构成例的剖视图。
具体实施方式
以下，参照附图对本实用新型的实施方式进行说明。本实施方式并不限定本实用新型。在以下的实施方式中，安装衬底的上下方向表示将供设置半导体芯片的面设为上时的相对方向，有时与按照重力加速度所得的上下方向不同。
在以下的实施方式中，对应用于BGA(Ball Grid Array，球状栅格阵列)的半导体装置(半导体封装)的一例进行说明，但对于LGA(Land Grid Array，焊盘网格阵列)也能同样地应用。
(第1实施方式)
图1是表示第1实施方式的半导体装置10的构成的一例的剖视图。半导体装置10具备安装衬底2、外部连接端子3、半导体芯片1a～1h、11、接合线4a、4b、5a、5b、12、密封树脂层6、以及屏蔽层8。
安装衬底2具有嵌埋到绝缘材料内的多层配线层。安装衬底2也被简称为衬底。绝缘材料例如包含绝缘层9a、9b。绝缘层9a、9b例如使用玻璃环氧树脂等绝缘材料。多层配线层例如包含配线层2a、2b、2c。配线层2a、2b、2c例如使用金、银、铜、铝、镍、钯、钨等导电性金属。而且，在安装衬底2的上表面设置着与配线层2a、2b、2c电连接的焊垫电极Pa、Pb。焊垫电极Pa、Pb经由接合线4a、4b、5a、5b电连接于半导体芯片1a～1h。在安装衬底2的背面，例如设置着焊料凸块3。焊料凸块3与未图示的其它半导体装置电连接。
配线层2c设置在配线层2a与配线层2b之间。配线层2c的一端在安装衬底2的侧面露出，且具有在安装衬底2的厚度方向(Z方向)上被切断所得的切断面。配线层2c的切断面是利用切割刀片切断所得的面。配线层2c被设置成接地配线，电连接于地面。
而且，为了将配线层2a、2b、2c中的任一配线层在配线层间电连接，安装衬底2具有贯通安装衬底2的通孔15。通孔15具有：导体层13，形成在贯通安装衬底2的贯通孔的内表面；以及填孔材14，填充在导体层13内侧的中空部。
半导体芯片1a～1h、11设置在安装衬底2的上表面上。半导体芯片11通过例如DAF(Die Attachment Film，芯片贴膜)(未图示)等而粘接在安装衬底2的上表面上。半导体芯片11经由接合线12与焊垫电极12a电连接。半导体芯片11例如为NAND(Not-AND，与非)型EEPROM(Electrically Erasable Programmable Read Only Memory，电可擦除可编程只读存储器)的控制器。半导体芯片11由树脂层16被覆。
半导体芯片1a～1h设置在半导体芯片11的上方，且积层在树脂层16上。半导体芯片1a～1h通过DAF而粘接在树脂层16上或其它半导体芯片1a～1g上。半导体芯片1a～1h例如为NAND型EEPROM芯片。
半导体芯片1a～1e通过接合线4a、5a与焊垫电极Pa电连接。而且，半导体芯片1f～1h通过接合线4b、5b与焊垫电极Pb电连接。
密封树脂层6以被覆半导体芯片1a～1h、11及接合线4a、4b、5a、5b、12的方式，设置在安装衬底2的上表面上。
屏蔽层8以被覆密封树脂层6的上表面、密封树脂层6的侧面、及安装衬底2的侧面的方式设置。屏蔽层8也设置在安装衬底2的侧面，且连接于配线层2c。
设置屏蔽层8的理由如下所述。从半导体芯片1a～1h、11及安装衬底2的配线层会放射电磁波。该电磁波有对半导体装置10外部的设备造成不良影响之虞。因此，设置覆盖密封树脂层6及安装衬底2的侧面的屏蔽层8。屏蔽层8将来自半导体装置10内部的电磁波阻断。由此，抑制来自半导体芯片1a～1h、11及安装衬底2的配线层的电磁波向外部泄漏。
为了有效地发挥这种电磁波屏蔽功能，屏蔽层8优选为由电阻率较低的金属层形成。例如，屏蔽层8使用铜、银、镍、不锈钢(SUS)等导电性金属或这些金属中的任意多种材料的积层膜。
外部连接端子3设置在安装衬底2的下表面，与安装衬底2的配线层2b电连接。外部连接端子3例如为焊料球。此外，作为接地配线的配线层2c经由外部连接端子3而与半导体装置10外部的地面电连接。
利用这种构成，半导体装置10能够将电磁波向地面传输，从而抑制电磁波向半导体装置10的封装外部泄漏。
图2是图1所示的安装衬底2的侧面中的配线层2c的剖视图。图2的左侧是图1的安装衬底2的侧面附近的圆C的放大剖视图。图2的右侧是沿着左侧的B-B线的剖视图。也就是说，图2的右侧表示已将屏蔽层8去除时的安装衬底2的侧面，且是从图1的X方向观察到的剖视图。此外，图2的右侧中，以实线Ls表示已将屏蔽层8去除时露出到安装衬底2的侧面的配线层2c，以虚线Lb表示安装衬底2内部的配线层2c。所谓安装衬底2的内部，是指图2的左侧的由绝缘层9a及9b夹着的区域。
如图2的左侧所示，将露出到安装衬底2的侧面F2的配线层2c的侧面设为F2c。配线层2c的侧面F2c相比安装衬底2内部的配线层2c来说变宽。因此，如图2的右侧所示，配线层2c的侧面F2c的面积(由Ls包围的区域的面积)大于安装衬底2内部的配线层2c的面积(由Lb包围的区域的面积的和)。这是因为，当安装衬底2被切割刀片切断时，配线层2c与切割刀片接触而延伸。
而且，如图2的右侧所示，多个配线层2c在安装衬底2的侧面F2中，排列在同一配线层内。也就是说，多个配线层2c在安装衬底2内沿Y方向排列。进而，换句话说，多个配线层2c在安装衬底2的侧面F2中沿相对于安装衬底2的上表面Ft大致平行的方向排列。多个配线层2c是接地配线，能够电连接于地面。此外，在图2的右侧示出了2个配线层2c，但也可以排列3个以上的配线层2c。而且，配线层2c由于为接地配线，所以即使相互短路也不存在问题。
如图2的右侧的虚线Lb所示，多个配线层2c在安装衬底2的内部相互分离。然而，如实线Ls所示，多个配线层2c在与安装衬底2的侧面F2大致同一面的侧面F2c沿Y方向扩展而相互连接。也就是说，相邻的多个配线层2c彼此在安装衬底2的侧面与屏蔽层8之间的接触面附近相互短路且连接。该情况下，在安装衬底2内的与安装衬底2的侧面F2大致平行的截面中，多个配线层2c与屏蔽层8的接触面积(由实线Ls包围的区域的面积)变得大于多个配线层2c的截面面积的和(由虚线Lb包围的区域的面积的和)。
由此，配线层2c与屏蔽层8的接触面积变大，而能够提高两者的连接状态。也就是说，能使屏蔽层8与配线层(接地配线)2c的接触电阻降低。其结果为，半导体装置10可使大部分电磁波向地面释放，从而减少电磁波向半导体装置10外部的泄漏。而且，通过使相邻的多个配线层2c在安装衬底2的侧面F2扩展并连接，可使配线层2c本身具有电磁屏蔽效果。其结果为，半导体装置10能够进一步减少电磁波的泄漏。
随着半导体封装的微细化，安装衬底2也被微细化。因此，相邻的多个配线层2c的间隔D2c变窄，而存在如下情况：当利用切割刀片将安装衬底2切断时，相邻的多个配线层2c自然地连接。这样一来，为了通过切割使多个配线层2c自行对准地连接，优选为相邻的配线层2c彼此的间隔D2c是安装衬底2的侧面F2中的配线层2c的扩展宽度EXT2c的2倍以下。由此，在切割后，多个配线层2c在安装衬底2的侧面F2扩展而可自行对准地连接。
(第2实施方式)
图3是表示第2实施方式的半导体装置10的构成例的剖视图。图3的左侧是图1的安装衬底2的侧面附近的圆C的放大剖视图。图3的右侧是沿着左侧的B-B线的剖视图。也就是说，图3的右侧表示已将屏蔽层8去除时的安装衬底2的侧面，且是从图1的X方向观察到的剖视图。此外，在图3的右侧，以实线Ls表示已将屏蔽层8去除时露出到安装衬底2的侧面的配线层2c，以虚线Lb表示安装衬底2内部的配线层2c。
第2实施方式与第1实施方式的不同点在于：多个配线层2c沿纵向(Z方向)排列。第2实施方式的半导体装置10的其它构成可与第1实施方式的半导体装置10的对应构成相同。
与第1实施方式同样地，配线层2c的侧面F2c相比安装衬底2内部的配线层2c来说变宽。因此，配线层2c的侧面F2c的面积(由Ls包围的区域的面积)大于安装衬底2内部的配线层2c的面积(由Lb包围的区域的面积的和)。
而且，如图3的右侧所示，多个配线层2c是在安装衬底2的侧面F2作为不同的配线层沿纵向排列。也就是说，多个配线层2c在安装衬底2内沿Z方向排列。进而，换句话说，多个配线层2c在安装衬底2的侧面F2沿相对于安装衬底2的上表面Ft大致垂直的方向排列。多个配线层2c是接地配线，能够电连接于地面。
如图3的右侧的虚线Lb所示，多个配线层2c在安装衬底2内相互分离。然而，如实线Ls所示，多个配线层2c在与安装衬底2的侧面F2大致同一面的侧面F2c中也沿Z方向扩展而相互连接。也就是说，相邻的多个配线层2c彼此在安装衬底2的侧面与屏蔽层8之间的接触面附近相互短路且连接。该情况下，在安装衬底2内的与安装衬底2的侧面F2大致平行的截面中，多个配线层2c与屏蔽层8的接触面积(由实线Ls包围的区域的面积)变得大于多个配线层2c的截面面积的和(由虚线Lb包围的区域的面积的和)。
由此，配线层2c与屏蔽层8的接触面积变大，而能够提高两者的连接状态。也就是说，能使屏蔽层8与配线层(接地配线)2c的接触电阻降低。其结果为，半导体装置10可使大部分电磁波向地面释放，从而减少电磁波向半导体装置10外部的泄漏。而且，通过使相邻的多个配线层2c在安装衬底2的侧面F2扩展并连接，可使配线层2c本身具有电磁屏蔽效果。其结果为，半导体装置10能够进一步减少电磁波的泄漏。
为了通过切割使多个配线层2c自行对准地连接，优选为在Z方向上相邻的配线层2c彼此的间隔D2c是安装衬底2的侧面F2中的配线层2c的扩展宽度EXT2c的2倍以下。由此，在切割后，多个配线层2c在安装衬底2的侧面F2扩展而可自行对准地连接。
(变化例)
图4是表示按照变化例而得的半导体装置10的构成例的剖视图。本变化例是第1实施方式与第2实施方式的组合。本变化例中，多个配线层2c在安装衬底2的侧面F2分别沿相对于安装衬底2的上表面Ft大致平行的方向及大致垂直的方向排列。也就是说，多个配线层2c在安装衬底2的侧面F2设置在同一配线层及不同的配线层。并且，多个配线层2c在大致平行方向及大致垂直方向上相互连接。
这样一来，也可以使在侧面F2内(沿Z方向及Y方向)排列的多个配线层2c相互连接。由此，配线层2c与屏蔽层8的接触面积变大，而能够提高两者的连接状态。其结果为，半导体装置10可使大部分电磁波向地面释放，从而减少电磁波向半导体装置10外部的泄漏。而且，通过使相邻的多个配线层2c在安装衬底2的侧面F2扩展并连接，可使配线层2c本身具有电磁屏蔽效果。
此外，在图4中示出了4条配线，但也可以将5条以上的配线二维配置在侧面F2内。由此，也能以配线层2c的金属覆盖安装衬底2的侧面F2整体。其结果为，半导体装置10能够进一步减少电磁波的泄漏。
已对本实用新型的若干个实施方式进行了说明，但这些实施方式是作为示例而提出的，并非意图限定实用新型的范围。这些实施方式能以其它各种方式实施，且能够在不脱离实用新型主旨的范围内进行各种省略、替换、变更。这些实施方式或其变化包含在实用新型的范围或主旨中，同样地包含在权利要求书所记载的实用新型及其均等的范围内。
符号的说明
10 半导体装置
2 安装衬底
3 外部连接端子
1a～1h、11 半导体芯片
4a、4b、5a、5b、12 接合线
6 密封树脂层
8 屏蔽层

Claims (6)

1.一种半导体装置，其特征在于具备：
衬底；
半导体芯片，搭载在所述衬底上；
第1与第2接地配线，设置在所述衬底的内部；
密封树脂层，以将所述半导体芯片密封的方式设置在所述衬底上；以及
导电性的屏蔽层，设置在所述密封树脂层的上表面、所述密封树脂层的侧面、及所述衬底的侧面，且在所述衬底的侧面连接于所述第1与第2接地配线；且
所述第1与第2接地配线通过在与所述屏蔽层的接触面附近展开而相互连接。
2.根据权利要求1所述的半导体装置，其特征在于所述第1与第2接地配线彼此在所述衬底的侧面与所述屏蔽层之间相互连接。
3.根据权利要求1或2所述的半导体装置，其特征在于所述第1与第2接地配线与所述屏蔽层的接触面积在所述衬底内的与所述衬底的侧面大致平行的截面中，大于所述第1与第2接地配线的截面面积的和。
4.根据权利要求1或2所述的半导体装置，其特征在于所述第1与第2接地配线间的间隔为所述衬底的侧面中的所述第1与第2接地配线的扩展宽度的2倍以下。
5.根据权利要求1或2所述的半导体装置，其特征在于所述第1与第2接地配线在所述衬底的侧面沿相对于所述衬底的上表面大致平行的方向排列，且相互连接。
6.根据权利要求1或2所述的半导体装置，其特征在于所述第1与第2接地配线在所述衬底的侧面沿相对于所述衬底的上表面大致垂直的方向排列，且相互连接。
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