CN104681493A - 半导体结构的形成方法 - Google Patents

半导体结构的形成方法 Download PDF

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CN104681493A
CN104681493A CN201310617911.4A CN201310617911A CN104681493A CN 104681493 A CN104681493 A CN 104681493A CN 201310617911 A CN201310617911 A CN 201310617911A CN 104681493 A CN104681493 A CN 104681493A
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layer
isolation structure
device layer
glossing
formation method
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CN104681493B (zh
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王新鹏
宁先捷
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Corp
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Abstract

一种半导体结构的形成方法,包括:提供衬底,所述衬底内具有若干隔离结构,所述隔离结构的表面高于所述衬底的表面;在所述衬底和隔离结构表面形成器件层;对所述器件层进行抛光工艺,直至暴露出隔离结构表面为止,所述抛光工艺对于器件层和隔离结构的抛光速率相同;在所述抛光工艺之后,采用干法处理工艺去除所述器件层和隔离结构表面的残余物质。所形成的半导体结构的形貌良好、性能稳定。

Description

半导体结构的形成方法
技术领域
本发明涉及半导体制造技术领域,尤其涉及一种半导体结构的形成方法。
背景技术
在目前的半导体产业中,集成电路产品主要可分为三大类型:模拟电路、数字电路和数/模混合电路,其中存储器件是数字电路中的一种重要器件类型。近年来,存储器件中的闪存(flash memory)发展尤为迅速。闪存的主要特点是在不加电的情况下能长期保持存储的信息;且闪存具有集成度高、存取速度快、易于擦除和重写等优点,因而在微机、自动化控制等多项领域得到了广泛的应用。
图1是现有技术的一种闪存存储单元的剖面结构示意图,包括:衬底10;位于所述衬底10表面的隧穿氧化层11;位于隧穿氧化层11表面的浮栅12,所述隧穿氧化层11和浮栅12内具有暴露出衬底10的开口(未标识);位于所述浮栅12顶部表面、且覆盖所述开口侧壁的侧墙13;位于所述开口底部衬底10表面的源线层14,所述源线层14覆盖侧墙13的部分表面,且所述源线层14的表面不高于所述侧墙13的顶部;位于侧墙13、源线层14和浮栅12外侧的字线层15,所述字线层15与浮栅12之间通过绝缘层16电隔离。
形成于同一衬底上的若干闪存存储单元的浮栅需要由隔离结构进行电隔离,图2是隔离闪存存储单元浮栅的隔离结构的示意图,包括:衬底20,所述衬底20具有浮栅区21和隔离区22;位于浮栅区21的衬底20表面的隧穿氧化层25、以及位于隧穿氧化层25表面的浮栅层23;位于隔离区22的衬底20内的隔离结构24,所述隔离结构24具有相邻的第一区域A和第二区域B,如图1所示的源线层14横跨隔离结构24的第一区域A,而与隔离结构24的第二区域B相对应的部分浮栅层23在后续工艺中被刻蚀去除。
然而,现有技术所形成的浮栅层和隔离结构的形貌不良,使得所形成的闪存存储单元的性能不稳定。
发明内容
本发明解决的问题是提供一种半导体结构的形成方法,提高所形成的器件层和隔离层的形貌,使所形成的半导体结构的性能稳定。
为解决上述问题,本发明提供一种半导体结构的形成方法,包括:提供衬底,所述衬底内具有若干隔离结构,所述隔离结构的表面高于所述衬底的表面;在所述衬底和隔离结构表面形成器件层;对所述器件层进行抛光工艺,直至暴露出隔离结构表面为止,所述抛光工艺对于器件层和隔离结构的抛光速率相同;在所述抛光工艺之后,采用干法处理工艺去除所述器件层和隔离结构表面的残余物质。
可选的,所述隔离结构的材料为氧化硅、氮化硅或氮氧化硅,所述器件层的材料为多晶硅。
可选的,所述干法处理工艺的气体包括含氟气体,所述干法处理工艺对于器件层和隔离结构的刻蚀速率相同。
可选的,所述干法处理的气体包括Ar、He、CF4、CHF3,所述Ar的流量为100sccm~800sccm,He的流量为50sccm~200sccm,CF4的流量为20sccm~300sccm,CHF3的流量为10sccm~200sccm。
可选的,所述干法处理工艺减薄器件层和隔离结构的厚度,减薄后的器件层和隔离结构表面相对于减薄前降低30埃~80埃。
可选的,所述残余物质包括硅材料。
可选的,所述器件层作为浮栅,所述浮栅用于构成闪存存储单元。
可选的,还包括:在所述干法处理工艺之后,在所述器件层表面形成第一介质层;在所述第一介质层表面形成控制栅、字线层或源线层。
可选的,还包括:在所述干法处理工艺之后,采用热氧化工艺在所述器件层和隔离结构表面形成氧化层;在所述氧化工艺之后,去除所述氧化层。
可选的,去除所述氧化层的工艺为湿法清洗工艺。
可选的,在所述湿法清洗工艺之后,在所述干法处理工艺之后,在所述器件层表面形成第一介质层。
可选的,所述第一介质层包括:第一氧化硅层、位于第一氧化硅层表面的氮化硅层、以及位于氮化硅层表面的第二氧化硅层。
可选的,所述氧化层的厚度为10埃~40埃。
可选的,所述抛光工艺包括:第一次抛光工艺、以及在第一次抛光工艺之后的第二次抛光工艺,所述第一次抛光工艺的抛光速率大于第二次抛光工艺的抛光速率。
可选的,所述第一次抛光工艺的抛光速率为5埃/秒~20埃/秒,所述第二次抛光工艺的抛光速率为1埃/秒~5埃/秒。
可选的,在所述第一次抛光工艺之后,所述器件层的表面到隔离结构顶部表面的距离为100埃~800埃。
可选的,所述隔离结构的形成工艺包括:在衬底表面形成掩膜层,所述掩膜层暴露出需要形成隔离结构的对应位置;以所述掩膜层为掩膜,刻蚀所述衬底,在所述衬底内形成沟槽;在所述沟槽内形成填充满所述沟槽的隔离层;对所述隔离层进行抛光直至暴露出掩膜层表面为止,在所述沟槽内形成隔离结构;在所述抛光工艺之后,去除所述掩膜层。
可选的,所述掩膜层和衬底之间还具有第二介质层。
与现有技术相比,本发明的技术方案具有以下优点:
本发明的半导体结构的形成方法中,在对衬底和隔离结构表面的器件层进行抛光工艺、并暴露出隔离结构表面之后,采用干法处理工艺去除所述器件层和隔离结构表面的残余物质。由于所述抛光工艺对于器件层和隔离结构的抛光速率相同,会在所述隔离结构表面残留所述浮栅层的材料,而所述干法处理工艺能够去除所述隔离结构表面的残余物质,从而保证了相邻器件层之间的电隔离性能良好。同时,所述干法处理工艺进去除隔离结构表面的残余物质,因此不会对器件层的尺寸造成进一步的影响,能够提高整片晶圆表面器件层的均一性。而且,经过所述干法处理工艺之后,所述隔离结构和器件层的表面光滑,有利于后续在所述隔离结构和器件层表面进行的工艺。
进一步,在所述干法处理工艺之后,采用氧化工艺在所述器件层和隔离结构表面形成氧化层;在所述氧化工艺之后,采用湿法清洗去除所述氧化层。所述氧化工艺能够将经过干法处理工艺未被去除的残余物质进行氧化,并形成氧化层,并以所述湿法清洗工艺去除所述氧化层,进一步去除隔离结构表面的残余物质。而且,经过氧化工艺和湿法清洗工艺之后,所述器件层和隔离结构表面更为光滑,有利于后续在所述器件层和隔离结构表面形成第一介质层。
进一步,所述隔离结构的材料为氧化硅,所述器件层的材料为多晶硅,所述器件层作为浮栅,所述浮栅用于构成闪存存储器件。所形成的浮栅尺寸均一,而且相邻浮栅之间的电隔离性能良好,因此以所述浮栅构成的闪存存储单元性能稳定。而且,所述浮栅和隔离结构表面光滑平坦,有利于后续形成第一介质层。
附图说明
图1是现有技术的一种闪存存储单元的剖面结构示意图;
图2是隔离闪存存储单元浮栅的隔离结构的示意图;
图3至图5是一种形成如图2所示浮栅层和隔离结构过程的剖面结构示意图;
图6至图11是本发明实施例的半导体结构的形成过程的剖面结构示意图。
具体实施方式
如背景技术所述,现有技术所形成的浮栅层和隔离结构的形貌不良,使得所形成的闪存存储单元的性能不稳定。
经过研究,请参考图3至图5是一种形成如图2所述浮栅层和隔离结构过程的剖面结构示意图。
请参考图3,提供衬底20,所述衬底20内具有若干隔离结构24,所述隔离结构24的表面高于所述衬底20的表面。
请参考图4,采用沉积工艺在所述衬底20和隔离结构24表面形成浮栅层23。
请参考图5,采用化学机械抛光工艺对所述浮栅层23进行抛光,直至暴露出隔离结构24表面为止。
其中,所述化学机械抛光工艺包括:第一次抛光工艺和第二次抛光工艺。其中,所述第一次抛光工艺对于浮栅层23和隔离结构24的抛光速率相同,且具有较高的抛光速率,能够减薄较多浮栅层23的厚度,使所述浮栅层23的表面接近隔离结构24的顶部表面;所述第二次次抛光工艺对于浮栅层23和隔离结构24的抛光速率相同,且具有较低的抛光速率,使所述浮栅层23表面逐渐接近隔离结构24,直至暴露出所述隔离结构24表面,所述较低的抛光速率能够保证所述第二次抛光工艺能够恰好停止于隔离结构24表面。
然而,由于所述第一次抛光工艺和第二次抛光工艺对于浮栅层23和隔离结构24的抛光速率均相同,因此容易在隔离结构24表面残余浮栅层23的材料,所残余的浮栅层23的材料容易导致相邻浮栅层23之间的漏电,使所形成的闪存存储单元的性能降低。因此,在第二次抛光工艺之后,需要进行第三次抛光工艺,所述第三次抛光工艺对于浮栅层23的抛光速率高于对于隔离结构24的抛光速率,能够去除隔离结构24表面的浮栅层材料。但是,所述第三次抛光工艺同时会降低所述浮栅层23的厚度,导致浮栅层23的尺寸难以精确控制;而且,由于化学机械抛光工艺对于晶圆中心和边缘的抛光速率不一致,而第三次抛光工艺主要对于浮栅层材料的抛光速率较大,因此,在经过所述第三次抛光工艺之后,更容易导致晶圆中心的浮栅层23尺寸与晶圆边缘的浮栅层23尺寸不一致,从而导致所形成的闪存存储单元的均一性变差、性能不稳定。
为了解决上述问题,经过进一步研究,本发明提出一种半导体结构的形成方法。其中,在对衬底和隔离结构表面的器件层进行抛光工艺、并暴露出隔离结构表面之后,采用干法处理工艺去除所述器件层和隔离结构表面的残余物质。由于所述抛光工艺对于器件层和隔离结构的抛光速率相同,会在所述隔离结构表面残留所述浮栅层的材料,而所述干法处理工艺能够去除所述隔离结构表面的残余物质,从而保证了相邻器件层之间的电隔离性能良好。同时,所述干法处理工艺进去除隔离结构表面的残余物质,因此不会对器件层的尺寸造成进一步的影响,能够提高整片晶圆表面器件层的均一性。而且,经过所述干法处理工艺之后,所述隔离结构和器件层的表面光滑,有利于后续在所述隔离结构和器件层表面进行的工艺。
为使本发明的上述目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施例做详细的说明。
图6至图11是本发明实施例的半导体结构的形成过程的剖面结构示意图。
请参考图6,提供衬底200,所述衬底200内具有若干隔离结构201,所述隔离结构201的表面高于所述衬底200的表面。
所述衬底200用于为后续工艺提供工作平台,所述衬底200为硅衬底、硅锗衬底、碳化硅衬底、绝缘体上硅(SOI)衬底、绝缘体上锗(GOI)衬底、玻璃衬底或III-V族化合物衬底,例如氮化镓或砷化镓等。所述衬底200具有有源区,所述有源区表面用于形成有源器件。本实施例中,后续形成的器件层作为闪存存储单元内的浮栅,所述有源区内形成闪存存储单元的源区和漏区。
所述隔离结构201的材料为氧化硅、氮化硅、氮氧化硅,所述隔离结构201用于隔离相邻浮栅区表面的浮栅层以及衬底200内的有源区。所述隔离结构201的形成工艺包括:在衬底200表面形成掩膜层(未示出),所述掩膜层暴露出需要形成隔离结构201的对应位置;以所述掩膜层为掩膜,刻蚀所述衬底200,在所述衬底200内形成沟槽(未示出);在所述沟槽内形成填充满所述沟槽的隔离层(未示出);对所述隔离层进行抛光直至暴露出掩膜层表面为止,在所述沟槽内形成隔离结构201;在所述抛光工艺之后,去除所述掩膜层。本实施例中,由于后续形成的器件层为闪存存储单元内的浮栅,后续形成器件层之后,需要形成横跨于部分隔离结构201表面的源线和字线。
所述掩膜层用于定义所述隔离结构201的位置以及顶部的图形,而且,所述掩膜层还能够为后续形成的器件层占据空间,从而定义了后续形成的器件层的结构和尺寸。在本实施例中,所述掩膜层的材料为氮化硅,所述掩膜层的形成工艺包括:在衬底200表面形成掩膜薄膜;在所述掩膜薄膜表面形成图形化层,所述图形化层定义出需要形成隔离结构201的对应位置;以所述图形化层为掩膜,采用各向异性干法刻蚀工艺刻蚀所述掩膜薄膜,形成掩膜层。其中,所述图形化层能够采用光刻工艺、纳米印刷工艺、定向自组装工艺或自对准多重图形工艺形成。
需要说明的是,由于后续在对器件层进行抛光之后,需要对器件层和隔离结构201的表面进行干法处理工艺,所述干法处理工艺会减薄所述器件层和隔离结构201的厚度,因此,为了保证在干法处理工艺之后,所述器件层的厚度能够达到预设厚度,所述隔离结构201的顶部表面到第二介质层202表面的距离需要大于所述器件层的预设厚度。在本实施例中,所述隔离结构201的顶部表面到第二介质层202表面的距离、比器件层203的预设厚度大50埃~150埃。
在本实施例中,所述掩膜层和衬底200之间还具有第二介质层202,所述第二介质层202的材料为氧化硅,所述第二介质层202的形成工艺为化学气相沉积工艺、原子层沉积工艺或热氧化工艺。所述第二介质层202能够在去除掩膜层时,保护衬底200表面免受损伤;此外,后续所形成的器件层为浮栅,所述第二介质层202能够作为浮栅和衬底之间的隧穿氧化层,当所形成的闪存存储单元工作时,位于浮栅底部的衬底200内形成沟道区,载流子能够穿过所述第二介质层202,实现在沟道区和浮栅之间的迁移,以此达到写入、擦除或编程等操作目的。
请参考图7,在所述衬底200和隔离结构201表面形成器件层203。
在本实施例中,所述器件层203用于形成闪存存储单元内的浮栅,所述器件层的材料为多晶硅。在其他实施例中,所述器件层的材料还能够为金属或绝缘材料。
所述器件层203的形成工艺为化学气相沉积工艺或物理气相沉积工艺。为了保证后续经过抛光工艺之后,所述器件层203的表面能够与隔离结构201的表面保持齐平,采用沉积工艺形成的器件层203厚度大于或等于所述隔离结构201顶部到第二介质层202表面的距离。
请参考图8,对所述器件层203进行抛光工艺,直至暴露出隔离结构201表面为止,所述抛光工艺对于器件层203和隔离结构201的抛光速率相同。
所述抛光工艺用于去除高于隔离结构201顶部的器件层203,并暴露出所述隔离结构201表面。
本实施例中,为了保证所述抛光工艺能够停止于隔离结构201的顶部表面,而不会对所述隔离结构201的顶部表面造成过多损伤,进而保证形成于相邻隔离结构201之间的器件层203的厚度更为精确,所述抛光工艺包括第一次抛光工艺、以及在第一次抛光工艺之后的第二次抛光工艺,而且所述第一次抛光工艺的抛光速率大于第二次抛光工艺的抛光速率。
所述第一次抛光工艺的抛光速率为5埃/秒~20埃/秒,在经过所述第一次抛光工艺之后,所述器件层203的表面到隔离结构201的表面的距离为100埃~800埃。在所述第一次抛光工艺中,对器件层203和隔离结构201的抛光速率相同,即所述器件层203和隔离结构201之间不具有抛光选择比;所述第一次抛光工艺的抛光速率较大,能够快速地使器件层203的表面接近所述隔离结构201的顶部。
在第一次抛光工艺之后,进行第二次抛光工艺,所述第二次抛光工艺的抛光速率为1埃/秒~5埃/秒,所述第二次抛光工艺用于暴露出隔离结构201的顶部表面。由于所述第二次抛光工艺对器件层203和隔离结构201的抛光速率相同,因此经过所述第二次抛光工艺之后,能够保证所述器件层203和隔离结构201的表面平坦、且保持齐平,使得器件层203的厚度均匀;而且,由于所述第二次抛光工艺的抛光速率较慢,能够使器件层203的表面接近隔离结构201的顶部表面的速率较慢,能够减少对隔离结构201顶部表面的损伤。
然而,由于所述第一次抛光工艺和第二次抛光工艺对器件层203和隔离结构201的抛光速率相同,容易使器件层203和隔离结构201的表面附着残余物质205,所述残余物质205包括器件层203的材料。位于隔离结构201表面的残余物质会造成相邻器件层203之间造成漏电,进而使所形成的半导体结构的电性能不良;而位于器件层203表面的残余物质205会造成器件层203的尺寸不均匀,则器件层203的性能不稳定。因此,后续需要通过干法处理工艺去除所述器件层203和隔离结构201表面的残余物质。在本实施例中,所述器件层203的材料为多晶硅,所述残余物质205的材料包括多晶硅。
请参考图9,在所述抛光工艺之后,采用干法处理工艺去除所述器件层203和隔离结构201表面的残余物质205(如图8所示)。
所述干法处理工艺对于器件层203和隔离结构201的刻蚀速率相同,因此,对器件层203和隔离结构201减薄的厚度相同,能够在干法处理工艺之后,使器件层203和隔离结构201的表面保持齐平、平坦。
所述干法处理工艺中,处理气体能够对残余物质205进行轰击,并通过处理气体的流动将残余物质205带离器件层203和隔离结构201表面。在本实施例中,所述残余物质205包括多晶硅,所述干法处理工艺的气体包括含氟气体。在本实施例中,所述干法处理的气体包括Ar、He、CF4、CHF3,其中,所述Ar的流量为100sccm~800sccm,He的流量为50sccm~200sccm,CF4的流量为20sccm~300sccm,CHF3的流量为10sccm~200sccm。
所述干法处理工艺还减薄所述器件层203和隔离结构201的厚度,减薄后的器件层203和隔离结构201表面相对于减薄前降低30埃~80埃,以此保证所述干法处理工艺能够完全去除残余物质205。在本实施例中,所述隔离结构201的顶部表面到第二介质层202表面的距离大于器件层的预设厚度,即经过第二次抛光工艺之后,所述器件层203的厚度大于预设厚度,因此,经过干法处理工艺之后,所述器件层203能够达到预设厚度,而且所述器件层203的尺寸均匀。
在本实施例中,为了保证彻底清除所述残余物质,在所述干法处理工艺开之后,还对所述器件层203表面进行氧化工艺和清洗工艺。
在另一实施例中,在所述干法处理工艺之后,在所述器件层表面形成第一介质层,在所述第一介质层表面形成控制栅、字线层或源线层,所述控制栅、字线层或源线层用于构成闪存存储单元。所述第一介质层的形成方法为化学气相沉积工艺,所述第一介质层包括:第一氧化硅层、位于第一氧化硅层表面的氮化硅层、以及位于氮化硅层表面的第二氧化硅层。由于所述器件层和隔离结构表面平坦均匀、且不具有残余物质附着,因此所形成的第一介质均匀致密,保证了电隔离性能。
请参考图10,在所述干法处理工艺之后,采用热氧化工艺在所述器件层203和隔离结构201表面形成氧化层204。
通过所述热氧化工艺能够在所述器件层203和隔离结构201表面形成氧化层204,从而使附着于器件层203和隔离结构201表面的残余物质205氧化,以此进一步去除所述残余物质205,从而保证了器件层203和隔离结构201表面的纯净。而且,所述氧化层204的厚度能够通过氧化工艺进行控制、且厚度均匀,因此经过所述氧化工艺之后,所述器件层203的厚度能够保证精确均匀。
本实施例中,所述器件层203的材料为多晶硅,所形成的氧化层204的材料为氧化硅,所述氧化层204的厚度为10埃~40埃。
请参考图11,在所述氧化工艺之后,去除所述氧化层204(如图10所示)。
本实施例中,去除所述氧化层204的工艺为湿法清洗工艺,所述湿法清洗工艺对于所述氧化层204和器件层203具有选择性,能够在去除氧化层204的同时,保证所述器件层203的表面不受损伤,因此所述器件层203的表面光滑平坦,且所述器件层203的尺寸精确均匀。本实施例中,由于所述氧化层204的材料为氧化硅,所述湿法清洗工艺的清洗液包括氢氟酸。
在其他实施例中,还能够以干法刻蚀工艺去除所述氧化层204。
需要说明的是,在所述湿法清洗工艺之后,在所述干法处理工艺之后,在所述器件层表面形成第一介质层。所述第一介质层采用化学气相沉积工艺或物理气相沉积工艺形成。所述第一介质层的材料为氧化硅、氮化硅、或氮氧化硅。
本实施例中,所形成的第一介质层由第一氧化硅层、位于第一氧化硅层表面的氮化硅层、以及位于氮化硅层表面的第二氧化硅层构成,形成ONO结构的介质层。在形成所述第一介质层之后,在所述第一介质层表面形成控制栅、字线层或源线层,所述控制栅、字线层或源线层,并进一步形成闪存存储单元。
本实施例中,在对衬底和隔离结构表面的器件层进行抛光工艺、并暴露出隔离结构表面之后,采用干法处理工艺去除所述器件层和隔离结构表面的残余物质。由于所述抛光工艺对于器件层和隔离结构的抛光速率相同,会在所述隔离结构表面残留所述浮栅层的材料,而所述干法处理工艺能够去除所述隔离结构表面的残余物质,从而保证了相邻器件层之间的电隔离性能良好。同时,所述干法处理工艺进去除隔离结构表面的残余物质,因此不会对器件层的尺寸造成进一步的影响,能够提高整片晶圆表面器件层的均一性。而且,经过所述干法处理工艺之后,所述隔离结构和器件层的表面光滑,有利于后续在所述隔离结构和器件层表面进行的工艺。
虽然本发明披露如上,但本发明并非限定于此。任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (18)

1.一种半导体结构的形成方法,其特征在于,包括:
提供衬底,所述衬底内具有若干隔离结构,所述隔离结构的表面高于所述衬底的表面;
在所述衬底和隔离结构表面形成器件层;
对所述器件层进行抛光工艺,直至暴露出隔离结构表面为止,所述抛光工艺对于器件层和隔离结构的抛光速率相同;
在所述抛光工艺之后,采用干法处理工艺去除所述器件层和隔离结构表面的残余物质。
2.如权利要求1所述的半导体结构的形成方法,其特征在于,所述隔离结构的材料为氧化硅、氮化硅或氮氧化硅,所述器件层的材料为多晶硅。
3.如权利要求2所述的半导体结构的形成方法,其特征在于,所述干法处理工艺的气体包括含氟气体,所述干法处理工艺对于器件层和隔离结构的刻蚀速率相同。
4.如权利要求3所述的半导体结构的形成方法,其特征在于,所述干法处理的气体包括Ar、He、CF4、CHF3,所述Ar的流量为100sccm~800sccm,He的流量为50sccm~200sccm,CF4的流量为20sccm~300sccm,CHF3的流量为10sccm~200sccm。
5.如权利要求1或3所述的半导体结构的形成方法,其特征在于,所述干法处理工艺减薄器件层和隔离结构的厚度,减薄后的器件层和隔离结构表面相对于减薄前降低30埃~80埃。
6.如权利要求2所述的半导体结构的形成方法,其特征在于,所述残余物质包括硅材料。
7.如权利要求2所述的半导体结构的形成方法,其特征在于,所述器件层作为浮栅,所述浮栅用于构成闪存存储单元。
8.如权利要求7所述的半导体结构的形成方法,其特征在于,还包括:在所述干法处理工艺之后,在所述器件层表面形成第一介质层;在所述第一介质层表面形成控制栅、字线层或源线层。
9.如权利要求1所述的半导体结构的形成方法,其特征在于,还包括:在所述干法处理工艺之后,采用热氧化工艺在所述器件层和隔离结构表面形成氧化层;在所述氧化工艺之后,去除所述氧化层。
10.如权利要求9所述的半导体结构的形成方法,其特征在于,去除所述氧化层的工艺为湿法清洗工艺。
11.如权利要求9所述的半导体结构的形成方法,其特征在于,在所述湿法清洗工艺之后,在所述干法处理工艺之后,在所述器件层表面形成第一介质层。
12.如权利要求8或11所述的半导体结构的形成方法,其特征在于,所述第一介质层包括:第一氧化硅层、位于第一氧化硅层表面的氮化硅层、以及位于氮化硅层表面的第二氧化硅层。
13.如权利要求9所述的半导体结构的形成方法,其特征在于,所述氧化层的厚度为10埃~40埃。
14.如权利要求1所述的半导体结构的形成方法,其特征在于,所述抛光工艺包括:第一次抛光工艺、以及在第一次抛光工艺之后的第二次抛光工艺,所述第一次抛光工艺的抛光速率大于第二次抛光工艺的抛光速率。
15.如权利要求14所述的半导体结构的形成方法,其特征在于,所述第一次抛光工艺的抛光速率为5埃/秒~20埃/秒,所述第二次抛光工艺的抛光速率为1埃/秒~5埃/秒。
16.如权利要求14所述的半导体结构的形成方法,其特征在于,在所述第一次抛光工艺之后,所述器件层的表面到隔离结构顶部表面的距离为100埃~800埃。
17.如权利要求1所述的半导体结构的形成方法,其特征在于,所述隔离结构的形成工艺包括:在衬底表面形成掩膜层,所述掩膜层暴露出需要形成隔离结构的对应位置;以所述掩膜层为掩膜,刻蚀所述衬底,在所述衬底内形成沟槽;在所述沟槽内形成填充满所述沟槽的隔离层;对所述隔离层进行抛光直至暴露出掩膜层表面为止,在所述沟槽内形成隔离结构;在所述抛光工艺之后,去除所述掩膜层。
18.如权利要求17所述的半导体结构的形成方法,其特征在于,所述掩膜层和衬底之间还具有第二介质层。
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