CN104616994A - 形成具有多重功函数栅极结构的方法及所产生的产品 - Google Patents
形成具有多重功函数栅极结构的方法及所产生的产品 Download PDFInfo
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- CN104616994A CN104616994A CN201410602674.9A CN201410602674A CN104616994A CN 104616994 A CN104616994 A CN 104616994A CN 201410602674 A CN201410602674 A CN 201410602674A CN 104616994 A CN104616994 A CN 104616994A
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Abstract
本发明揭露一种形成具有多重功函数栅极结构的方法及所产生的产品,其方法包含去除NMOS晶体管和PMOS晶体管的牺牲栅极结构,从而定义NMOS栅极腔和PMOS栅极腔;在该NMOS栅极腔和该PMOS栅极腔中形成高k栅极绝缘层;在该NMOS和PMOS栅极腔中的该高k栅极绝缘层上形成镧系材料层;执行加热工艺,以从该镧系材料层将材料驱入该高k栅极绝缘层,从而在每个该NMOS和PMOS栅极腔内形成含镧高k栅极绝缘层;以及在该NMOS和PMOS栅极腔中的该含镧高k栅极绝缘层上方形成栅极电极结构。
Description
技术领域
一般来说,本发明涉及半导体装置的制造,并且,更具体地,各种新颖的方法,以形成具有多重功函数的晶体管的栅极结构以及和含有这种晶体管的各种集成电路产品。
背景技术
高级集成电路(例如,CPU、存储设备、特定功能集成电路(application specific integrated circuits,ASIC)及类似者)的制造需要在一个给定的晶片面积中按照指定的线路布局形成大量的电路元件,其中,所谓的金属氧化物半导体场效晶体管(MOSFET或FET)表示电路元件的一个重要类型,其实质地决定了该集成电路的性能。该晶体管通常是NMOS(NFET)或PMOS(PFET)型装置,其中,“N”和“P”标记乃基于形成该装置的源极区和漏极区的掺质的类型而设。所谓的互补金属氧化物半导体(CMOS)技术或产品指的是同时使用NMOS和PMOS而制造的集成电路产品。
场效晶体管,无论是NMOS或PMOS,通常包括源极区、漏极区、位在源极区和漏极区之间的通道区、以及位在通道区上方的栅极电极。流过FET的电流乃透过加诸于栅极电极的电压来控制。对于NMOS而言,如果没有电压被施加到栅极电极,则没有电流流过该装置。然而,当一个适当的正电压被施加到栅极电极时,NMOS的通道区就变成导通的,同时电流会被允许通过通道区,在源极区和漏极区之间流动。对于PMOS言,控制电压反向地运作。场效晶体管可以有各种不同的物理形状,如所谓的平面FET或所谓的3D或FinFET。
几十年来,主流一向以平面FET用于制造集成电路的产品,其乃肇因于涉及了形成这种平面装置的制造方法在比较下更简便,相对于涉及了形成3D晶体管的制造方法而论。为了提高平面FET的速度也为了增大平面FET于集成电路的密度,设计者多年来已经大幅降低了平面FET的物理尺寸。更具体言之,平面FET的通道长度已显著地减小,其导致平面FET开关速度的提升。然而,降低通道区长度同时也减少了源极区和漏极区之间的距离。在某些情况下,源极区和漏极区间的分离缩减使得它很难有效地防止源极区和通道区的电势被漏极区负面地影响。这有时被称为短通道效应,使其中平面FET作为主动开关的特性遭到劣化。
如上所述,相对于平面场效晶体管,所谓的3D或FinFET装置有种三维(3D)结构。更具体地说,在FinFET里,一般而言垂直设置的鳍状的作用区形成在半导体基底,而栅极结构(栅极绝缘层和栅极电极)则被置于鳍形作用区的左右两侧和上表面,以期形成三面栅极结构,进而使用三维结构取代平面结构。在某些情况下,绝缘覆盖层(例如,氮化硅)位于鳍的顶部,使该FinFET只有双栅极结构。不同于平面FET,在FinFET装置中,通道垂直形成于半导体基底的表面,以便缩小半导体装置尺寸。此外,在FinFET中,接面电容在装置漏极区被大幅减小,这往往会降低至少一些短通道效应。当一个适当的电压被施加到鳍式场效晶体管的栅极电极,鳍的表面(和接近该表面的内部),也就是那大致垂直直立的侧壁和鳍的上表面,会成为导电通道区,从而让电流流通。在FinFET装置中,“通道宽度”是大约垂直鳍的高度的2倍再加上该鳍顶部表面的宽度,也就是鳍宽度。多个鳍可以形成在其相对平面型晶体管装置的覆盖区内。因此,对于一个给定的覆盖区,FinFET往往能够产生明显更强的电流-相较于平面晶体管装置而言。也因此FinFET的漏电流在装置关闭后大大地降低-相较于平面晶体管装置而言。此乃肇因于对“鳍”通道区更优越的控制。总之,FinFET的三维结构是一个更优越的MOSFET结构-相较于平面晶体管装置而言-特别是在20nm的CMOS技术节点和其后驱者。
对于许多早期的设备技术世代,大部分晶体管元件的栅极结构已经由多种硅基材料构成,如二氧化硅氧化物、和/或氮氧化硅、及其与多晶硅栅极电极的组合。然而,随着大幅缩小后的晶体管元件的通道长度变得越来越小,许多较新世代的装置采用包含替代材料的栅极结构,以便避免短通道效应可能伴随着使用传统硅基材料于短通道而发生。例如,在一些大幅缩小的晶体管元件中,通道长度可能在10-32纳米的数量级上,其中,实施有包括一个所谓的高k电介质绝缘层的栅极结构和一或多层充当栅极电极(HK/MG)的金属层。这种替代栅极结构已经证实可以提供优化的操作特性-相较于传统二氧化硅氧化物/多晶硅栅极结构配置而言。
根据具体的整体装置的要求,几种不同高k材料–也就是介电常数大约大于10的材料-已被使用于栅极的绝缘层中的HK/MG栅极电极结构,而有了不同程度的成功。例如,在某些晶体管元件设计中,高k绝缘层可能包括了五氧化二钽(Ta2O5)、氧化铪(HfO2)、氧化锆(ZrO2)、二氧化钛(TiO2)、氧化铝(Al2O3)、铪硅酸盐(HfSiOx)、和类似者。另外,一或多个非多晶硅金属栅极电极材料–也就是,金属栅极堆迭层–可被用于HK/MG设置中以便于控制晶体管的功函数。这些金属电极材料可包括,例如,一或多层的钛(Ti)、氮化钛(TiN)、铝化钛(TiAl)、钛铝碳(TiAlC)化物、铝(Al)、氮化铝(AlN)、钽(Ta)、氮化钽(TaN)、碳化钽(TaC)、钽碳氮化物(TaCN)、钽硅氮化物(TaSiN)、钽硅化物(TaSi)及类似者。
在现代集成电路产品的制造中,晶体管装置有时刻意地形成予多个临界电压。一般而言,临界电压相对较低的晶体管可以工作于较高的切换速度-相对于临界电压较高的晶体管而言。此低临界电压(LVT)晶体管通常给运用在集成电路产品中其速度为欲得或致要之处,比方说,在数位电路类的集成电路产品中就是如此。不幸地,这种低临界电压装置倾向于呈现较大的漏电流于关闭态,这意味着这些装置消耗了比其相对装置所期还多的功率。因此,当其它相较条件相同时,此种低临界电压装置就成了劣等的选择,其乃针对于重视减低功率的应用而言,诸如行动运算、手机应用等。相反的论调对所谓的高临界电压(HVT)晶体管也适用-它们工作于较低的切换速度(坏处),但是呈现较低的漏电流于关闭态-相对于临界电压较低的晶体管而言(优点)。此种高临界电压装置通常给运用在集成电路产品中装置性能表现和速度不那么要紧之处,比方说SRAM电路。装置设计者也可以制作所谓的一般性临界电压(RVT)晶体管,其临界电压介于低临界电压与高临界电压之间。当然,这些临界电压的绝对值(低、一般性、高)可能受多种因子影响。
装置设计者使用了数种技巧以便刻意改变晶体管的临界电压。其中,一种技巧涉及改变栅极长度-晶体管中源极区和漏极区之间的距离。当其它相较条件相同时,栅极长度较短的晶体管可更高速地工作,但是呈现较大的漏电流于关闭态,相对于长度较长的晶体管而言。装置大小已经缩小到一个程度,其栅极长度短到要制造更短栅极长度的晶体管变得很困难、费时、且昂贵。因此以减小栅极长度调整临界电压愈发堪虑。
另一装置设计者用的改变临界电压的技巧涉及改变杂质掺入量,其运用可见于晶体管中半导体井区的形成。当其它相较条件相同时,井区的杂质掺入量愈高,最后临界电压愈高,反之亦然。但是,在某些应用中,如FinFET,取得适当的杂质掺入量是挑战性相当高的,其乃因杂质掺入量有随机性的变动及一般离子布值所具有的常态性高斯分布。
还有另一个设计者用的改变晶体管临界电压的技巧,其仅涉及由具有不同功函数的不同材料形成栅极层,以便最终得到需要的临界电压变化量。功函数(WF)这个辞汇通常给用在半导体设计和制造中来代表从金属表面移除电子所需的最小能量。金属的功函数通常针对不同的金属有不同的固定特性,且通常以电子伏特(eV)量之。一般而言,对使用硅质基底的CMOS集成方法而言,在NMOS中,功函数金属需要接近电子传导能带边缘(约4.0eV)的功函数,而在NMOS中另一种功函数金属则被需要,其功函数接近电子共价能带边缘(约5.1-5.2eV)。因此在CMOS集成方法中,要运用高k介电栅极材料,至少需要两种栅极堆迭层,也就是说,能合乎NMOS和PMOS个别需求的功函数的材料。如上所述,PMOS的栅极堆迭层有个平带电压,其较接近PMOS的通道区的共价能带边缘,而NMOS的栅极堆迭层有个平带电压,其较接近NMOS的通道区的传导能带边缘。
举例来说,形成CMOS集成电路伙同双功函数晶体管装置可能涉及沉积一层高k材料(比方氧化铪),其作为所有晶体管的栅极绝缘层(PMOS和NMOS)并且沉积一层P功函数金属(例如氮化钛(WF=约4.9eV)),置于高k栅极绝缘层上。因此,P功函数金属会被布线于仅仅于PMOS上。然后,一N功函数金属,如铝系材料,像是铝钛(WF=约4.3eV),给沉积于暴露的高k绝缘层的绝缘材料之上(于此NMOS将被形成),同时也在布线过的PMOS的功函数金属之上。在对N功函数金属布线后,PMOS装置的栅极堆迭层由三层材料所组成(高k栅极绝缘层材料,P功函数金属,N功函数金属),而NMOS、PMOS装置的栅极堆迭层仅由两层材料所组成(高k栅极绝缘层材料,N功函数金属)。
上述堆迭层工艺可以扩充而赋予晶体管更多层次的功函数值,只要使用适当的遮罩、金属沉积、和金属蚀刻步骤即可。举例来说,为了制造有三个功函数的晶体管给集成电路产品,能在该第三装置形成区的基底区域给予蚀刻,以便于清除上述P-和N功函数金属的栅极绝缘层。因此,第三金属层,如氮化钨(WF=约4.6eV-P-和N功函数的中间值)可被沉积在暴露的高k绝缘层上(其处为第三装置形成处)及布线过的P功函数上和布线过的N功函数上。第三金属层布线过后,PMOS的栅极堆迭层由四层材料组成(高k栅极绝缘层材料、P功函数金属、N功函数金属、和第三金属层);NMOS的栅极堆迭层由三层材料组成(高k栅极绝缘层材料、N功函数金属、和第三金属层);第三装置的栅极堆迭层由两层材料组成(高k栅极绝缘层材料、和第三金属层)。除了N-和P功函数金属之外,还可以配置次-N功函数金属(WF=4.45eV)及配置次-P功函数金属(WF=4.75eV)。上述所言工艺可重复应用以集成形成第三和第四装置,其具有包含此第三第四金属层的栅极结构。
很明显地,上述堆迭层工艺可能变得不好使用又复杂-当其越来越多版本的晶体管伴随不同的临界电压被制造出来时。在其它问题中的一项-金属蚀刻越发困难,且不同栅极堆迭层的高度来自于不同装置,其于后续工艺中产生出问题。举例来说,要在一层材料上达成真正的平面化可能更加困难,即便是这层材料经过一重或多重CMP工艺亦然-当这层材料给沉积在各种不同高度的栅极堆迭层时。这种平面化的不足会导致问题于沉积层布线上的精确性,其肇因乃光学景深的变化-当需求为暴露一层光阻层于沉积层之上时。
本发明乃关于一新方法用以形成多个功函数值的晶体管,及形成多种含此晶体管的集成电路产品,其可能解决或减少一或多项上述的问题。
发明内容
下面给出本发明的简化概要,以便提供对本发明的一些方面的基本理解。此概要不是本发明的详尽全貌。它并不旨在标示本发明的关键或重要元素。其主要目的在于以简化形式呈现一些概念,作为后面讨论的更详细描述的前奏。
一般来说,本发明涉及形成晶体管和栅极结构的新方法伴随多个功函数值,并且涉及含有这种晶体管的各种集成电路产品。这里所图示揭露的一种方法包括(除其它项目外):执行至少一个蚀刻工艺,以去除该NMOS晶体管的牺牲栅极结构和该PMOS晶体管的牺牲栅极结构,从而定义NMOS栅极腔和PMOS栅极腔;在该NMOS栅极腔和该PMOS栅极腔中形成高k栅极绝缘层;在该高k栅极绝缘层上形成位于该NMOS和PMOS栅极腔内的镧系材料层;执行至少一个加热工艺,以从该镧系材料层将材料驱入该高k栅极绝缘层,从而在每个该NMOS和该PMOS栅极腔内形成含镧高k栅极绝缘层;以及执行至少一个工艺操作,以在该NMOS栅极腔中的该含镧高k栅极绝缘层上方形成第一栅极电极结构、以及在该PMOS栅极腔中的该含镧高k栅极绝缘层上方形成第二栅极电极结构。
另一揭露的一种示例方法包括(除其它项目外):执行至少一个蚀刻工艺,以去除该NMOS晶体管的牺牲栅极结构和该PMOS晶体管的牺牲栅极结构,从而定义NMOS栅极腔和PMOS栅极腔;在该NMOS栅极腔和该PMOS栅极腔中形成包含氧化铪的高k栅极绝缘层;在该高k栅极绝缘层上形成位于该NMOS和PMOS栅极腔内的镧系材料层;执行至少一个加热工艺,以从该氧化镧层将镧驱入该高k栅极绝缘层,从而在每个该NMOS和该PMOS栅极腔内形成铪镧氧化物栅极绝缘层;以及执行至少一个工艺操作,以在该NMOS栅极腔中的该铪镧氧化物栅极绝缘层上形成第一栅极电极结构、以及在该PMOS栅极腔中的该铪镧氧化物栅极绝缘层上形成第二栅极电极结构。
另一图示揭露的一种方法包括(除其它项目外):执行至少一个蚀刻工艺,以去除该NMOS晶体管的牺牲栅极结构和该第一及第二PMOS晶体管的牺牲栅极结构,从而定义NMOS栅极腔和第一及第二PMOS栅极腔;在每个该NMOS栅极腔和该第一及第二PMOS栅极腔中形成高k栅极绝缘层;形成图案化的硬遮罩层,以覆盖该第一PMOS栅极腔内的该高k栅极绝缘层,但暴露该NMOS栅极腔及该第二PMOS栅极腔内的该高k栅极绝缘层;在该NMOS栅极腔中的该暴露的高k栅极绝缘层上、该第二PMOS栅极腔中的该暴露的高k栅极绝缘层上、及该图案化的硬遮罩层上形成镧系材料层;执行至少一个加热工艺,以从该镧系元素层将材料驱入该NMOS栅极腔中的该高k栅极绝缘层及该第二PMOS栅极腔中的该高k栅极绝缘层,从而在该NMOS栅极腔中形成第一含镧高k栅极绝缘层、及在该第二PMOS栅极腔中形成第二含镧高k栅极绝缘层;执行至少一个蚀刻工艺,以去除该镧系材料层和该图案化的硬遮罩层;以及执行至少一个工艺操作,以形成︰第一栅极电极结构在该NMOS栅极腔中的该第一含镧高k栅极绝缘层上;第二栅极电极结构在该第二PMOS栅极腔中的该第二含镧高k栅极绝缘层上;以及第三栅极电极结构在该第一PMOS栅极腔中的该高k栅极绝缘层上。
本文所公开的一种新的集成电路产品包括(除其它项目外):NMOS晶体管和PMOS晶体管,该NMOS晶体管具有栅极结构,该栅极结构包含NMOS栅极绝缘层及位于该NMOS栅极绝缘层上方的NMOS功函数调整金属层,该NMOS栅极绝缘层包含含镧高k栅极绝缘材料,该PMOS晶体管具有栅极结构,该栅极结构包含PMOS栅极绝缘层及位于该PMOS栅极绝缘层上方的PMOS功函数调整金属层,该NMOS栅极绝缘层包含含镧高k栅极绝缘材料。
本文所公开的另一种新的集成电路产品包括(除其它项目外)具有栅极结构的第一NMOS晶体管,该栅极结构包含第一NMOS栅极绝缘层及位于该第一NMOS栅极绝缘层上方的第一NMOS功函数调整金属层,该第一NMOS栅极绝缘层包含含镧高k绝缘材料。该装置也包括具有栅极结构的第二NMOS晶体管,该栅极结构包含第二NMOS栅极绝缘层及位于该第二NMOS栅极绝缘层上方的第二NMOS功函数调整金属层,该第二NMOS栅极绝缘层包含高k绝缘材料,其中,该第一及第二NMOS功函数调整金属层包含NMOS功函数调整材料。该装置另包括具有栅极结构的第一PMOS晶体管,该栅极结构包含第一PMOS栅极绝缘层及位于该第一PMOS栅极绝缘层上方的一PMOS功函数调整金属层,该第一PMOS栅极绝缘层包含高k绝缘材料。该装置另包括具有栅极结构的第二PMOS晶体管,该栅极结构包含第二PMOS栅极绝缘层及位于该第二PMOS栅极绝缘层上方的第二PMOS功函数调整金属层,该第二PMOS栅极绝缘层包含含镧高k绝缘材料,其中,该第一及第二PMOS功函数调整金属层包含PMOS功函数调整材料。
附图说明
本揭示可通过参考以下的说明与其附图而理解,其中,参考数字对应于所指参考物件成分,其中,
图1A-图1W描述了本文所揭露的各种例示方法,用以形成CMOS集成电路产品的栅极结构和各种新的CMOS集成电路产品。
本文所揭示的主题虽易于引发各种修改和替代型式,但其具体实施例已经通过附图中的范例于本文中详述。然而,读者应当理解,此处本具体实施例的描述并非用以局限本发明于本具体实施例所示型态,相反地,本具体实施例的描述乃意在涵盖所有的修改,相等物,替代物,盖其被涵盖于本发明精神及范围如所附权利要求书所言者。
符号说明
100 产品
12 基底
14 牺牲栅极结构
14A 牺牲栅极绝缘层
14B 牺牲栅极电极
16 侧璧间隔
18 绝缘材料层
18S 表面
20A-D 栅极腔
22 高k栅极绝缘层
10N1、10N2、10P1、10P2 晶体管装置
24 牺牲硬遮罩
26 镧系材料层
28、28A 第一金属层
30 遮罩层
32 第二金属层
34 第三金属层
36 第四金属层
40 牺牲层
42 导电材料层
44 栅极覆盖层。
具体实施方式
本发明的各种示例性实施方案描述如下。为求清晰,并非所有实施例都于本说明书中尽述。读者应能顺理成章地理解,在任何这种具体实施的开发过程中,许多的特定的实施决定必需被作出以达到开发者的特定目标,比方说遵照系统相关和业务相关的限制,其将随各不同实施而变化。此外,读者亦可理解此种开发可能复杂又耗时,且过程对于此技艺中有一般能力者仅为例行程序-在获悉此发明之后。
本主题将参照附图而述。许多绘于附图的结构、系统、和装置仅供解释所用,使得本揭示的焦点不致于被本领域技术人员周知的细节所混淆。另外,附图乃用来描述和解释本揭示的范例。本文件中的用字遣词应做被理解及解释作如同本领域技术人员所接受者。于此,没有任何一个辞句被意图赋予特别意义而使其不同于本领域技术人员所理解的一般性和习惯性的用法。此原则如是界定,其若一词句欲被赋予不同于本领域技术人员所理解的意义,那么这特殊的定义会被在说明书中以直接定义的方式呈现并提供且该词句一令人不作它想的唯一定义。
本揭示涉及一种新方法,用以形成多重功函数值的晶体管的栅极结构、以及含有这种晶体管的集成电路产品。当本领域技术人员阅读本发明后,即可明显地认知到–此处所揭示的方法可被用于制造许多不同的装置,其中,包括,但不限于–逻辑装置和记忆体装置等等。如参照附图所示,此方法的许多图示实施和此处揭示的装置现在将被更详细地描述。
本领域技术人员阅读本发明后,可以理解到,此处所揭示的发明可以被用于形成使用平面晶体管的集成电路也可以用于所谓的3D装置如FinFET,或这些装置的组合。为此揭示,其将参考到一示例的工艺流程,其中,一集成电路产品100随多个FinFET晶体管以CMOS工艺形成。另外,此发明将于一内容中被揭示,其内容乃是以替代栅极形成栅极结构。然而,此处揭示的方法,结构,和产品亦可被应用于某些晶体管,其栅极结构以所谓的栅极优先(gate-first)方法形成。因此本发明不该被视为仅限于被应用在此处所描述的示例。
图1A乃为一简化的剖面图,其属于一示例集成电路产品100于制造的初期步骤阶段。多个晶体管装置10N1、10N2、10P1和10P2将使用所谓替代栅极技术,而形成于半导体基底12上。该半导体基底12可有多种设置,如所示的硅主体设置。该半导体基底12亦可有绝缘层上硅元件(SOI)设置,其包含硅主体层、埋置的绝缘层、和作用层,其中,半导体装置形成于该作用层之内与之上。该半导体基底12可由硅或非硅的材料制成。因此,此词汇“基底”和“半导体基底”应被理解为涵盖各种材料及各种这些材料的各种型态。附图中所示剖面图乃沿图示鳍13的长轴而取,其形成于基底12。换句话说,附图中所示的剖面图乃沿栅极结构而取,其方向为晶体管装置的栅极长度方向。为免于混淆此处所揭示的发明,基底12里形成的隔离区,其用来定义诸如晶体管装置10N1、10N2、10P1和10P2形成处的作用区,并没有示例在附图中。另外,杂质掺杂区诸如源极区和漏极区、光晕植入区、井区及其类,亦未示例在附图中。
如上所述,在一示例实施例中,四示例晶体管装置10N1、10N2、10P1和10P2将于基底12上被形成。此例中,每个晶体管装置诸如10N1、10N2、10P1和10P2都会被形成来获得多重功函数。示例中,晶体管装置10N1和10N2为NMOS,而10P1和10P2为PMOS。NMOS 10N1会被形成以具有比NMOS 10N2还低的功函数。PMOS 10P1会被形成以具有比PMOS 10P2还高的功函数。如此,举例而言,示例NMOS晶体管装置10N1和PMOS晶体管装置10P2可被应用于如是场合,其高性能表现诸如较高的切换速度为一重要设计考量处,如同N-逻辑电路和P-逻辑电路,分别言之。对比之下,示例NMOS晶体管装置10N1和PMOS晶体管装置10P2可被应用于如是场合,其低耗电表现诸如低关闭状态漏电流为一重要设计考量处,如同N型SRAM和P型SRAM电路,分别言之。藉由使用此处所揭示的方法,装置设计者会有更高的弹性来设计集成电路产品100,其更倾向于为特定所需应用量身订作。
继续依图1A所示,产品100依制造中某过程描述,其处牺牲栅极结构14形成于基底12之上,且任何之前被置于牺牲栅极结构14之上的栅极覆盖层皆被移除。在此阶段于栅极替代工艺流程中,源极区和漏极区(未示)将已经被形成于基底12,并且,一退火工艺将已经被执行来活化植入的材料同时修复基底12因诸多离子布植工艺而遇到的损伤。该牺牲栅极结构14包括牺牲栅极绝缘层14A和虚设栅极电极和牺牲栅极电极14B。同时被描述的有示例的侧璧间隔16和绝缘材料层18。产品100的各种组件可用多种不同材料并用多种已知技术来形成。例如,牺牲栅极结构14可由二氧化硅氧化物组成,牺牲栅极电极14B可由多晶硅组成,侧璧间隔16可由氮化硅组成,而绝缘材料层18可由二氧化硅氧化物组成。图1A所示各层材料及如下所示各层材料可由各种已知技术形成,例如化学气相沈积(CVD)、原子层沈积(ALD)、物理气相沈积、热生成工艺等等。
如图1B所示,一道或多道蚀刻工艺被用来移除牺牲栅极电极14B和牺牲栅极绝缘层14A,以定义多个栅极腔20A-D,其中,一个不同的栅极结构会接续为每个晶体管装置10N1、10N2、10P1及10P2形成。一般来说,牺牲栅极电极14B会被移除,作为替代栅极技术的一部分,其如此处所述。然而,牺牲栅极电极14B可能不会于所有的应用中都被移除。即便是在一情况下,其牺牲栅极电极14B被刻意移除者,通常会有一层非常薄的原生氧化物层(未示)形成在基底12于栅极腔20A-D中。
图1C描绘产品100于几个工艺操作被执行之后。首先,一预洗(pre-clean)工艺被执行,以便移除所有外来材料出到栅极腔20A-D之外于形成各层材料之前,其各层材料将成为替代栅极的一部分。因此,高k栅极绝缘层22(k值大于10),如铪氧化物,其有厚度近似1-3nm,被先藉由执行ALD工艺而沈积于栅极腔20A-D。
图1D描绘产品100于几个工艺操作被执行之后,其执行乃为最终形成布线过的牺牲硬遮罩24于高k栅极绝缘层22之上,该高k栅极绝缘层22位于每个栅极腔20B和栅极腔20D内,同时令栅极腔20A及栅极腔20C内的高k栅极绝缘层22处于暴露状态。该牺牲硬遮罩24可由许多不同材料构成,如多晶硅、金属等。在一示例实施中,牺牲硬遮罩24可由一层氮化钛组成,且其可以形成以任何所需的厚度。经布线的牺牲硬遮罩24可由地毯式沈积(经CVD或PVD)一层硬遮罩层于产品100上而得,以便过填满所有的栅极腔20A-D,形成一布线过的光阻蚀刻遮罩(未示)于沈积的硬遮罩层上,之后再执行蚀刻程序以移除沈积的硬遮罩层里头欲除去的部份,以便得到如所示布线的牺牲硬遮罩24。该高k栅极绝缘层22可作为蚀刻停止层-在布线硬遮罩材料层时。之后布线过的光阻蚀刻遮罩可被移除以得到图1D中所示结构。
图1E描绘产品于镧系材料层26被形成于暴露部分的高k栅极绝缘层22及布线过的牺牲硬遮罩24之后。该镧系材料层26可以诸种形式呈现如金属、碳化物、卤化物或氮化硅,其厚度可依应用而变,其可以任何所欲工艺而形成,如ALD、PVD、CVD等。于所示实施例中,镧系材料层26是一层氧化镧,其厚度约1nm,其由实施ALD而形成。更完整地叙述如下,镧系材料层26的厚度可被调整以改变能带宽度相移的大小于受影响的原件中。另外,更大的热预算导致更多从镧系材料层26来的扩散,其制造更大的相移于元件中。
以图1F为示例,退火工艺被操作来驱入或混入部分的镧系材料层26-以与其接触的高k栅极绝缘层22为之。此程序导致形成多个含镧高k栅极绝缘层22A,也就是,混杂层22A,其为该高k绝缘层和部分的镧系材料层26的混杂或合金。例如一情况,其中,高k栅极绝缘层22由铪氧化物形成,且镧系材料层26由氧化镧形成,此时混杂层22A可由铪镧氧化物(HfLaxOy)组成。在该范例中,退火工艺被持续执行一段时间,其使得高k栅极绝缘层22的整个厚度范围被混杂于来自镧系材料层26的镧系材料。在一例中,该驱入退火工艺可在一温度条件下进行,其范围落在约500-1200℃,并持续由数纳秒到约1-10秒不等的时间。此种退火工艺可依应用而改变,比如,尖波退火、雷射退火、快速热消退退火(RTA)等。在某些实施例中,上述驱入退火工艺可以额外或部分于所谓的可靠性退火工艺执行,其一般用来执行以提高高k栅极绝缘层22的可靠性。另外,虽然附图未示,在某些应用中,额外的材料层可以在镧系材料层26上形成-在执行上述驱入退火工艺之前。例如,一层厚度为1-2nm的氮化钛(未示)可以形成于镧系材料层26上因此一层多晶硅或非晶硅(未示)可以给地毯式覆盖于氮化钛层之上以便过填满栅极腔20A和栅极腔20C。至此,上述退火过程则可为额外或部分的传统可靠性退火工艺,其乃实施于高k栅极绝缘层22。
图1G描绘产品100于一或多个蚀刻工艺被执行之后,其用以移除所有的材料,除了高k栅极绝缘层22的剩余部分之外(于栅极腔20B和栅极腔20C内)。例如,在一情况下,其于上述的氮化钛层和多晶硅/非晶硅形成处,蚀刻工艺步骤顺序可以如下:一DHF为基础的蚀刻工艺后接氢氧化铵为基础的湿工艺以便循序移除表面氧化层和其下方的多晶硅/非晶硅硅材;一SC1为基础的蚀刻工艺用以移除氮化钛层;一SC2为基础的蚀刻工艺用以移除氧化镧层;另一SC-1为基础的蚀刻工艺用以移除布线过的牺牲硬遮罩24(当它由氮化钛组成时)。
其次,如图1H所示,第一金属层28形成于高k栅极绝缘层22和混杂层22A之中于栅极腔20A-D内。该第一金属层28由金属组成,其作为替PMOS晶体管10P1和10P2调整功函数用的金属,也就是说,第一金属层28是P功函数金属。第一金属层28的厚度可依特定的应用而变,且可由任何所欲工艺形成之,如ALD和PVD之类。于一例中,第一金属层28可为一材料层组成诸以TaN、WN、TiC、或TaC等,其厚度可为2-7nm,且其形成可藉执行一ALD工艺或一电浆增强型的物理气象沉积(PVD)工艺来完成。
图1I描绘产品100在布线过的遮罩层30被形成于产品100之上之后。该布线过的遮罩层30覆盖了PMOS区域,也就是PMOS晶体管10P1和10P2,而NMOS晶体管10N1和10N2被暴露以便作更近一步的工艺处理。在一实施例中,该布线过的遮罩层30可为布线过的光阻层,其可藉已知的光学微影法工具和技术形成。
图1J描绘产品100在一干或湿蚀刻工艺给执行之后,其作用为移除暴露部分的第一金属层28。更精确地说,该第一金属层28(此P功函数金属)被从NMOS晶体管10N1和10N2相对的栅极腔20A和栅极腔20中移除。以蚀刻工艺的结果论,第一金属层28A的剩余部分被仅置于相对于PMOS 10P2和10P1的栅极腔20C和栅极腔20D中。
图1K描绘产品100于布线过的遮罩层30被移除后。该遮罩层30可藉由执行多种已知工艺(如ashing)工艺而移除。
其次,如图1L所示,光学第二金属层32被形成于产品100上。该第二金属层32由金属组成,其为阻挡层用以防止N功函数金属的扩散侵入其下方的绝缘层。在一例中,该第二金属层32可为一材料层,其组成为氮化钛,TaN,TiSiN,TaSiN,WN,或WSiN等。其厚度可为0.5-2nm,且其形成可藉执行ALD来完成。
其次,如图1M,第三金属层34形成于第二金属层32之上。第三金属层34由金属组成,其作用为NMOS的功函数调整金属。于一例中,第三金属层34可为材料层,其组成为铝钛碳(TiAlC)、TiAl、TiAlN、TaAl、TaAlC、HfAlC、HfAl、Wsi、TiSi、HfSi、或其它任何的N功函数金属,其厚度可为1-8nm,且其形成可藉执行ALD来完成。上述第二金属层32通常被需要于当N功函数金属含有铝的情况时。
其次,如图1N所示,第四金属层36被形成于第三金属层34之上。该第四金属层36由金属构成,其作用为一附着层组成以各种材料如W,Al,Ti,Co和它们的合金,其亦作用为一保护层以防止N功函数层的氧化。然而,第四金属层36不一定在所有的应用中都被需要。举例来说,若一未经形成的导电材料对于N功函数金属表现出好的附着性质,则第四金属层36可在这些应用中被忽略。在一例中,第四金属层36可为一层材料,其组成为氮化钛、TaN、TiSiN、TaSiN、WN、或WSiN等。其厚度可为1-6nm,且其形成可藉执行ALD或CVD来完成。
图1O描绘产品100于布线过的牺牲层40被地毯式覆盖于该产品100后,其作用为过填满栅极腔20A-D。该牺牲层40可由诸不同材料构成,例如,OPL等。且其形成可藉由执行如旋转涂布工艺而完成。该牺牲层40可以任何所欲厚度形成。若需要,CMP工艺可被用在牺牲层40上。
图1P描绘产品100于一或多道平面化工艺之后,如CMP工艺,其被执行来移除各该材料的一部份,其该材料位于绝缘材料18的表面18S之上和栅极腔20A-D之外。
其次,如图1Q所示,干或湿蚀刻工艺被执行来将牺牲层40嵌入栅极腔20A-D中。在一实施例里,该嵌入工艺可为计时蚀刻工艺,且最终牺牲层40在栅极腔20A-D内的残余量可有垂直厚度落于50-90nm之间-当总栅极高度约为100nm时(比如从鳍的顶端算起)。
图1R描述产品100于一或多个蚀刻工艺之后,如计时的干或湿蚀刻工艺,其被执行来移除栅极腔20A-D之中的部份的材料层如混杂层22A、高k栅极绝缘层22、第一金属层28A、第二金属层32、和第四金属层36。
图1S描绘该产品于一或多道工艺被执行之后。首先,蚀刻工艺或溶剂为基础的工艺被执行来从栅极腔20A-D内移除部份的牺牲层40。然后,导电材料层42被地毯式地覆盖于产品100上以过填满栅极腔20A-D。该导电材料层42可由诸不同导电材料形成,例如,金属如W、Al、Co、Ti、Ni、任何包含上述材料的合金,金属硅化物,高掺杂浓度的多晶硅等,且其形成可藉执行如CVD、ALD、或PVD工艺而得之,其中,可能还包括了回焊步骤。在某些情况下,附着或湿层可能需要在生成导电材料层之前先被形成,其理由为间隔介质上呈现的的低度聚合和低附着度,比如CVD W需要ALD TiN作为湿层和附着层。此导电材料层层42可被以任何所欲厚度形成。其次,以一或多道平面化工艺论,如CMP工艺,其乃被形成来移除部份的导电材料层42,其位于绝缘材料18的表面18S上和栅极腔20A-D之外。
图1T描绘产品100于一或多道工艺被执行之后。首先,干或湿蚀刻工艺被执行来将导电材料层42嵌入栅极腔20A-D中。在一实施例中,该嵌入工艺可为计时蚀刻工艺,且最终导电材料层42在栅极腔20A-D的残余量可被以任何所欲垂直厚度嵌入。其次,栅极覆盖层44给在每个栅极腔20A-D中形成。该栅极覆盖层44可形成以诸如氮化硅之类的材料,且其可先藉由地毯式地沈积一层栅极覆盖层(未示)初步形成,以便过填满所有的栅极腔20A-D,然后藉由执行一或多道平面化工艺来完成形成,其工艺如CMP工艺,用以移除位于绝缘材料18的表面18S和栅极腔20A-D之外的栅极覆盖层。工艺流程进行至此时,分别针对晶体管装置10N1、10N2、10P1、10P2的最终栅极结构50N1、50N2、50P1、和50P2已然形成。于如图1T所示的制造过程,集成电路产品100可以执行诸多传统制造工艺而得,如形成导电接触于装置的源极区和漏极区处,形成本产品的多道金属化层等。
运用此处揭示的方法,晶体管装置10N1、10N2、10P1和10P2可以不同的栅极结构生成,且其可被生成以获得四种功函数值。依此,产品100的晶体管装置10N1、10N2、10P1和10P2会有不同的临界电压。更具体地说,如示例言,此处揭示的方法导致能带宽度相移约-0.16eV,其乃基于装置10N1(4.33eV)和10P2(4.76ev)出发去比较,其包含含镧的栅极绝缘层22A相较于10N2(4.49eV)和10P1(4.92eV)而得,其乃以传统高k栅极绝缘层22为栅极绝缘层。此例中,镧系材料层26是一层氧化镧,其厚度被形成为约0.1-1nm。很重要地,也出乎意料地,含镧的栅极绝缘层22A提供了一有效的途径来控制PMOS和NMOS的功函数。提供装置设计者更多的技巧来制造多临界电压的装置并给予了设计者更高的弹性来运用在设计愈发复杂的集成电路产品。下面的表格设定了一些关于新结构产品100的特征,其描绘如图1T所示。
除了图1T中所示的四个装置的例子,此处揭示的方法还可以用来形成较少装置数目的集成电路产品,其装置亦呈现不同的功函数。更具体地说,图1U描绘了一实施例,其被用于另一集成电路产品101中,其包含三个示例用的晶体管装置10N1、10N2、和10P1,其可被随同不同的栅极结构来形成,以便有三个不同的功函数和不同的临界电压。如示例,此处揭示的方法导致功函数相移约-0.3eV,其乃基于装置10N1(4.3eV)出发去比较,其包含含镧的栅极绝缘层22A,相较于10N2(4.6eV)而得,其具有传统高k栅极绝缘层22和于能带中间的功函数的金属。于此例中,装置10P1(4.9eV)伴随高k栅极绝缘层22形成。因此,装置10N2可被视为“中间能带”装置。此处应被注意的事情为:该“中间能带”装置亦可对等地以PMOS装置制作,其运用了此处揭示的含镧的栅极绝缘层22A,也就是,相反于上述实施例的情况,其处N功函数金属给10N1用,P功函数金属给10N2和10P1用,其中,La2O3层给包含到10N2里头以造成-0.3eV的移动-相对于4.9eV而言。在此例中,镧系材料层26乃一氧化镧层,其构成厚度约0.1-1nm(1-10A),用以在此实施例中涵盖较高的能带宽度电压移动(-0.3eV)-相对于图1T中所示实施例而言。下面的表格设定了一些关于新结构101的特征,其描绘如图1U所示。
图1V描绘了另一集成电路产品102的实施例,其包含三个示例用的晶体管装置10N1、10P1、和10P2,其可随同不同的栅极结构来被形成,以便有三个不同的功函数和不同的临界电压。更具体言,于此示例中,此处揭示的方法导至功函数相移约-0.3eV,其乃基于装置10P2(4.6eV)出发去比较,其包含含镧栅极绝缘层22A,相较于10P1(4.9eV)而得,其具有传统高k栅极绝缘层22。于此实施例中,装置10N1(4.3eV)伴随高k栅极绝缘层高k栅极绝缘层22形成。下面的表格设定了一些关于新结构101的特征,其描绘如图1V所示。
图1W描绘了另一集成电路产品102的实施例,其包含两个示例用的晶体管装置10N1和10P1,其可随同不同的栅极结构来被形成,以便有两个不同的功函数和不同的临界电压。更具体言,于此示例中,此处揭示的方法导致功函数能带宽度相移约-0.6eV,其乃基于装置10N1(4.3eV)出发去比较,其包含含镧的栅极绝缘层22A,相较于10P1(4.9eV)而得,其具有传统高k栅极绝缘层22。于此例中,镧系材料层26乃一氧化镧层,其构成厚度约0.5-2nm,用以在此实施例中涵盖较高的能带宽度电压移动(-0.6eV)-相对于图1S-图1T中所示的另一实施例而言。下面的表格设定了一些关于新结构103的特征,其描绘如图1W所示。
重要地,此处揭示的方法同等地相容于形成NMOS和PMOS的替代栅极,如上所示。因此,此处揭示的方法有显著的价值,其既因关联于以CMOS技术形成集成电路产品。其余助益乃显而易见-对完整地阅读过本申请的本领域的技术人员而言。在如图1T-图1W所示的制造过程中,集成电路100-103可藉由实施数种传统的制造工艺完成,如形成导电接触于装置的源极区和漏极区处,和形成本产品的多道金属化层等。
上述揭示的特定的实施例仅为示例作用,其既因本发明可以不同的但等价的方法修改-当其方法对了解本发明好处的本领域的技术人员而言为显而易见时。例如,上述工艺步骤可用不同的顺序来执行。更进一步,没有限制被意图设于此处所示的建造细节和设计之上-除了如同权利要求书所述之外。因此显然地,上面所揭示的特定实施可被更动或修正,且其变化被视为落于此发明的精神范围内。请注意本发明所用词汇如“第一”,“第二”,“第三”,或“第四”以描述多种结构于此说明书者,仅为相对步骤/结构的简单代号,并不表示这些步骤/结构需以如代号所示的顺序执行。当然,以要求项的措词为准,该工艺的顺序描述可能被需要或不被需要。有鉴于此,本发明于此所请求的保护被列于权利要求书中。
Claims (12)
1.一种方法,用以形成NMOS晶体管和PMOS晶体管的替代栅极结构,该方法包含︰
执行至少一个蚀刻工艺,以去除该NMOS晶体管的牺牲栅极结构和该PMOS晶体管的牺牲栅极结构,从而定义NMOS栅极腔和PMOS栅极腔;
在该NMOS栅极腔和该PMOS栅极腔中形成高k栅极绝缘层;
在该高k栅极绝缘层上形成位于该NMOS和PMOS栅极腔内的镧系材料层;
执行至少一个加热工艺,以从该镧系材料层将材料驱入该高k栅极绝缘层,从而在每个该NMOS和该PMOS栅极腔内形成含镧高k栅极绝缘层;以及
执行至少一个工艺操作,以在该NMOS栅极腔中的该含镧高k栅极绝缘层上方形成第一栅极电极结构、以及在该PMOS栅极腔中的该含镧高k栅极绝缘层上方形成第二栅极电极结构。
2.根据权利要求1所述的方法,其中,该镧系材料层包含金属、氧化物、卤化物、碳化物或氮化物的一者。
3.根据权利要求1所述的方法,其中,执行该至少一个加热工艺包含于500-1200℃执行该至少一个加热工艺达不大于三秒的期间。
4.根据权利要求1所述的方法,其中,该镧系材料层是氧化镧层,而该高k栅极绝缘层是氧化铪层。
5.根据权利要求1所述的方法,其中,该含镧高k栅极绝缘层是铪镧氧化物(HfLaxOy)层。
6.一种方法,用以形成NMOS晶体管和PMOS晶体管的替代栅极结构,该方法包含︰
执行至少一个蚀刻工艺,以去除该NMOS晶体管的牺牲栅极结构和该PMOS晶体管的牺牲栅极结构,从而定义NMOS栅极腔和PMOS栅极腔;
在该NMOS栅极腔和该PMOS栅极腔中形成包含氧化铪的高k栅极绝缘层;
在该高k栅极绝缘层上形成位于该NMOS和PMOS栅极腔内的镧系材料层;
执行至少一个加热工艺,以从该氧化镧层将镧驱入该高k栅极绝缘层,从而在每个该NMOS和该PMOS栅极腔内形成铪镧氧化物栅极绝缘层;以及
执行至少一个工艺操作,以在该NMOS栅极腔中的该铪镧氧化物栅极绝缘层上形成第一栅极电极结构、以及在该PMOS栅极腔中的该铪镧氧化物栅极绝缘层上形成第二栅极电极结构。
7.根据权利要求6所述的方法,其中,执行该至少一个加热工艺包含于500-1200℃执行该至少一个加热工艺达不大于三秒的期间。
8.一种方法,用以形成NMOS晶体管装置和第一及第二PMOS晶体管装置的替代栅极结构,该方法包含︰
执行至少一个蚀刻工艺,以去除该NMOS晶体管的牺牲栅极结构和该第一及第二PMOS晶体管的牺牲栅极结构,从而定义NMOS栅极腔和第一及第二PMOS栅极腔;
在每个该NMOS栅极腔和该第一及第二PMOS栅极腔中形成高k栅极绝缘层;
形成图案化的硬遮罩层,以覆盖该第一PMOS栅极腔内的该高k栅极绝缘层,但暴露该NMOS栅极腔及该第二PMOS栅极腔内的该高k栅极绝缘层;
在该NMOS栅极腔中的该暴露的高k栅极绝缘层上、该第二PMOS栅极腔中的该暴露的高k栅极绝缘层上、及该图案化的硬遮罩层上方形成镧系材料层;
执行至少一个加热工艺,以从该镧系元素层将材料驱入该NMOS栅极腔中的该高k栅极绝缘层及该第二PMOS栅极腔中的该高k栅极绝缘层,从而在该NMOS栅极腔中形成第一含镧高k栅极绝缘层、及在该第二PMOS栅极腔中形成第二含镧高k栅极绝缘层;
执行至少一个蚀刻工艺,以去除该镧系材料层和该图案化的硬遮罩层;以及
执行至少一个工艺操作,以形成︰
第一栅极电极结构在该NMOS栅极腔中的该第一含镧高k栅极绝缘层上;
第二栅极电极结构在该第二PMOS栅极腔中的该第二含镧高k栅极绝缘层上;以及
第三栅极电极结构在该第一PMOS栅极腔中的该高k栅极绝缘层上。
9.根据权利要求8所述的方法,其中,该镧系元素层包含金属、氧化物、卤化物、碳化物或氮化物的一者。
10.根据权利要求8所述的方法,其中,执行该至少一个加热工艺包含于500-1200℃执行该至少一个加热工艺达不大于三秒的期间。
11.根据权利要求8所述的方法,其中,该镧系材料层是氧化镧层,而该高k栅极绝缘层是氧化铪层。
12.根据权利要求11所述的方法,其中,该含镧高k栅极绝缘层是铪镧氧化物(HfLaxOy)层。
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