WO2011137624A1 - 一种闪存器件及其制造方法 - Google Patents

一种闪存器件及其制造方法 Download PDF

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Publication number
WO2011137624A1
WO2011137624A1 PCT/CN2010/077296 CN2010077296W WO2011137624A1 WO 2011137624 A1 WO2011137624 A1 WO 2011137624A1 CN 2010077296 W CN2010077296 W CN 2010077296W WO 2011137624 A1 WO2011137624 A1 WO 2011137624A1
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Prior art keywords
region
doped well
flash memory
doped
layer
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PCT/CN2010/077296
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English (en)
French (fr)
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朱慧珑
骆志炯
尹海洲
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中国科学院微电子研究所
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Priority to US13/062,024 priority Critical patent/US20120280305A1/en
Publication of WO2011137624A1 publication Critical patent/WO2011137624A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/47—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/48—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components

Definitions

  • Flash memory device and manufacturing method thereof
  • the present invention relates to the field of semiconductor manufacturing technology, and in particular, to a flash memory device and a method of fabricating the same. Background technique
  • Flash Memory is a non-volatile memory integrated circuit developed from rewritable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM). It is one-time programmable ( OTP) equipment, its main advantages are fast working speed, small unit area, high integration, good reliability, etc., and it has broad application prospects in the fields of smart cards and microcontrollers.
  • the present invention provides a flash memory device comprising: a semiconductor substrate; a flash memory region formed on the semiconductor substrate; wherein the flash memory region includes: a first doped well, wherein the first doped well is divided into a first region and a second region by isolation, the second The region is doped with impurities opposite to the conductivity of the first doped well; a high-k gate dielectric layer formed on the first doped well; a metal layer formed on the high-k gate dielectric layer .
  • the flash memory device comprises a polysilicon layer in the metal gate stack of the transistor region, which realizes compatibility between the high-k dielectric metal gate and the rewritable flash memory, so that the high-k dielectric metal gate can be applied to the one-time In the programmable (OTP) device, the performance of the flash memory is improved.
  • the present invention also provides a method of fabricating a flash memory device, comprising the steps of: providing a semiconductor substrate, forming a flash memory region on the substrate, the flash memory region including a first doped well, the first The doped well is divided into a first region and a second region by isolation, the second region is doped with impurities opposite to the conductivity of the first doped well; formed on the first doped well High-k gate dielectric layer and metal layer.
  • the method of fabricating a flash memory in accordance with the present invention achieves compatibility with a high K dielectric metal gate process. Since the floating gate of the flash memory and the metal gate of the transistor use the same material and stacked structure, many of the same steps are used in the method of separately forming the flash memory and the transistor on the same substrate, which greatly simplifies the process flow. , to improve production efficiency and product consistency, thus providing favorable conditions for large-scale industrial production. DRAWINGS
  • FIG. 1 is a schematic diagram of a flash memory device in accordance with an embodiment of the present invention.
  • FIGS. 2 to 11 are cross-sectional views showing the structure of a device in an intermediate step of a method of fabricating a flash memory device in accordance with an embodiment of the present invention. detailed description
  • the flash memory device of the present invention uses a metal gate electrode layer in the transistor region, which not only overcomes the shortcomings of the metal gate erasing performance which is fabricated according to the high-k dielectric metal gate process, but also unifies the fabrication process of the flash memory and the transistor.
  • the manufacturing process is simplified, and the production efficiency is improved, so that the flash memory fabricated by the high-k dielectric metal gate process can be applied to the OTP device.
  • Fig. 1 shows a flash memory device of the present invention.
  • the device is exemplified by a bulk wafer substrate, which includes a substrate 300; a flash memory region 100 formed in the substrate 300, the flash memory region including a first doped well 101, the first doped well
  • the inner region is divided into a first region 101-1 and a second region 101-2 through an isolation region (STI as shown in FIG. 1), and the second region 101-2 is doped with the first An impurity having opposite conductivity of the doped well; a high-k gate dielectric layer 103 formed on the first doped well; and a metal layer 104 formed on the high-k gate dielectric layer.
  • the first doped well 101 is P-type doped, and the impurities in the second region 101-2 are P, AS or a combination of the two.
  • the impurity doped in the second region 101-2 is B, Ga, In or a combination thereof.
  • polysilicon 105 formed on the metal layer is further included.
  • An oxide layer 102 is also included over the substrate of the flash memory region.
  • the high-k gate dielectric layer 103 may include a Hf0 2 layer having a thickness of about 1-4 nm, and the metal layer 104 may include a TiN layer having a thickness of about 3-10 nm.
  • Hf0 2 layer having a thickness of about 1-4 nm
  • the metal layer 104 may include a TiN layer having a thickness of about 3-10 nm.
  • it may be TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x , MoN x , TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni 3 Si, Pt, Ru, Ir a combination of any one or more of Mo, Hf u, and RuO x .
  • a metal silicide layer 106 such as a NiSi layer, over the polysilicon 105 may also be included.
  • the flash memory device is compatible with the high-k metal gate process.
  • a buried oxide region 301 is formed on the semiconductor substrate, and the flash memory region is formed on the buried oxide region 301 as shown in FIG.
  • the device further includes a transistor region 200, the flash region 100 and a transistor region 200 is isolated by the isolation zone.
  • the transistor region 200 includes a second doped well 201, which may be doped with impurities having the same or opposite conductivity as the first doped well, and formed over the substrate of the transistor region High k gate dielectric layer 203 and metal layer 204.
  • the transistor region 200 also includes a source region and a drain region 207.
  • the transistor region further includes polysilicon 205 formed on the metal layer 204.
  • the high-k gate dielectric layer 203 may include an Hf0 2 layer having a thickness of about 2-4 nm, and the metal layer 204 may include a TiN layer having a thickness of about 3-10 nm.
  • a metal silicide layer 206 such as a NiSi layer, over the polysilicon 205 and the source and drain regions 207 may also be included.
  • the gate stacks of the flash and transistor regions can be formed during the same formation process to be compatible with the fabrication process of the high k gate stack.
  • the flash memory device further includes an interlayer dielectric layer overlying the device and a metal silicide contact over the source and drain regions of the transistor region, 206 as shown in FIG.
  • FIG. 1 a method of forming the flash memory device of the present invention as shown in FIG. 1 can be described in detail with reference to the accompanying drawings.
  • the present invention can form the flash memory device by using specific steps and processes different from those described below, but None of these may depart from the scope of the invention.
  • a semiconductor substrate 300 is provided.
  • a semiconductor substrate 300 is first provided, and at least two shallow trench isolations (STIs) are formed on the substrate 300 to isolate a flash region and a transistor region to be subsequently implanted and isolated in the flash memory region.
  • the first zone and the second zone formed are injected.
  • a flash memory region 100 is formed on the substrate, the flash memory region includes a first doped well 101, and the first doped well is divided into a first region 101-1 and a second by isolation.
  • the region 101-2 is doped with impurities opposite to the conductivity of the first doped well.
  • the substrate 300 may be well implanted to form the first doped well region 101.
  • the substrate of the entire flash memory region 100 may be ion implanted using a p-type dopant, so the flash memory region is also referred to below.
  • the second region 101-2 is ion implanted with a second type of impurity, wherein the second doping type is opposite to the first doping type, for example, using P, AS, or both a combination, for example, by making a composition mask, performing photolithography, and then performing The first doped well 101 is formed by ion implantation.
  • the present invention may optionally include a transistor region 200 including a second doped well 201 isolated from the first doped well by an isolation region,
  • the second doped well is doped with impurities opposite to the conductivity of the first doped well.
  • the substrate of the entire transistor region 200 may be ion implanted using an n-type dopant, and thus the transistor region is also below It is called the n-well region.
  • the first doped well of the flash region and the second doped well of the transistor region can be formed by photolithography and ion implantation. Of course, it can also be formed by other means, and these do not depart from the scope of protection of the present invention.
  • an oxide layer 102 may be formed on the substrate of the flash memory region, preferably having a thickness of from 1 to 20 nm.
  • a p-well region and an n-well region may be preferably formed in the substrate, and then an oxide layer 102 is formed on the substrate.
  • photolithography is performed to remove the oxide layer on the transistor region 200.
  • retain the oxide layer on the flash area as shown in Figure 3.
  • a photoresist pattern is formed again, and an As or P element is implanted into the second region 101-2 in the p well region 101 in the direction of the angle A. The photoresist is then removed.
  • the oxide layer 102 is not necessary, that is, the step of forming the oxide layer 102 may be omitted in some processes.
  • the addition of an oxide layer 102 can effectively reduce the magnitude of the leakage current.
  • a high-k gate dielectric layer 103 and a metal layer 104 are formed on the first doped well 101, and optionally a polysilicon layer 105 may also be formed.
  • the high-k gate dielectric layer 103, the metal layer 104, and the polysilicon layer 105 may be formed on the entire substrate.
  • the high-k gate dielectric layer 103 may have Hf0 2 and a thickness of about 2-4 nm, and the metal in the metal layer 104 may be ⁇ With TiN, the thickness is about 3-10 nm.
  • the metal layer 104 may be, for example, TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x , MoN x , TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi x , Ni 3 Si, Pt, A combination of any one or more of Ru, Ir, Mo, HfRu, RuO x . Thereafter, as shown in FIGS.
  • a photoresist pattern is formed, and the polysilicon layer 105, the metal layer 104, and the high-k gate dielectric layer 103 are etched by a reactive ion etching process (RIE). The photoresist is then removed.
  • RIE reactive ion etching process
  • a gate stack of transistor regions may be simultaneously formed in the step of forming a gate stack of the above-described flash region.
  • step 4 may be performed thereafter:
  • a source region and a drain region 207 are formed in the transistor region 200 of the substrate 300.
  • source and drain extension implants are first formed.
  • sidewalls 108 and 208 are formed on sidewalls of the gate stack of the flash region 100 and the transistor region 200, respectively, followed by source-drain implantation, followed by source-drain annealing to activate dopant ions to form source and drain regions. Area.
  • step 5 may be performed after the source and drain regions are formed: a metal silicide layer, such as NiSi, is formed on the source and drain of the transistor region 200 and on the gate stack of the flash region and the gate stack of the transistor region. Then, a subsequent processing is performed on the device to cover the device to form an interlayer dielectric layer, and a metal contact region is formed over the source region and the drain region of the transistor region, as shown in FIG.
  • a metal silicide layer such as NiSi
  • the second region 101-2 serves as a control gate of the flash memory device
  • the polysilicon layer 105 serves as a floating gate
  • the first region 101-1 serves as a source/drain region.
  • the source/drain contact holes can be made on both sides of the floating gate, on the 101-1 of the flash memory area, and the gate contact holes can be made on the 101-2, thereby realizing the memory function of the flash memory device, that is, The erasing of the charge on the floating gate can be achieved by changing the voltage of the control gate.
  • the polysilicon having good erasing performance is applied to the flash memory structure fabricated by the high-k gate dielectric metal gate process, so that the flash memory structure including the high-k gate dielectric metal gate can also be applied to the OTP device, Strong compatibility.
  • the flash memory and the transistor can be formed separately on the same substrate material by the same steps, which greatly simplifies the process complexity and improves the production efficiency of the semiconductor device.

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Description

一种闪存器件及其制造方法
技术领域
本发明涉及半导体制造技术领域， 特别涉及一种闪存器件及其制造方 法。 背景技术
随着计算机技术的飞速发展， 对半导体存储器件的性能也提出了更高 的要求。 用于存储数据的半导体存储器件可以分为挥发性存储器件和非挥 发性存储器件两大类。 挥发性存储器件在供电中断后将失去存储数据， 而 非挥发性存储器件在供电中断后仍然能够保留其中的存储数据。闪存（ Flash Memory ) 是一种从可擦写可编程只读存储器 （ EPROM ) 和电可擦写可编 程只读存储器 （EEPROM )发展而来的非挥发性存储集成电路， 属于一次 性可编程 （OTP )设备， 其主要优点是工作速度快、 单元面积小、 集成度 高、 可靠性好等， 在智能卡、 微控制器等领域具有广泛的应用前景。
近年来， 在半导体制作工艺中逐渐开始釆用以 Hf 元素为基础的高 K 材料代替以往的二氧化硅作为栅介质层， 不仅极大地提高了半导体器件的 工作性能， 还减小了电流浪费和能量损失， 使得半导体制作工艺取得了巨 大进步。
但是， 当传统的利用互补金属氧化物 （CMOS ) 制作成闪存的工艺中 引入高 K介质金属栅工艺时， 由于在高 K介质金属栅工艺中形成的金属栅 中存储的数据不易被电流擦除， 因此极大地影响了闪存的可擦写性能， 使 得这种闪存无法重复多次读写， 从而使高 K介质金属栅工艺应用到一次可 编程 （OTP )设备的制作工艺上时遇到了很大的挑战。 发明内容
针对现有技术的不足， 本发明的目的是要提供一种与高 K介质金属栅 工艺相兼容的半导体结构及其制造方法。
为了实现上述目的， 本发明提供了一种闪存器件， 包括： 半导体衬底； 形成于所述半导体衬底上的闪存区； 其中， 所述闪存区包括： 第一掺杂阱， 所述第一掺杂阱内通过隔离区分为第一区和第二区， 所述第二区内掺杂了 与所述第一掺杂阱的导电性能相反的杂质； 形成于所述第一掺杂阱上的高 k栅介质层； 形成于所述高 k栅介质层上的金属层。
本发明的有益效果是， 该闪存器件在晶体管区的金属栅堆叠中包括多 晶硅层， 实现了高 K介质金属栅与可擦写闪存之间的兼容， 使得高 K介质 金属栅能够应用到一次性可编程（OTP )设备中， 提高了闪存的工作性能。
相应地， 本发明还提供了一种闪存器件的制造方法， 包括以下步骤： 提供半导体衬底， 在所述衬底上形成闪存区， 所述闪存区包括第一掺杂阱， 所述第一掺杂阱内通过隔离区分为第一区和第二区， 所述第二区内掺杂了 与所述第一掺杂阱的导电性能相反的杂质； 在所述第一掺杂阱上形成高 k 栅介质层和金属层。
根据本发明的制造闪存的方法实现了与高 K介质金属栅工艺的互相兼 容。 由于闪存的浮栅和晶体管的金属栅极釆用相同的材料和层叠结构， 因 此在同一个衬底上分别形成闪存和晶体管的方法中将会釆用很多相同的步 骤， 极大地简化了工艺流程， 提高了生产效率和产品的一致性， 从而为大 规模工业生产提供了有利条件。 附图说明
本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的描 述中将变得明显和容易理解， 其中：
图 1是根据本发明的实施例的闪存器件的示意图；
图 2至图 11是根据本发明的实施例的闪存器件的制造方法中间步骤的 器件结构剖面图。 具体实施方式
下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功 能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发 明， 而不能解释为对本发明的限制。
本发明的闪存器件在晶体管区使用金属栅电极层， 不但能够克服按照 高 K介质金属栅工艺制作的金属栅极电擦写性能不理想的缺点， 而且可以 将闪存和晶体管的制作工艺统一起来， 简化了制作步骤， 提高了生产效率， 使得由高 K介质金属栅工艺制作而成的闪存能够应用于 OTP设备中。为了 能够更清楚地理解本发明的思想， 以下将以具体实施例进行详细介绍： 图 1示出的是本发明的闪存器件。该器件以体硅 (bulk wafer)衬底为例， 其包括衬底 300; 形成于衬底 300中的闪存区 100 , 所述闪存区包括第一掺 杂阱 101 ,所述第一掺杂阱内通过隔离区（如图 1所述的 STI, 浅沟槽隔离） 分为第一区 101-1和第二区 101-2, 所述第二区 101-2内掺杂了与所述第一 掺杂阱的导电性能相反的杂质； 形成于所述第一掺杂阱上的高 k栅介质层 103 ; 形成于所述高 k栅介质层上的金属层 104。
特别地， 所述第一掺杂阱 101为 P型掺杂， 第二区 101-2内的杂质为 P、 AS或者是二者的组合。 特别地， 如果所述第一掺杂阱 101为 N型掺杂， 则第二区 101-2内掺杂的杂质为 B、 Ga、 In或者是它们的组合。
可选地， 还包括形成于所述金属层上的多晶硅 105。 在所述闪存区的 衬底上方还包括氧化物层 102。
所述高 k栅介质层 103可以包括 Hf02层，厚度约为 l-4nm,金属层 104 可以包括 TiN层， 厚度约为 3-10nm。 当然， 本领域技术人员可以根据实际 需要选用上述材料的等同替代材料， 本发明并未对此做出限制。 例如可以 是 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax、 MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 Hf u、 RuOx中任一种或多种的组合。 特别地还可以包括在所述多晶硅 105 之上的金属硅化物层 106 , 例如 NiSi层。
由于金属层 104的存在， 从而使得闪存器件能够与高 k金属栅工艺兼 容。
在本发明的另一个实施例中， 所述半导体衬底上形成有埋氧区 301 , 所述闪存区形成于所述埋氧区 301上， 如图 11所示。
特别地， 所述器件还包括晶体管区 200, 所述闪存区 100和晶体管区 200由隔离区隔离。 所述晶体管区 200包括了第二掺杂阱 201 , 所述第二掺 杂阱可以掺杂与第一掺杂阱的导电性能相同或相反的杂质， 以及形成于所 述晶体管区的衬底上方的高 k栅介质层 203和金属层 204。 所述晶体管区 200还包括源极区和漏极区 207。 可选地， 所述晶体管区还包括形成于所述 金属层 204上的多晶硅 205。
所述高 k栅介质层 203可以包括 Hf02层，厚度约为 2-4nm,金属层 204 可以包括 TiN层， 厚度约为 3-10nm。 当然， 本领域技术人员可以根据实际 需要选用上述材料的等同替代材料， 本发明并未对此做出限制。 特别地还 可以包括在所述多晶硅 205和源极区、漏极区 207之上的金属硅化物层 206 , 例如 NiSi层。
特别地，所述闪存区和晶体管区的栅堆叠能够在同一形成过程中形成， 以便与高 k栅堆叠的制造工艺兼容。 可选地， 所述闪存器件还包括覆盖所 述器件的层间介质层和在所述晶体管区的源极区和漏极区上方的金属硅化 物接触， 如图 10所示的 206。
以下将结合附图详细介绍能够制作如图 1 所示的本发明所示的闪存器 件的形成方法， 当然本发明可以釆用不同于以下描述的具体的步骤和工艺 来形成所述闪存器件， 但这些均不脱离本发明的保护范围。
首先， 在步骤 1 : 提供半导体衬底 300。 按照图 2所示， 首先提供半导 体衬底 300, 并在衬底 300上形成至少两个浅沟槽隔离 （STI ) , 以隔离随 后将要注入形成的闪存区与晶体管区并隔离在闪存区中将要注入形成的第 一区和第二区。
而后， 在步骤 2, 在所述衬底上形成闪存区 100, 所述闪存区包括第一 掺杂阱 101 , 所述第一掺杂阱内通过隔离区分为第一区 101-1 和第二区 101-2 , 所述第二区 101-2内掺杂了与所述第一掺杂阱的导电性能相反的杂 质。 具体来说， 可以对衬底 300进行阱注入以形成第一掺杂阱区 101 , 例 如可以使用 p型掺杂剂对整个所述闪存区 100的衬底进行离子注入， 因此 闪存区以下也称 p阱区， 而后釆用第二类型的杂质对所述第二区 101-2进 行离子注入， 其中所述第二掺杂类型与第一掺杂类型相反， 例如使用 P、 AS或者是二者的组合， 例如可以通过制作构图掩膜、 进行光刻、 而后进行 离子注入的方式来形成第一掺杂阱 101。
可选地， 为了与晶体管区的工艺流程相兼容， 本发明可以可选择地包 括晶体管区 200 , 所述晶体管区包括与所述第一掺杂阱通过隔离区隔离的 第二掺杂阱 201 , 所述第二掺杂阱掺杂了与第一掺杂阱的导电性能相反的 杂质， 例如可以使用 n型掺杂剂对整个所述晶体管区 200的衬底进行离子 注入， 因此晶体管区以下也称 n阱区。
可以釆用光刻和离子注入的方式形成闪存区的第一掺杂阱和晶体管区 的第二掺杂阱。 当然也可以通过其他方式来形成， 这些均不脱离本发明的 保护范围。
可选地， 还可以在所述闪存区的衬底上形成氧化物层 102 , 厚度优选 为 l-20nm。 具体来说， 可以首选在衬底中形成 p阱区和 n阱区， 而后在衬 底上形成氧化物层 102 , 如图 2所示， 进行光刻以去除晶体管区 200上的 氧化物层， 并保留闪存区上的氧化物层， 如图 3所示。 而后， 如图 4所示， 再次形成光刻胶图形， 按照角度 A的方向注入 As或 P元素到 p阱区 101 中的第二区 101-2。 而后移除光刻胶。
在这个步骤中， 氧化物层 102不是必须的， 即在某些工艺上也可以省 略形成该氧化物层 102的步骤。 增加一层氧化物层 102能够有效减小漏电 流的大小。
此后， 在步骤 3 , 在所述第一掺杂阱 101上形成高 k栅介质层 103和 金属层 104 , 可选地还可以形成多晶硅层 105。 可以首先在整个衬底上形成 高 k栅介质层 103、 金属层 104以及多晶硅层 105 , 高 k栅介质层 103可以 釆用 Hf02, 厚度约为 2-4nm, 金属层 104中的金属可以釆用 TiN, 厚度约 为 3-10nm。金属层 104例如可以是 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax、 MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx中任一种或多种的组合。 此后， 如图 6和图 7所示， 形成光刻胶图形， 釆用反应离子刻蚀工艺 （RIE )蚀刻 多晶硅层 105、 金属层 104和高 k栅介质层 103。 然后移除光刻胶。
此外， 与所述晶体管区的工艺流程相兼容地， 可以在形成上述闪存区 的栅堆叠的步骤中， 同时形成晶体管区的栅堆叠。 以上已经结合附图描述了根据本发明的实施例。 可选择地， 此后可以 进行步骤 4: 如图 8和图 9所示， 在衬底 300的晶体管区 200中形成源极 区和漏极区 207。 例如， 首先形成源、 漏延伸注入。 然后在闪存区 100和 晶体管区 200的栅堆叠的侧壁分别形成侧墙 108和 208 , 接着进行源漏注 入， 再接着进行源漏退火工艺以激活掺杂离子， 以形成源极区和漏极区。
可选地， 可以在源漏极区形成后进行步骤 5: 在晶体管区 200 的源极 和漏极上以及在闪存区的栅堆叠和晶体管区的栅堆叠上形成金属硅化物 层， 例如 NiSi。 而后， 对器件进行后续加工工艺， 覆盖所述器件形成层间 介电层， 并在晶体管区的源极区和漏极区上方形成金属接触区， 如图 10所 示。
在根据本发明实施例得到的闪存器件中， 第二区 101-2作为闪存器件 的控制栅极， 多晶硅层 105作为浮置栅极， 第一区 101-1作为源 /漏区。
此外， 如图 9在浮置栅极两侧、 闪存区的 101-1上可以做源 /漏接触孔， 以及在 101-2 上可以做栅极接触孔， 从而实现闪存器件的存储功能， 即通 过改变控制栅极的电压能够实现浮置栅极上电荷的擦写。
本发明的实施例一中把擦写性能比较好的多晶硅应用到高 K栅介质金 属栅工艺制作的闪存结构中， 使得包含高 K栅介质金属栅的闪存结构也能 够应用到 OTP设备中， 具有较强的兼容性。 此外， 闪存和晶体管可以在同 一个衬底材料上釆用相同的步骤来分别形成，极大地简化了工艺的复杂性， 提高了半导体器件的生产效率。
以上所披露的仅为本发明的优选实施例， 当然不能以此来限定本发明 的权利保护范围。 可以理解， 依据本发明所附权利要求中限定的实质和范 围所作的等同变化， 仍属于本发明所涵盖的范围。

Claims

权 利 要 求
1、 一种闪存器件， 包括：
半导体衬底； 以及闪存区， 位于所述半导体衬底上；
其中， 所述闪存区包括：
第一掺杂阱，所述第一掺杂阱内通过隔离区分为第一区和第二区， 所述第二区内掺杂了与所述第一掺杂阱的导电性能相反的杂质；
高 k栅介质层， 形成于所述第一掺杂阱上； 以及
金属层， 形成于所述高 k栅介质层上。
2、根据权利要求 1所述的器件，还包括形成于所述金属层上的多晶硅 层。
3、 根据权利要求 1 所述的器件， 其中所述第一掺杂阱为 P型掺杂， 所述第二区内掺杂的杂质为 P、 AS或者是二者的组合。
4、 根据权利要求 1所述的器件， 其中所述第一掺杂阱为 N型掺杂， 所述第二区内掺杂的杂质为 B、 Ga、 In或者是它们的组合。
5、 根据权利要求 1 所述的器件， 其中所述金属层包括： TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax、 MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 魔 u、 RuOx 中的一种或多种的组合。
6、根据权利要求 1所述的器件，其中在所述衬底和高 k栅介质层之间 还包括氧化物层。
7、 根据权利要求 1所述的器件， 其中所述半导体衬底为体硅。
8、根据权利要求 1所述的器件，其中所述半导体衬底上形成有埋氧区， 所述闪存区形成于所述埋氧区上。
9、根据权利要求 1至 8中任一项所述的器件， 还包括： 形成于所述半 导体衬底上的晶体管区。
10、 根据权利要求 9所述的器件， 所述晶体管区包括：
与所述第一掺杂阱通过隔离区隔离的第二掺杂阱；
形成于所述第二掺杂阱上的栅堆叠和所述栅堆叠两侧的源 /漏区，所述 栅堆叠包括高 k栅介质层和所述高 k栅介质层上的金属层。
11、 根据权利要求 9所述的器件， 所述第二掺杂阱掺杂了与第一掺杂 阱的导电性能相反的杂质。
12、 根据权利要求 10所述的器件， 所述栅堆叠还包括：
形成于所述金属层上的多晶硅层。
13、 一种闪存器件的制造方法， 其特征在于， 包括以下步骤： 提供半导体衬底，
在所述衬底上形成闪存区， 所述闪存区包括第一掺杂阱， 所述第一掺 杂阱内通过隔离区分为第一区和第二区， 所述第二区内掺杂了与所述第一 掺杂阱的导电性能相反的杂质；
在所述第一掺杂阱上依次形成高 k栅介质层和金属层。
14、 根据权利要求 13所述的方法， 其中所述形成闪存区的步骤包括： 在所述衬底中形成隔离区以隔离第一区和第二区， 釆用第一类型的杂 质对所述第一区和第二区进行离子注入以形成第一掺杂阱， 以及
釆用第二类型的杂质对所述第二区进行离子注入， 其中所述第一掺杂 类型与第二掺杂类型相反。
15、 根据权利要求 13所述的方法， 还包括在所述闪存区的金属层上形 成多晶硅层的步骤。
16、 根据权利要求 13所述的方法， 其中所述第一掺杂阱为 P型掺杂， 所述第二区内的杂质为卩、 AS或者是二者的组合。
17、 根据权利要求 13所述的方法， 其中所述第一掺杂阱为 N型掺杂， 所述第二区内的杂质为 8、 Ga、 In或者是它们的组合。
18、 根据权利要求 13所述的方法， 其中所述金属层包括： TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTax、 MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 魔 u、 RuOx 中的一种或多种的组合。
19、 根据权利要求 13所述的方法， 在所述第一掺杂阱上形成高 k栅介 质层的步骤之前还包括： 在所述闪存区上形成氧化物层的步骤。
20、 根据权利要求 13所述的方法， 其中所述半导体衬底为体硅。
21、根据权利要求 13所述的方法，其中所述半导体衬底上形成有埋氧 区， 所述闪存区形成于所述埋氧区上。
22、 根据权利要求 13-21 中任一项所述的方法， 还包括： 在所述半导 体衬底上形成晶体管区的步骤。
23、根据权利要求 22所述的方法，其中形成所述晶体管区的步骤包括： 在衬底上形成第二掺杂阱， 所述第二掺杂阱通过隔离区与所述第一掺 杂阱隔离；
在所述第二掺杂阱上形成栅堆叠和所述栅堆叠两侧的源 /漏区， 所述栅 堆叠包括高 k栅介质层和所述高 k栅介质层上的金属层。
24、 根据权利要求 23所述的方法， 所述第二掺杂阱掺杂了与第一掺杂 阱的导电性能相反的杂质
25、 根据权利要求 23所述的方法， 其中形成栅堆叠的步骤还包括： 在 所述金属层上形成多晶硅层的步骤。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9227001B2 (en) 2010-10-07 2016-01-05 Everheart Systems Inc. High efficiency blood pump
US9018691B2 (en) * 2012-12-27 2015-04-28 Ememory Technology Inc. Nonvolatile memory structure and fabrication method thereof
US10294944B2 (en) 2013-03-08 2019-05-21 Everheart Systems Inc. Flow thru mechanical blood pump bearings
US10276726B2 (en) * 2016-05-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Non-volatile memory cell and non-volatile memory
CN112636727A (zh) 2019-10-08 2021-04-09 长鑫存储技术有限公司 数据的存储比较方法、存储比较电路装置及半导体存储器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114677A (zh) * 2006-07-27 2008-01-30 三星电子株式会社 非易失半导体存储器装置及其制造方法
US20090243029A1 (en) * 2008-03-26 2009-10-01 Anderson Brent A Method, structure and design structure for customizing history effects of soi circuits
US20090256211A1 (en) * 2008-04-10 2009-10-15 International Business Machines Corporation Metal gate compatible flash memory gate stack

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4530464B2 (ja) * 2000-03-09 2010-08-25 ルネサスエレクトロニクス株式会社 半導体集積回路
JP2002009173A (ja) * 2000-06-26 2002-01-11 Toshiba Corp 半導体装置の製造方法
JP2004200553A (ja) * 2002-12-20 2004-07-15 Fujitsu Ltd 半導体装置及びその製造方法
JP4171695B2 (ja) * 2003-11-06 2008-10-22 株式会社東芝 半導体装置
US7164161B2 (en) * 2003-11-18 2007-01-16 Micron Technology, Inc. Method of formation of dual gate structure for imagers
US7138680B2 (en) * 2004-09-14 2006-11-21 Infineon Technologies Ag Memory device with floating gate stack
DE102005022129B4 (de) * 2005-05-12 2015-06-18 Infineon Technologies Ag Feldeffekttransistor und Verfahren zum Herstellen eines Feldeffekttransistors
JP4719035B2 (ja) * 2006-03-13 2011-07-06 株式会社東芝 不揮発性半導体メモリ装置及びその製造方法
KR100870289B1 (ko) * 2007-02-09 2008-11-25 주식회사 하이닉스반도체 플래시 메모리 소자 및 그의 제조 방법
KR20080076074A (ko) * 2007-02-14 2008-08-20 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법
US7709924B2 (en) * 2007-07-16 2010-05-04 International Business Machines Corporation Semiconductor diode structures
JP2009081203A (ja) * 2007-09-25 2009-04-16 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114677A (zh) * 2006-07-27 2008-01-30 三星电子株式会社 非易失半导体存储器装置及其制造方法
US20090243029A1 (en) * 2008-03-26 2009-10-01 Anderson Brent A Method, structure and design structure for customizing history effects of soi circuits
US20090256211A1 (en) * 2008-04-10 2009-10-15 International Business Machines Corporation Metal gate compatible flash memory gate stack

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