CN104321867A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN104321867A
CN104321867A CN201380026637.1A CN201380026637A CN104321867A CN 104321867 A CN104321867 A CN 104321867A CN 201380026637 A CN201380026637 A CN 201380026637A CN 104321867 A CN104321867 A CN 104321867A
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wiring
semiconductor chip
grid
grid wiring
semiconductor device
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CN104321867B (zh
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道越久人
平方宣行
野津浩史
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Abstract

一种半导体器件，包括：至少一个半导体芯片、连接至该至少一个半导体芯片的栅极布线、连接至该至少一个半导体芯片的第一布线以及连接至该至少一个半导体芯片的第二布线。第一和第二布线沿栅极布线延伸。第一布线布置在栅极布线和第二布线之间。第一布线是最接近栅极布线的布线。栅极布线的与第一布线相对的第一部分短于栅极布线的与第二布线相对的第二部分。

Description

半导体器件
技术领域
本发明涉及一种半导体器件。
背景技术
已知作为半导体器件的一个实例是一种配备有MOSFET的半导体芯片的半导体器件(参见专利文献1)。在这种半导体器件中，安装在管芯焊盘上的半导体芯片通过栅极线连接至栅极引线，并且通过多个源极线连接至源极引线。
引证专利文献列表
专利文献
[专利文献1]日本专利公布No.4746061
发明内容
技术问题
在上述半导体中，最接近栅极线的源极线具有等于和长于其他源极线的长度。因此，当流过多个源极线的电流随时间变化时，由于电磁效应，栅极线更易受从多个源极线接收的互感的影响。因此，在上述半导体器件中，施加至栅极线的栅电压更随时间波动。
本发明的一个目的是提供一种半导体器件，其能抑制栅电压随时间波动。
问题的解决方法
根据本发明一个方面的半导体器件包括至少一个半导体芯片、连接至该至少一个半导体芯片的栅极布线、连接至该至少一个半导体芯片的第一布线以及连接至该至少一个半导体芯片的第二布线，其中第一和第二布线沿栅极布线延伸，其中第一布线布置在栅极布线和第二布线之间，其中第一布线是最接近栅极布线的布线，并且其中栅极布线的与第一布线相对的第一部分短于栅极布线的与第二布线相对的第二部分。栅极布线的第一部分可以是位于栅极布线和从第一布线的给定点引出至栅极布线的垂线之间的交点处的部分。栅极布线的第二部分可以是位于栅极布线和从第二布线的给定点引出至栅极布线的垂线之间的交点处的部分。
当流过第一和第二布线的电流随时间变化时，因为电磁效应，因此栅极布线易受从第一和第二布线接收的互感的影响。因此，半导体芯片的栅电压随时间波动。互感由栅极布线和第一和第二布线之间的距离以及栅极布线的与第一和第二布线相对的部分的长度决定。随着栅极布线和第一和第二布线之间的距离更短，互感变得更大。随着栅极布线的与第一和第二布线相对的部分的长度更长，互感变得更大。
在半导体器件中，栅极布线的与最接近栅极布线的第一布线相对的第一部分的长度d1短于栅极布线的与第二布线相对的第二部分的长度d2。因此，由于电磁效应而由栅极布线从第一布线接收的互感更小，由此抑制栅电压随时间波动。
该至少一个半导体芯片可以包括多个半导体芯片；该多个半导体芯片可以沿第一方向布置；并且，相对于在彼此相邻的半导体芯片之间的沿与第一方向垂直的第二方向延伸的轴，在一侧上的栅极布线、第一布线以及第二布线可以与另一侧上的栅极布线、第一布线以及第二布线反转地布置。
这均匀化了由半导体芯片的栅极布线由于电磁效应而从第一和第二布线接收的互感的影响，由此降低在彼此相邻的半导体芯片之间的栅电压的波动。
至少一个半导体芯片可以由包含宽带隙半导体的材料制成。
与由硅制成的半导体芯片相比，这允许更大的电流流过第一和第二布线。因此，在宽带隙半导体中，栅电压趋于随时间更大地波动，这通过抑制栅电压随时间波动而产生更大的效果。
半导体器件进一步包括连接至栅极布线的布线图案。
在这种情况下，将半导体芯片和布线图案之间的距离设定得更小可以降低栅极布线的长度。这使得栅极布线较不易受由于电磁效应而从第一和第二布线接收的互感的影响，由此进一步限制栅电压随时间波动。
半导体器件进一步包括电连接至栅极布线的第一引线、电连接至第一和第二布线的第二引线以及具有用于安装至少一个半导体芯片的芯片安装表面的管芯焊盘。
对于配备有引线的半导体器件来说，典型的困难是将栅极布线与第一和第二布线充分分开。因此，在配备有引线的半导体器件中，栅电压趋于更随时间波动，这通过抑制栅电压随时间波动而产生更大的效果。
发明的有益效果
根据本发明，可以提供能抑制栅电压随时间波动的半导体器件。
附图说明
图1是示意性图示根据第一实施例的半导体器件的平面图；
图2是图示在根据第一实施例的半导体器件中的栅电压随时间波动的实例的图表；
图3是示意性图示用于参考的半导体器件的平面图；
图4是图示在用于参考的半导体器件中的栅电压随时间波动的实例的图表；
图5是示意性图示根据第二实施例的半导体器件的平面图；以及
图6是示意性图示用于参考的半导体器件的平面图。
具体实施方式
在下文中，将参考附图详细解释本发明的实施例。在附图的说明中，将以相同的附图标记表示相同或等效的组成部分，同时省略它们的重复说明。图1、3、5和6图示XYZ正交坐标系。
第一实施例
图1是示意性图示根据第一实施例的半导体器件的平面图。图1中图示的半导体器件10是树脂密封型半导体器件。半导体器件10包括多个半导体芯片14a至14d。半导体芯片14a至14d可以并联连接。
半导体器件10可以配备有管芯焊盘12，管芯焊盘12具有用于安装半导体芯片14a至14d的芯片安装表面12a。管芯焊盘12可以电连接至半导体芯片14a至14d。管芯焊盘12例如形成为板状。芯片安装表面12a例如是矩形的。用于管芯焊盘12的材料的实例包括诸如铜(Cu)和铜合金的金属。管芯焊盘12可以形成有在厚度方向上通过其贯穿的贯通孔26。贯通孔26例如是当利用螺钉将半导体器件10固定至另一构件(例如热沉)时用于通过其插入螺钉的孔。
半导体芯片14a至14d在预定位置处安装在芯片安装表面12a上。半导体芯片14a至14d的实例包括诸如双极晶体管、MOS-FET以及绝缘栅双极晶体管(IGBT)的晶体管以及诸如pn结二极管和肖特基势垒二极管的二极管。半导体芯片14a至14d可以通过接合层安装在芯片安装表面12a上，接合层由包括含铅金属焊料、无铅金属焊料、导电树脂等的材料构成。用于半导体芯片14a至14d的材料的实例包括宽带隙半导体以及诸如硅的其他半导体。宽带隙半导体具有大于硅的带隙。宽带隙半导体的实例包括碳化硅(SiC)、氮化镓(GaN)以及金刚石。
半导体芯片14a至14d的每一个都可以具有栅极电极焊盘GP以及电极焊盘SP。栅极电极焊盘GP可以形成在半导体芯片14a至14d的主面上的一个端部。栅极配线GL可以连接至栅极电极焊盘GP。电极焊盘SP可以形成在半导体芯片14a至14d的主面上的没有栅极电极焊盘GP和栅极配线GL的区域中。
当半导体芯片14a至14d包括MOS-FET时，电极焊盘SP对应于源极电极焊盘。当半导体芯片14a至14d包括IGBT时，电极焊盘SP对应于发射极电极焊盘。半导体芯片14a至14d的整个背面例如都形成有诸如漏极电极焊盘或集电极电极焊盘的另一电极焊盘。
栅极布线30a、第一布线32a以及第二布线34a连接至半导体芯片14a。栅极布线30a可以连接至半导体芯片14a的栅极电极焊盘GP。第一布线32a和第二布线34a可以连接至半导体芯片14a的电极焊盘SP。类似地，栅极布线30b至30d可以分别连接至半导体芯片14b至14d的栅极电极焊盘GP。第一布线32b至32d可以分别连接至半导体芯片14b至14d的电极焊盘SP。第二布线34b至34d可以分别连接至半导体芯片14b至14d的电极焊盘SP。第一布线32a至32d以及第二布线34a至34d是用于将电流供应至半导体芯片14b至14d的布线。栅极布线30a至30d是用于开关流过第一布线32a至32d以及第二布线34a至34d的布线。第一布线32a至32d以及第二布线34a至34d可以分散布置在电极焊盘SP上，以便抑制电流集中。
第一布线32a至32d以及第二布线34a至34d沿栅极布线30a至30d延伸。栅极布线30a至30d、第一布线32a至32d以及第二布线34a至34d可以沿XY平面延伸。第一布线32a至32d布置在栅极布线30a至30d与第二布线34a至34d之间。例如，第一布线32a布置在栅极布线30a和第二布线34a之间。第一布线32a至32d分别是最接近栅极布线30a至30d的布线。栅极布线30a至30d的与第一布线32a至32d相对的第一部分30x的长度d1短于栅极布线30a至30d的与第二布线34a至34d相对的第二部分30y的长度d2。长度d2可以是长度d1的1.2倍或更大。可以通过在与半导体芯片14a至14d的主面垂直的Z方向上观察第一布线32a至32d以及第二布线34a至34d来测量d1和d2的长度。栅极布线30a至30d的第一部分30x可以是位于栅极布线30a至30d与从第一布线32a至32d的给定点引出至栅极布线30a至30d的垂线之间的交点处的部分。栅极布线30a至30d的第二部分30y可以是位于栅极布线30a至30d与从第二布线34a至34d的给定点引出至栅极布线30a至30d的垂线之间的交点处的部分。
半导体芯片14a至14d可以沿X方向(第一方向)布置。沿Y方向(与第一方向垂直的第二方向)延伸的轴Ax布置在彼此相邻的半导体芯片14a至14d之间。相对于Ax轴，一侧上的栅极布线30a至30d、第一布线32a至32d以及第二布线34a至34d可以与另一侧上的栅极布线30a至30d、第一布线32a至32d以及第二布线34a至34d反转地布置。相对于Ax轴，一侧上的栅极电极焊盘GP和电极焊盘SP也可以与另一侧上的栅极电极焊盘GP和电极焊盘SP反转地布置。例如，栅极布线30a可以相对于Ax轴布置在与栅极布线30b对称的位置处。
半导体器件10可以包括第一引线18、第二引线20以及第三引线16。每个均沿Y方向延伸的引线16、18、20沿X方向布置成一排。引线16位于引线18、20之间。引线16、18、20以及管芯焊盘12可以构成引线框架。半导体器件10例如是用于电源等的功率半导体器件。用于半导体器件10的封装形式的实例包括典型的TO系列。TO系列的实例包括TO-247、TO-220、TO-263(D2-PAK)以及TO-252(D-PAK)。
引线18电连接至栅极布线30a至30d。引线20电连接至第一布线32a至32d以及第二布线34a至34d。引线16的内端部机械地整体地连结至管芯焊盘12。因为管芯焊盘12是导电的，因此引线16和管芯焊盘12彼此电连接。用于引线16的材料的实例包括与管芯焊盘12的材料相同的材料。
当半导体芯片14a至14d包括MOS-FET时，引线16、18和20分别对应于漏极、栅极以及源极电极端子。当半导体芯片14a至14d包括IGBT时，引线16对应于集电极电极端子，引线18对应于栅极电极端子且引线20对应于发射极电极端子。用于引线18、20的材料的实例包括诸如铜和铜合金的金属。
半导体器件10可以包括连接至栅极布线30a至30d的布线图案36，以及布置在管芯焊盘12和布线图案36之间的绝缘构件38。布线图案36通过布线40连接至引线18。绝缘构件38在Z方向上置于管芯焊盘12和布线图案36之间。绝缘构件38例如是绝缘衬底或绝缘层。用于绝缘构件38的材料的实例包括诸如环氧树脂的树脂和陶瓷。管芯焊盘12、绝缘构件38以及布线图案36可以利用粘合剂彼此接合在一起。
半导体器件10可以包括连接至第一布线32a至32d和第二布线34a至34d的布线图案42，以及布置在管芯焊盘12和布线图案42之间的绝缘构件44。布线图案42通过多个布线46连接至引线20。绝缘构件44在Z方向上置于管芯焊盘12和布线图案42之间。绝缘构件44例如是绝缘衬底或绝缘层。用于绝缘构件44的材料的实例包括诸如环氧树脂的树脂以及陶瓷。管芯焊盘12、绝缘构件44以及布线图案42可以借助粘合剂彼此接合在一起。布线图案36、42也成为布线条(wiringbar)。用于布线图案36、42的材料的实例包括与管芯焊盘12的材料相同的材料。
栅极布线30a至30d、第一布线32a至32d、第二布线34a至34d以及布线40、46可以是导线或接合带(bonding ribbon)。用于栅极布线30a至30d、第一布线32a至32d、第二布线34a至34d以及布线40、46的材料的实例包括诸如铝、金和铜的金属。栅极布线30a至30d、第一布线32a至32d、第二布线34a至34d以及布线40、46例如通过采用超声波、压力等的引线接合连接至布线图案36、42、半导体芯片14a至14d或引线18、20。
管芯焊盘12、半导体芯片14a至14d、引线18的内端部以及引线20的内端部可以利用树脂部24覆盖。引线16、18、20的内端部插入树脂部24中。在引线16、18、20中，树脂部24内部的部分是所谓的内部引线部。在引线16、18、20中，树脂部24外部的部分是所谓的外部引线部。树脂部24的外部形式的实例是基本上长方体。用于树脂部24的材料的实例包括诸如聚苯硫醚树脂(PPS树脂)以及液晶聚合物的热塑性树脂。可以通过利用热塑性树脂模制管芯焊盘12和半导体芯片14a至14d来形成树脂部24。树脂部24形成有贯通孔28，贯通孔28的中心轴与管芯焊盘12的贯通孔26的中心轴对齐。与贯通孔26相同，贯通孔28例如是用于在螺固时通过其插入螺钉等的孔。贯通孔28具有小于贯通孔26的直径。
当流过第一布线32a至32d以及第二布线34a至34d的电流随时间变化时，栅极布线30a至30d易受由于电磁效应而从第一布线32a至32d以及第二布线34d至34d接收的互感的影响。因此，半导体芯片14a至14d的栅电压随时间波动。互感由在栅极布线30a至30d与第一布线32a至32d和第二布线34a至34d之间的距离，以及栅极布线30a至30d的与第一布线32a至32d和第二布线34a至34d相对的部分的长度决定。当栅极布线30a至30d与第一布线32a至32d和第二布线34a至34d之间的距离更短时，互感变得更大。当栅极布线30a至30d的与第一布线32a至32d以及第二布线34a至34d相对的部分的长度更长时，互感变得更大。
例如，在半导体器件10中，栅极布线30b的与最接近栅极布线30b的第一布线32b相对的第一部分30x的长度d1短于栅极布线30b的与第二布线34b相对的第二部分30y的长度d2。因此，栅极布线30b较不易受由于电磁效应而从第一布线32b接收的互感的影响。因此，抑制栅电压随时间波动。
相对于在半导体器件10中彼此相邻的半导体芯片14a至14d之间沿Y方向延伸的轴Ax，一侧上的栅极布线30a至30d、第一布线32a至32d以及第二布线34a至34d可以与另一侧上的栅极布线30a至30d、第一布线32a至32d以及第二布线34a至34d反转地布置。这均匀化了由半导体芯片14a至14d的栅极布线30a至30d由于电磁效应而从第一布线32a至32d以及第二布线34a至34d接收的互感的影响。因此，在彼此相邻的半导体芯片14a至14d之间的栅电压的波动降低。
当半导体芯片14a至14d由包含宽带隙半导体的材料制成时，与由硅制成的半导体芯片14a至14d相比，更大的电流会流过第一布线32a至32d以及第二布线34a至34d。因此，在宽带隙半导体中，栅电压趋于更随时间波动，这通过抑制栅电压随时间波动而产生更大的效果。
当半导体器件10配备有连接至栅极布线30a至30d的布线图案36时，半导体芯片14a至14d与布线图案36之间的距离可以被设定得更小。因此，栅极布线30a至30d可以被制造得更短。这使得栅极布线30a至30d较不易受由于电磁效应而从第一布线32a至32d和第二布线34a至34d接收的互感的影响，由此进一步抑制栅电压随时间波动。
半导体器件10可以包括引线18、20以及管芯焊盘12。这使得其难以使栅极布线从第一和第二布线中充分分开。因此，栅电压趋于更随时间波动，由此通过抑制栅电压随时间波动而实现更大的效果。
图2是图示在根据第一实施例的半导体器件中的栅电压随时间波动的实例的图表。图2图示了由半导体芯片14b的栅极布线30b从第一布线32a至32d以及第二布线34a至34d接收的互感的影响的实例。没有考虑栅极布线30b的自感的影响。
流过并联连接的半导体芯片14a至14d的电流值是50A。因此，12.5A的电流流过半导体芯片14a至14d的每一个。当半导体芯片14a至14d处于操作中时，栅电压是15V。开关时间是20ns。栅极布线30b的长度是3.2mm。栅极布线30b的第一部分30x的长度d1是2.4mm。栅极布线30b的第二部分30y的长度是3.2mm。
对于在栅极布线30b与第一布线32a至32d以及第二布线34a至34d之间的距离来说，采用最短距离。如图1和2中所示，最短距离是在第一布线32a至32d以及第二布线34a至34d上的点P1至P8与栅极布线30b之间的距离。例如，在栅极布线30b与第二布线34a上的点P1之间的距离是3.72mm。利用这个距离以及长度d1和d2，计算由栅极布线30b从第一布线32a至32d以及第二布线34a至34d接收的互感。通过以下表达式计算栅电压的波动Y：
V＝L×di/dt
其中，L是互感，i是电流，并且t是时间。
图2图示了互感以及栅电压的波动的计算结果。例如，由栅极布线30b从第二布线34a接收的互感是0.22nH。其导致的栅电压波动是0.14V。由栅极布线30b从第一布线32a至32d以及第二布线34a至34d接收的总互感是1.81nH。栅极布线30b中的栅电压的总波动是1.14V(当四舍五入至两个有效数字时是1.1V)。类似地，计算由栅极布线30a从第一布线32a至32d以及第二布线34a至34d接收的互感。由栅极布线30a从第一布线32a至32d以及第二布线34a至34d接收的总互感是1.81nH。也计算了栅极布线30a中的栅电压的波动。栅极布线30a中的栅电压的总波动是1.1V(当四舍五入至两个有效数字时)。因此，栅电压发生相同的波动，并且因此在彼此相邻的半导体芯片14a、14b之间，其中没有产生任何变化。
图3是示意性图示用于参考的半导体器件的平面图。图3中图示的半导体器件110除包括半导体芯片114a至114d、栅极布线130a至130d、第一布线132a至132d以及第二布线134a至134d来取代半导体芯片14a至14d、栅极布线30a至30d、第一布线32a至32d以及第二布线34a至34d之外，半导体器件110具有与半导体器件10相同的结构。
栅极布线130a至130d布置在第一布线132a至132d以及第二布线134a至134d之间。栅极布线130a至130d的与第一布线132a至132d以及第二布线134a至134d相对的部分中的每一个都具有与栅极布线130b相同的长度。
图4是图示在用于参考的半导体器件中的栅电压随时间波动的一个实例的图表。图4图示了由半导体芯片114b的栅极布线130b从第一布线132a至132d以及第二布线134a至134d接收的互感的影响的实例。没有考虑栅极布线130b的自感的影响。
流过并联连接的半导体芯片114a至114d的电流值是50A。因此，12.5A的电流流过半导体芯片114a至114d中的每一个。当半导体芯片114a至114d处于操作中时，栅电压是15V。开关时间是20ns。栅极布线130b的长度是3.2mm。栅极布线130b的与第一布线132a至132d以及第二布线134a至134d相对的长度是3.2mm。
对于在栅极布线130b与第一布线132a至132d以及第二布线134a至134d之间的距离来说，采用最短距离。如图3和4中所示，最短距离是在第一布线132a至132d以及第二布线134a至134d上的点P11至P18与栅极布线130b之间的距离。例如，栅极布线130b与在第二布线134a上的点P11之间的距离是4.54mm。利用这个距离以及栅极布线130b的长度，计算由栅极布线130b从第一布线132a至132d以及第二布线134a至134d接收的互感。图4图示了互感以及栅电压的波动的计算结果。例如，由栅极布线130b从第二布线134a接收的互感是0.10nH。其导致栅电压的波动是0.07V。由栅极布线130b接收的总互感是1.90nH。栅极布线130b中的栅电压的总波动是1.19V(当四舍五入至两个有效数字时是1.2V)。类似地，计算由栅极布线130a从第一布线132a至132d以及第二布线134a至134d接收的互感。由栅极布线130a从第一布线132a至132d以及第二布线134a至134d接收的总互感是1.74nH。也计算在栅极布线130a中的栅电压的波动。栅极布线130a中的栅电压的总波动是1.1V(当四舍五入至两个有效数字时)。因此，栅电压发生0.1V的波动，并且因此在彼此相邻的半导体芯片114a、114b之间，其中产生差异。
第二实施例
图5是示意性图示根据第二实施例的半导体器件的平面图。图5中图示的半导体器件10a是盒型(case type)半导体器件。半导体器件10a包括半导体芯片14a至14l、分别连接至半导体芯片14a至14l的栅极布线30a至30l、分别连接至半导体芯片14a至14l的第一布线32a至32l、分别连接至半导体芯片14a至14l的第二布线34a至34l以及盒60。半导体芯片14e、14g、14i、14k可以具有与半导体芯片14a相同的结构。半导体芯片14f、14h、14j、14l可以具有与半导体芯片14b相同的结构。
半导体芯片14a至14f设置在形成在第一基板50a上的布线图案52a上。布线图案54a、56a可以形成在基板50a上。布线图案54a可以通过栅极布线30a至30f连接至半导体芯片14a至14f。布线图案56a可以通过第一布线32a至32f以及第二布线34a至34f连接至半导体芯片14a至14f。
类似地，半导体芯片14a至14f设置在形成在第二基板50b上的布线图案52b上。布线图案54b、56b可以形成在基板50b上。布线图案54b可以通过栅极布线30g至30l连接至半导体芯片14g至14l。布线图案56b可以通过第一布线32g至32l以及第二布线34e至34l连接至半导体芯片14g至14l。
盒60可以配备有用于安装基板50a、50b的底部60a。用于安装汇流条72a至72c的台60b可以布置在底部60a上。汇流条72a至72c可以电连接至半导体芯片14g至14l。盒60可以包括围绕基板50a、50b以及台60b的第一侧壁部60c以及围绕第一侧壁部60c的第二侧壁部60d。盒60的开口可以利用盖密封。用于盒60的材料的实例包括诸如以聚对苯二甲酸丁二醇酯(PBT)或聚苯硫醚(PPS)树脂为代表的工程塑料的树脂。用于盖的材料的实例包括热塑性树脂。例如，诸如硅凝胶的凝胶可以注入盒60中以便缓解应力。半导体器件10a可以实现与半导体器件10相同的操作和效果。
图6是示意性图示用于参考的半导体器件的平面图。图6中图示的半导体器件110a除包括半导体芯片114a至114l、栅极布线130a至130l、第一布线132a至132l以及第二布线134a至134l来取代半导体芯片14a至14l、栅极布线30a至30l、第一布线32a至32l以及第二布线34a至34l之外，半导体器件110a具有与半导体器件10a相同的结构。
栅极布线130a至130l布置在第一布线132a至132l以及第二布线134a至134l之间。栅极布线130a至130l的与第一布线132a至132l和第二布线134a至134l相对的部分中的每一个都具有与栅极布线130b相同的长度。
本发明不限于上文详细解释的优选实施例。
例如，半导体器件10、10a可以仅包括一个半导体芯片。半导体器件10、10a可以包括连接至半导体芯片的第三布线。
半导体芯片14a至14l可以包括取代垂直晶体管的横向晶体管。在这种情况下，半导体芯片14a至14l的背面上不形成电极焊盘，而诸如漏极电极焊盘和集电极电极焊盘的不同的电极焊盘例如形成在半导体芯片14a至14l的正面上。
半导体器件10可以不具有布线图案36、42。在这种情况下，栅极布线30a至30d连接至引线18。第一布线32a至32d以及第二布线34a至34d连接至引线20。
附图标记列表
10,10a：半导体器件；14a至14l：半导体芯片；12：管芯焊盘；12a：芯片安装表面；18：第一引线；20：第二引线；30a至30l：栅极布线；30x：栅极布线的第一部分；30y：栅极布线的第二部分；32a至32l：第一布线；34a至34l：第二布线；36：布线图案；Ax：轴

Claims (5)

1.一种半导体器件，包括：
至少一个半导体芯片；
栅极布线，所述栅极布线连接至所述至少一个半导体芯片；
第一布线，所述第一布线连接至所述至少一个半导体芯片；以及
第二布线，所述第二布线连接至所述至少一个半导体芯片；
其中，所述第一布线和所述第二布线沿所述栅极布线延伸；
其中，所述第一布线布置在所述栅极布线和所述第二布线之间；
其中，所述第一布线是最接近所述栅极布线的布线；并且
其中，所述栅极布线的与所述第一布线相对的第一部分短于所述栅极布线的与所述第二布线相对的第二部分。
2.根据权利要求1所述的半导体器件，其中，所述至少一个半导体芯片包括多个半导体芯片；
其中，所述多个半导体芯片沿第一方向布置；并且
其中，相对于在彼此相邻的半导体芯片之间的沿与所述第一方向垂直的第二方向延伸的轴，一侧上的所述栅极布线、所述第一布线和所述第二布线与另一侧上的所述栅极布线、所述第一布线和所述第二布线反转地布置。
3.根据权利要求1或2所述的半导体器件，其中，所述至少一个半导体芯片由包含宽带隙半导体的材料制成。
4.根据权利要求1至3中的任何一项所述的半导体器件，进一步包括连接至所述栅极布线的布线图案。
5.根据权利要求1至4中的任何一项所述的半导体器件，进一步包括：
第一引线，所述第一引线电连接至所述栅极布线；
第二引线，所述第二引线电连接至所述第一布线和所述第二布线；以及
管芯焊盘，所述管芯焊盘具有用于安装所述至少一个半导体芯片的芯片安装表面。
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