CN101183669A - 垂直传导电路小片的封装设计 - Google Patents

垂直传导电路小片的封装设计 Download PDF

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Publication number
CN101183669A
CN101183669A CNA2006101671776A CN200610167177A CN101183669A CN 101183669 A CN101183669 A CN 101183669A CN A2006101671776 A CNA2006101671776 A CN A2006101671776A CN 200610167177 A CN200610167177 A CN 200610167177A CN 101183669 A CN101183669 A CN 101183669A
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Prior art keywords
encapsulation
small pieces
circuit
conducting element
circuit small
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CNA2006101671776A
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Inventor
詹姆斯·哈恩登
谢方德
王黎明
杨宏波
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GEM ELECTRONICS (SHANGHAI) CO Ltd
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GEM ELECTRONICS (SHANGHAI) CO Ltd
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Publication of CN101183669A publication Critical patent/CN101183669A/zh
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Abstract

本发明的各实施例涉及垂直传导半导体装置的封装设计，所述封装设计包括与电路小片的一顶面的低电阻接触。在一实施例中，所述低电阻接触可通过使用与一引线框架的一侧或与一引线框架的两个对置侧相接合的铝条带来形成。根据一特定实施例，所述垂直传导装置可容纳于一经修改以用于此目的的方形扁平无引线(Quad FlatNo－lead，QFN)封装内。

Description

垂直传导电路小片的封装设计
技术领域
本发明涉及垂直传导半导体装置的封装设计，所述封装设计包括与电路小片的一顶面的低电阻接触。
背景技术
对极大容量的便携式计算机产品(例如便携式远程通信产品、数字照相机、MP3播放器、袖珍式计算机等等)中离散式、集成式“功率管理半导体产品”、及多种技术的组合的广泛需求已促生了用于从电池中产生并切换大量电压的新产品。大批量生产的压力又推动了专门半导体产品的迅速发展，并促使产生了相继的几代装置封装，这些装置封装表现出减小的垂直断面、更小的占用面积、更低的热阻及电阻、及更低廉的制造成本。
只需要具有接至所容纳电路小片的一侧的单个低电阻触点的封装存在一些可接受的替代形式。此种仅在单侧上具有触点的电路小片的实例包括集成电路、功率集成电路(功率IC)及侧向离散电路。
然而，垂直传导离散装置(例如传统的Mosfet)所表现出的低的单位面积电阻需要形成接至电路小片顶面及底面二者上的极低电阻触点。此要求已导致开发出封装、工艺及材料的独特组合。
影响前几代垂直传导离散装置的封装的设计的一个目的是减小封装所表现出的电阻。在该上一代封装中，使用表现出更低电阻的替代物来代替传统的2密耳厚金接合导线。影响前几代封装的设计的另一目的是消除引线，从而既实现更低的热阻又实现更薄的封装轮廓。
为垂直传导离散装置设计下一代封装的一关键将是将那些相同的目的集中到可制造的并具有成本效益的标准封装中。未来封装设计的另一关键将是提供用于以经济的方式将不同技术电路小片甚至无源组件与功率管理电路小片互连的方式。有利地以比在单独封装中互连此种装置所能达到的更低的阻抗、更低的电感及更高的频率实现此种互连。
因此，所属领域中需要具有用于为垂直传导离散装置及其他需要在两侧上具有低电阻触点的电路小片制作封装的改良技术。
发明内容
根据本发明的各实施例涉及垂直传导半导体装置的封装设计，其包括与电路小片的一顶面的低电阻接触。在一实施例中，所述低电阻接触可使用与一引线框架的一侧或与所述引线框架的两个对置侧相接合的铝条带来形成。根据一特定实施例，所述垂直传导装置可容纳于一针对此目的加以修改的QFN封装内。
一种根据本发明的封装的一实施例包括一引线框架，所述引线框架包括一电路小片焊垫及一导电元件，所述导电元件从所述封装中伸出且不与所述电路小片焊垫成一整体。一电路小片在一第一侧上由所述电路小片焊垫支撑，且一导电条带在所述导电元件与所述电路小片的一与所述第一侧对置的第二侧之间提供电接触。
一种根据本发明用于封装一垂直传导电路小片的方法的一实施例包括提供：一导电条带，所述导电条带电接触所述电路小片的一第一侧，所述第一侧与所述电路小片的一电接触一电路小片焊垫的第二表面对置；及一导电元件，其从所述封装中伸出但不与所述电路小片焊垫成一整体。
一种根据本发明的导电肋的一实施例具有：一第一部分，其经配置以与一电路小片的一表面上的触点电连通，所述电路小片在一第二表面上由一电路小片焊垫支撑；及一第二部分，其经配置以与一从容纳所述电路小片及所述条带的封装中伸出的导电元件电连通，所述导电元件不与所述电路小片焊垫成一整体。
本发明的这些及其它实施例以及其特征和某些潜在优点将结合下文及附图加以更详细阐述。
附图说明
图1A显示一由一组接合导线及一铝条带所提供区域的简化剖面图。
图1B显示由一铝接合导线及一铝条带所提供的垂直断面。
图2A显示一根据本发明封装的一实施例的一简化平面图，所述封装容纳单个垂直传导电路小片并与其一顶面具有以一铝接合条带形成的接触。
图2B显示图2A所示封装的一简化剖面图。
图3显示一根据本发明容纳两个电路小片的封装的一替代实施例的一简化平面图。
图4A-B分别显示一传统QFN封装的布局的简化透视图及平面图。
图5A-5G显示一根据本发明各实施例加以修改的QFN封装的各种电阻-电路小片尺寸选项的简化平面图。
图6A-6C显示电路小片在不同封装类型的电路小片焊垫上的各种接合方案选项的对比性电路小片尺寸。
图7A-D展示根据本发明某些实施例的布局规则向容纳单个或两个Mosfet电路小片的4×4mm及3×3mm封装的扩展。
图8A显示另一与QFN密切相关的传统封装配置的简化平面图。
图8B图解说明一利用与源极的铝条带连接的图8A所示DFN封装的布局的简化平面图。
图8C显示代替2×5mm QFN封装(10mm2)的“标准型”3×3mm QFN封装(占用面积为9mm2)。
图9A至图9C展示容纳具有PIC的Mosfet、其它Mosfet及其它有源装置(例如Schottky二极管)的常用组合的封装。
具体实施方式
根据本发明某些实施例的装置封装涉及到使用铝条带(而不是接合导线)来与一垂直传导电路小片的至少一个表面形成低电阻接触。
位于Irvine，California的Orthodyne Electronics公司(铝导线接合器的一主要制造商)最近发布了一系列能够接合宽度及厚度从20密耳宽×2密耳厚直至80密耳宽×10密耳厚不等的铝条带的机器。表A列出了接合导线直径剖面相对于在电方面可比的铝条带的尺寸的关系。
表A
Figure A20061016717700061
图1A比较两种用于与一电路小片表面形成具有大体相同电阻的接触的两种不同方法的剖面图。在传统方法中，七条直径分别为8密耳的铝接合导线提供一等于351平方密耳的组合截面积。相比之下，根据本发明一实施例的两条40密耳×4密耳铝条带提供一等于320平方密耳的组合截面积。铝条带与接合导线相比所提供的更大的截面积会有利地降低由所述连接所提供的电阻。
此外，图1B比较由图1A中所示的这两种方法所提供的垂直断面。图1B显示由于变薄，因而铝条带表现出变低的环圈高度。此种变低的环圈高度可允许增大电路小片上塑料的厚度。或者，变低的环圈高度可允许减小封装的厚度，而不牺牲覆盖电路小片的塑料量。此会使所述封装的垂直断面非常有利地减小。
图2A显示一根据本发明利用一铝条带接合图案的封装的一实施例的一简化平面图。图2B显示图2A所示封装沿图2A所示的线A-A′截取的简化剖面图。与使用传统接合导线的等效封装相比较，用于与电路小片表面形成电接触的这对4mm×40mm铝条带使图2A-B中所示封装的实施例能够表现出一减小的垂直断面。
图2A的实施例确实显示一将栅极触点与一毗邻引脚相连接的接合导线。不过，与栅极的接触不需要使用高电压。因此，栅极触点接合导线的直径(例如4密耳或0.1mm)小于传统上用来形成源极触点的接合导线的直径(例如8密耳)。因此，即使假定接合导线与条带的接合断面相同，因只使用具有更小直径(4密耳相对于8密耳)的剩余栅极接合导线而带来的高度减小量也将大于所述封装的总厚度的10％。
虽然图2A-B中所示封装的具体实施例是容纳单个电路小片，但根据本发明的各实施例并不仅限于此种配置。在各替代实施例中，一封装可容纳多于一个电路小片且仍属于本发明的范围内。因此，图3显示一根据本发明的封装布局的另一实施例的一简化平面图，所述封装布局利用单独的铝条带来接合至一对容纳于所述封装内的电路小片的顶面。
图3中所示的实施例突出显示使用铝条带接合的一个方面。具体而言，诸多现有的功率管理封装是设计用于导线接合的，而导线结合要求以相对锐角接合并以紧半径弯曲来拉动所述导线。然而，因铝条带具有薄/宽的形状，不容易将其侧向弯曲来使其与电路小片或引线框架接合端头对齐以使其顺从现有的封装。因此，在图3所示的实施例中，将铝条带描绘成与电路小片的顶面形成一稍微倾斜的连接。考虑到此种倾斜的连接及双电路小片引线框架上接合端头的宽度，条带的宽度受到限制，从而会增大串联电阻。
根据本发明的各实施例，发明者已发现对一传统封装类型加以修改可有利于使用铝接合图案来形成与电路小片表面的低电阻接触。具体而言，“方形扁平无引线”(QuadFlat No-lead，QFN)为一系列以内部电路小片布置、接合及构造为特征的经JEDEC注册的封装，其使与功率电路小片的连接得到优化以使电路小片尺寸对封装占用面积比之比最大化、使封装电阻及热阻最小化并满足经JEDEC注册的外部封装尺寸。图4A-B分别显示一利用接合导线来与其中所容纳的电路小片的顶面形成电接触的传统QFN封装的简化透视图及平面图。
根据本发明的特定实施例采用QFN及其它封装设计来容纳垂直传导、功率管理装置。此方法提供数种用于改进先前在传统上一直封装此类功率管理半导体装置的方式的替代方案。
例如，传统的功率管理装置封装与上文所示QFN封装之间的一个差别在于QFN通常具有精细得多的引线间距、更小的引线及多得多的引线，且所述引线位于封装的所有四个侧上。对于集成电路(IC)的封装，引脚数量已随着时间增加以容纳具有越来越多电连接线的电路小片。相比之下，对于如Mosfet等离散产品及对于小的功率管理集成电路(PIC)，电连接线的数量通常不大，且某些现有封装中通常存在高的引脚数量以通过添加许多并行的引线来弥补差的热阻。
然而，对于根据本发明的各实施例所揭示的16至50引脚的经修改QFN封装，高的引脚数量会提供对电路小片及“经组合的”/整体引脚进行定向的灵活性，从而以最小限度的方向变动来容纳铝条带接合图案，以形成与电路小片的低热阻及电阻接触。例如，根据本发明的特定实施例，一铝条带的端部可与封装的对置侧上的引脚相接合，使条带的中心与电路小片表面相接触。下表B归纳已根据本发明各实施例加以修改的图5A-G所示QFN封装的某些特性。
表B
图号 封装尺寸(mm) 引脚数量 引脚间距(mm) 电路小片焊垫尺寸(mm) 电路小片数量 电路小片尺寸(mm) 电路小片面积(mm2)
5A 5×5 36 0.4 3.4×4.35     1 3.25×4.2 13.65
5B 5×5 36 0.4 3.4×2.0     2 3.25×1.85 6.012
5C 5×5 36 0.4 4.0×4.35     1 3.85×4.2 15.96
5D 5×5 40 0.4 4.0×2.0     2 3.85×1.85 7.123
5E 5×5 36 0.4 3.4×4.35     1 3.25×4.2 13.65
5F 5×5 36 0.4 3.4×2.0     2 3.25×1.85 6.012
5G 5×5 36 0.4 4.0×4.35     1 3.85×4.2 15.96
针对任何尺寸的QFN封装及该封装中的任何配置实现最低的总电阻均可能涉及到某些折衷且可能产生一种对于所有组合而言均较佳的配置。例如，图5A显示位于一根据本发明一实施例加以修改的36引脚5×5mm QFN封装501中的单个Mosfet电路小片的布局的简化平面图。在此特定实施例中，所述单个Mosfet电路小片500在所述电路小片的一侧的中心上具有一接至栅极触点504的接合导线引线连接线505。此定向能实现一对称的条带接合布置并容易容纳两个4×40密耳的条带502及503。
图5B显示一根据本发明的封装520的一替代实施例的布局的一简化平面图。图5B所示的实施例利用与图5A所示实施例中相同类型的中心(引线)栅极连接线521及522，其中封装520包封有两个而不是一个Mosfet电路小片524。
在这两个图5A-B所示的布局中，铝条带的电阻作用均已通过跨越电路小片顶面在两侧上连接至引线框架而得到最小化。可将此种接合方法与图5C所示的方法相比较，图5c显示一根据本发明的封装530的一替代实施例的布局的一简化平面图。具体而言，图5C所示的封装530的铝条带532将源极仅在所容纳电路小片的一侧上连接至引线框架。
以图5A及5B所示实施例的方式在所述封装的两侧上连接源极会将串联接合条带电阻减半，从大约0.4莫姆减到大约0.20莫姆。然而，获得此种减小的电阻是以电路小片尺寸减小大约20％为代价。减小的电路小片尺寸的影响因而为所述电路小片的电阻的函数。在此实例中，在现有技术水平的低电压Mosfet技术中，图5A-B中所示尺寸的电路小片将表现出一大约1莫姆的总电路小片电阻。在本实例中，在电路小片尺寸减小20％时将会增加大约0.2莫姆。此可与从封装的两侧上接合源极以使所述接合条带减小一半(此也使总电阻减小约0.2莫姆)相比较。因此，此处，将可根据经济条款(硅面积相对于条带接合物)或根据如切换速度等性能量度而不仅仅只根据电阻来作出是否在所述引线框架的两侧上接合所述条带的决定。
当Mosfet的击穿电压额定值增大时，此种尺寸的Mosfet的电阻也将增大-且一20％的电路小片尺寸损失将造成更大的电路小片电阻损失，因而如果目标是得到最高的绝对最低电阻，则将可选择最大的电路小片尺寸。
通过使用一36引脚的5×5mm QFN封装，图5A、B及C所示的接合图将会奏效。不过，可使用一具有相同尺寸但具有40个引脚而不是36个引脚的经修改QFN封装来改进一双电路小片封装实施例上的栅极布置。具体而言，图5D显示一经修改以容纳双电路小片543的此种QFN封装540的一简化布局，其中源极触点的条带接合544仅连接至引线框架的一侧上。
由于图5B及5D所示的双电路小片占用的面积略小于图5A及5C所示实施例所容纳的单电路小片面积的一半，因此所得到的电阻略大于所述单电路小片电阻的两倍。而且，由于每一电路小片只具有与所述双电路小片实施例上所使用的这两个条带相同尺寸的单个条带，因此铝接合条带及Mosfet二者仍对总串联电阻贡献大致相同的百分比。
图5C-D所示的实施例图解说明仅在封装的一侧上接合至源极引脚的铝条带。封装的其余三侧上的引脚均与电路小片焊垫成一整体，从而使可供所述电路小片占用的电路小片焊垫面积最大化。此种布置能够以封装电阻增大几分之一莫姆为代价来增大可供电路小片使用的电路小片焊垫的面积。
在设计封装时还有的另一考虑因素是电路小片尺寸的百分比差会针对不同的封装尺寸而变化。例如，为在两侧上隔离电路小片所需的最小间隔为一固定值。然而，当封装尺寸增大时，此值为总封装尺寸的一更小的百分比。
一在源极引脚之间引出栅极连接线的引脚图(例如图5A-B的实施例中所示)允许电路小片及封装布局具有最对称的布局并容许条带接合具有最直接的路径。从P.C.板布局的观点看，由于源极引脚往往直接通过“通路”连接至一内部电源或接地平面，因此在源极连接线之间得到通往栅极连接线的迹线通常不会造成问题。
在其中源极及栅极必须连接在单个P.C.板层上的罕见情况下，图5E至5F提供具有36个引脚的5×5mm QFN封装的布局的简化平面图，其具有与图5A-B相同的两个单条带及两个双条带接合/引脚图选项。不过，在图5E-F所示的实施例中，栅极焊垫550及引脚552移至一个角上(在图5E所示的单电路小片封装中)或移至对置的角上(在图5F所示的双电路小片封装中)。结果会得到相同的电路小片尺寸及相同的接合条带电阻。因而，相同的电路小片/封装电阻比仍适用。不过，更小封装上略微不当的接合角度可能会限制可适应的条带宽度。
图5G的实施例中所示的边角栅极选项可适用于图5C所示的单电路小片实施例。如同前面的说明一样，通过使用40×4密耳的条带，仍可使跨越源极顶部金属的接合路径得到优化。不过，如果在更小的封装中增大条带宽度或减小电路小片尺寸，则所述边角栅极封装选项可能会限制可用的接合配置。
上述说明表明，根据本发明各实施例的高引脚数量的经修改QFN封装中的复数条引线使封装设计具有更大的灵活性。具体而言，大的可用引脚数量使设计者能够从大量可能性中为一给定电路小片选择最佳的内部连接线，同时仍使封装占用面积满足相关JEDEC标准。QFN封装的最小间距及引线宽度还提供将栅极及其它更小电阻的临界电连接线接合至外部世界而不在引线框架上浪费大量面积的替代选择。
当在一5×5mm封装中使用一40密耳宽的条带时，图5E及5G所示实施例中的条带图案是可接受的。但是，对于更小封装中的40密耳条带而言，或如果要在5×5mm封装中使条带的宽度最大化，则对栅极连接线使用边角引脚将略微欠佳。以不为直线的任何形式接合所述条带均会牺牲一定的面积并在接合过程期间造成应力及张力。此种应力可能足以也可能不足以对源极金属下面的结构或对条带/源极金属接合物的完整性造成可靠性问题。
使用根据本发明加以修改的QFN型封装的另一优点在于，各单独引脚之间的区域用来密封至封装边缘周围的塑料。具体而言，某些传统的封装设计的特征是具有一阻断封装本体的顶部与底部塑料部分之间的连续性的连续凸片部分。此使得为保持封装的完整性，封装必须变厚，因为顶部塑料与底部塑料在一侧面区域的一主要部分中并不相连此种传统封装设计可与将侧面划分成许多引脚且顶部与底部塑料相连并在引脚之间连续的高引脚数量QFN型封装形成对照。
图6A呈现一根据本发明修改的用于容纳一垂直传导功率切换装置的QFN封装设计的一实施例的一简化平面图。图6B呈现一根据本发明修改的用于容纳一垂直传导功率切换装置的QFN封装设计的一替代实施例的一简化平面图。
可将图6A-B所示经修改的QFN封装的实施例的布局与对应于图2A-B及3所示非QFN封装设计的图6C的布局相比较。表C归纳这三个封装设计的相对尺寸。
表C
封装图 PC板面积 电路小片焊垫(S) 电路小片/占用面积比(效率)
6A 5mm×5mm＝25mm2 4.0mm×4.35mm＝17.4mm2 69.6％
6B 5mm×5mm＝25mm2 3.4mm×4.35mm＝14.79mm2 59％
6C 5.75mm×4.9mm＝28.2mm2 3.95mm×3.3mm＝13.035mm 46.26％
表C表明，与不同于经修改的QFN封装方法(图6C)的其它方法、甚至是以铝条带接合为特征的其他方法相比较，本发明的经修改的QFN封装设计的这两个实例会在一更小的占用面积中得到一更大的电路小片。而且，图6A展示一类似于图5C所示封装的引脚图布置，从而允许从电路小片的一侧接合源极并沿封装的对置侧(以及QFN型封装的两端及底侧，以实现最大的热传送)接触漏极。这使空间利用率提高16％。因而，这是一种标准的JEDEC外形封装，其具有一更小的占用面积、一更大的电路小片、呈一具有得到改善的热性能及电性能的更薄(至多0.8mm)表面安装封装形式。
总体而言，在适用于根据本发明各实施例的封装类型的Mosfet电路小片尺寸及技术范围内，所述条带接合物可经配置以使封装电阻保持在由封装与电路小片电阻之和所表示的总电阻的约15-30％之间。在各特定实施例中，对于包封单个Mosfet电路小片的封装而言，本发明所采用的传导条带经配置以表现出一小于约0.5莫姆的电阻。对于包封双Mosfet电路小片的封装而言，所述导电条带将预期表现出一约1.0莫姆或更小的电阻。
图7A-D展示根据本发明某些实施例的布局规则向容纳单个或双Mosfet电路小片的4×4mm及3×3mm封装的扩展。相同的规则仍适用：以最大数量的引脚实现最大的电路小片及最优化的接合角度。在图7A及7B所示4×4mm封装的情况下，最大的电路小片及最优化的接合角度是以一为28的引脚数量及一为0.4mm的引脚间距实现的。在图7C及7D所示3×3mm封装的情况下，最大的电路小片及最优化的接合角度是以一为20的引脚数量及一为0.4mm的引脚间距实现的。表D归纳了图7A-D中所示电路小片的某些特性。
表D
图号 所容纳电路小片的数量 QFN占用面积(mm) 电路小片焊垫占用面积(mm) 电路小片焊垫/占用面积效率(％)
7A 1 4×4 3.5×3.05 67
7B 2 4×4 2.55×1.7 54
7C 1 3×3 2.2×2.5 58
7D 2 3×3 1.85×1.16 48
上文说明已阐述了修改一QFN类型的封装(遵照JEDEC规范MO-220)以容纳垂直传导装置。不过，本发明并不仅限于此特定实施例，且替代实施例利用其它封装类型。例如，JEDEC规范第MO-243号阐述QFN封装的一较新的变化形式，且根据本发明的各替代实施例可遵照此规范。其它规范涵盖QFN类型的封装，且根据本发明的各实施例可遵照这些封装规范。
另外，图8A显示与QFN密切相关的另一传统封装配置的一简化平面图。具体而言，图8A中所示的2×5mm“DFN型”(JEDEC规范MO-229)封装只沿两侧带有引脚。虽然DFN型封装被广泛使用，但2×5mm尺寸的封装几乎专门用于“反向阻断式Mosfet开关”。反向阻断式Mosfet开关包括两个垂直传导Mosfet，这两个垂直传导Mosfet具有一作为Mosfet的基极的共用漏极。在此配置中，当这两个Mosfet关断时，每一Mosfet中的本征二极管均阻断另一Mosfet的本征二极管的正向偏置导通。此配置用于许多具有多个电源的产品。相同的Mosfet配置也常见于智能及受保护的电池中。通过使用所示的电路小片焊垫尺寸及布置，图8A中所示的传统DFN封装展示出一等于3.05mm×1.5mm＝4.57mm2(效率为46％)的可用电路小片焊垫面积。
图8B图解说明利用接至源极的铝条带连接线的8A所示DFN封装的布局的一简化平面图。图8B图解说明试图通过仅切换至图8A所示DFN封装中的铝条带接合来降低阻抗及成本可能不会产生明显的效果。具体而言，在此实施例中，由于封装的窄端上的触点的位置及电路小片的窄的长宽比，最大条带宽度为20密耳。由于所述条带具有仅为2密耳的厚度，图8B所示的实施例提供仅为在前面的实例中所用4×40密耳条带的四分之一的截面积。
在图8C中，“标准型”3×3mm QFN封装(占用面积为9mm2)代替了2×5mm DFN封装(10mm2)。在本实例中，由于封装占用面积减少10％(1mm2)，电路小片焊垫面积增加约9％。以所述反向阻断式配置容纳的电路小片占用一为2.57×2.02mm＝5.2mm2的面积，此为电路小片焊垫尺寸相对于图8B所示配置增大了大约9％。另外，所述封装现在容纳两个40×4密耳的铝条带，其中电路小片触点与引线框架源极触点之间的距离大约为前述实例(图8B)的封装的一半。
图9A至图9C展示容纳如表E中所归纳的Mosfet与PIC的常用组合、其它Mosfet及其它有源装置(如Schottky二极管)的封装。
表E
图号 QFN尺寸(mm) 所容纳的电路小片
9A 5×5 Mosfet与PIC
9B 5×5 2个Mosfet与PIC，或Mosfet、Schottky二极管与PIC
9C 3×3 Mosfet与PIC
此处，一目标是能够以一种使所需装置可互连的方式来容纳所需装置。在存在任何接至Mosfet或Schottky二极管的高电流连接线的情况下，另一目标是提供一种将允许各装置与铝条带相接合的布局，所述铝条带具有一直接连接至一具有足够空间以容纳所述条带接合物的引线框架端头的清楚路径。可使用一更薄的铝接合导线来实现非功率连接。可能的情况是，可在对功率连接线使用铝条带的同一电路小片上对非功率连接线使用甚至更小直径的金或铜导线。在这些实施例中，应使顶部金属与引线框架的触点区中的点镀相兼容。
虽然上文详尽阐述了各具体实施例，但也可使用各种修改、替代构造及等效形式。因此，上文说明及例示不应视为对本发明范围的限制，本发明范围由随附权利要求书界定。

Claims (20)

1.一种封装，其包括：
一引线框架，其包括，
一电路小片焊垫，及
一导电元件，其从所述封装中伸出且不与所述电路小片焊垫成一整体，
一电路小片，其由所述电路小片焊垫支撑在一第一侧上；及
一导电条带，其在所述导电元件与所述电路小片的一与所述第一侧对置的第二侧之间提供电接触。
2.如权利要求1所述的封装，其中所述导电条带还在所述电路小片的所述第二侧与一在与所述第一导电元件对置的一侧上从所述封装中伸出的第二导电元件之间提供电接触，所述第二导电元件不与所述电路小片焊垫成一整体。
3.如权利要求1所述的封装，其中所述电路小片包括一垂直传导电路小片。
4.如权利要求3所述的封装，其中所述垂直传导电路小片包括一Mosfet。
5.如权利要求4所述的封装，其中所述导电条带提供一与所述Mosfet的一源极触点的电接触。
6.如权利要求4所述的封装，其中所述引线框架进一步包括一从所述封装中伸出且与所述电路小片焊垫成一整体的第二导电元件，所述第二导电元件提供与所述Mosfet的一漏极的电接触。
7.如权利要求4所述的封装，其中所述引线框架进一步包括一从所述封装中伸出且不与所述电路小片焊垫成一整体的第二导电元件，所述封装进一步包括一在所述第二导电元件与所述Mosfet的一栅极触点之间提供电接触的接合导线。
8.如权利要求1所述的封装，其中所述导电条带包含铝。
9.如权利要求1所述的封装，其中所述封装的尺寸遵照JEDEC规范MO-229、MO-220、或MO-243。
10.如权利要求1所述的封装，其进一步包括：
一支撑于所述电路小片焊垫上的第二电路小片；及
一第二导电条带，其在所述第二电路小片与一伸出所述封装之外且不与所述电路小片焊垫成一整体的第二导电元件之间提供电接触。
11.如权利要求10所述的封装，其中所述电路小片及所述第二电路小片包括以一反向阻断式配置形式连接的Mosfet。
12.如权利要求10所述的封装，其中所述第二电路小片包括一Mosfet、一功率集成电路(PIC)、或Schottky二极管。
13.一种用以封装一垂直传导电路小片的方法，所述方法包括提供一导电条带，所述导电条带电接触于，
所述电路小片的一第一侧，所述第一侧与所述电路小片的一电接触一电路小片焊垫的第二表面对置，及
一从所述封装中伸出且不与所述电路小片焊垫成一整体的导电元件。
14.如权利要求13所述的方法，其中所述导电条带还在所述电路小片的所述第一侧与一在与所述第一导电元件对置的一侧上从所述封装中伸出的第二导电元件之间提供电接触，所述第二导电元件不与所述电路小片焊垫成一整体。
15.如权利要求13所述的方法，其中所述电路小片包括一Mosfet，且所述导电条带电接触一源极触点。
16.一种导电条带，其具有，
一第一部分，其经配置以与一电路小片的一表面上的一触点电连通，所述电路小片由一电路小片焊垫支撑在一第二表面上，及
一第二部分，其经配置以与一从一容纳所述电路小片及所述条带的封装中伸出的导电元件电连通，所述导电元件不与所述电路小片焊垫成一整体。
17.如权利要求16所述的导电条带，其进一步包括一第三部分，所述第三部分经配置以与一在与所述第一导电元件对置的一侧上从所述封装中伸出的第二导电元件电连通，所述第二导电元件不与所述电路小片焊垫成一整体。
18.如权利要求16所述的导电条带，其包含铝。
19.如权利要求16所述的导电条带，其具有一介于约40-800平方密耳之间的截面积。
20.如权利要求16所述的导电条带，其经配置以在与一Mosfet电路小片的一源极触点的电连通中呈现一约1莫姆或以下的电阻。
CNA2006101671776A 2006-11-14 2006-12-26 垂直传导电路小片的封装设计 Pending CN101183669A (zh)

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