CN202042483U - 一种功率半导体器件的封装结构 - Google Patents
一种功率半导体器件的封装结构 Download PDFInfo
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Abstract
本实用新型涉及集成电路封装领域,具体公开了一种功率半导体器件的封装结构,包括:引线框架,所述引线框架包括引脚和本体;设置于所述引线框架本体上的驱动芯片;散热基板;设置于散热基板上的功率芯片,设置于引线框架本体或者散热基板上的电阻,所述电阻连接驱动芯片和功率芯片,所述引线框架本体、驱动芯片、散热基板、功率芯片和电阻均密封于树脂内。本实用新型提供的功率半导体器件的封装结构,利用电阻连接驱动芯片和功率芯片,可以通过调节电阻的大小满足整个模块性能。
Description
技术领域
本实用新型涉及集成电路封装领域,尤其涉及一种功率半导体器件的封装结构。
背景技术
电力电子技术正朝大容量、高频化、模块化、智能化及廉价化的方向迅速发展,以提高装置的功率密度,降低噪音,减小能耗和原材料消耗,提高装置的性能,并简化电路设计和提高系统的可靠性。IPM(Intelligent Power Module,智能功率模块)是在这种趋势下发展起来的新型电力电子器件。
IPM模块是以IGBT为功率器件的新型模块,作为功率集成电路产品,这种功率模块是将输出功率元件IGBT和驱动电路、多种保护电路集成在同一模块内,除了具有驱动功能外, 还具有很多保护功能,与传统分立IGBT或模块相比, 其具有体积小、功能多、可靠性高、价格便宜等优点,并在系统性能和可靠性上有进一步的提高,而且由于IPM通态损耗和开关损耗都比较低,使散热器的尺寸减小,故使整个系统尺寸减小。由于驱动电路直接驱动功率元件IGBT,使得IGBT的导通和关断时间不能调节,并且各模块中的IGBT性能不完全一致,导致了功率元件IGBT导通时的电压变化率、关断时的电流变化率等均不一致,进一步影响系统稳定性。
发明内容
本实用新型为解决现有技术功率半导体器件的封装结构中不能调节IGBT的导通和关断时间的问题,从而提供了一种新型的功率半导体器件的封装结构。
为解决上述技术问题,本实用新型提供如下技术方案:
一种功率半导体器件的封装结构,包括:引线框架,所述引线框架包括引脚和本体;设置于所述引线框架本体上的驱动芯片;散热基板;设置于散热基板上的功率芯片,设置于引线框架本体或者散热基板上的电阻,所述电阻连接驱动芯片和功率芯片,所述引线框架本体、驱动芯片、散热基板、功率芯片和电阻均密封于树脂内。
进一步地,所述电阻电极之间的引线框架本体或散热基板上设置有第一凹槽。
优选地,所述凹槽为V型槽或者矩形槽。
优选地,所述驱动芯片、功率芯片和电阻均通过绑线电连接。
进一步地,所述电阻电极与其相邻的绑线之间设置有第二凹槽。
进一步地,所述功率芯片为IGBT。
进一步地,所述电阻与引线框架本体或散热基板接触的一面设置有绝缘层,并通过胶与引线框架本体或者散热基板固定;电阻与引线框架本体或散热基板非接触一面中的两个电极设置有可以绑线的金属层。
优选地,所述金属层为镀金层。
与现有技术相比,本实用新型具有如下有益效果:本实用新型提供的功率半导体器件的封装结构,利用电阻连接驱动芯片和功率芯片,可以通过调节电阻的大小满足整个模块性能。
附图说明
图1是本实用新型第一实施例功率半导体器件的封装结构示意图。
图2是本实用新型第二实施例功率半导体器件的封装结构示意图。
图3是本实用新型第二实施例中电阻区域放大示意图。
图4是本实用新型第三实施例功率半导体器件的封装结构示意图。
图5是本实用新型第三实施例中电阻区域放大示意图。
具体实施方式
为了使本实用新型所解决的技术问题、技术方案及有益效果更加清楚明白,以下结合附图及实施例,对本实用新型进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本实用新型,并不用于限定本实用新型。
图1是本实用新型第一实施例功率半导体器件的封装结构示意图;一种功率半导体器件的封装结构,包括:引线框架10,包括引脚和本体;设置于引线框架本体上的驱动芯片2;散热基板8;设置于散热基板8上的功率芯片4,设置于引线框架本体或者散热基板上的电阻3,所述电阻3连接驱动芯片2和功率芯片4,所述引线框架本体、驱动芯片2、散热基板8、功率芯片4和电阻3均密封于树脂7内。本实用新型利用电阻连接驱动芯片和功率芯片,可以通过调节电阻的大小满足整个模块性能。本实施例中驱动芯片2和功率芯片4可以通过焊锡9与散热基板固定连接,各元器件之间通过绑定线电连接。
图2是本实用新型第二实施例功率半导体器件的封装结构示意图;本实施例以电阻放置在散热基板8上为例,其他实施例中也可以放置在引线框架本体上。在图一的基础上,电阻电极之间的散热基板8上设置有第一凹槽12,该电阻区域的放大示意图见图3,该第一凹槽12可以防止电阻3两端电极短路,有效保护的半导体器件;该第一凹槽12的形状可以根据实际情况设定,可以是V型槽,也可以是矩形槽,还可以是其他形状的,只要能够将两个电极隔开即可。
在本实施例中,电阻电极与其相邻的绑线1之间设置有第二凹槽11,由于电阻3的电极需要与驱动芯片2和功率芯片4分别电连接,并且通过绑线1电连接,电阻电极与其相邻的绑线1为距离电阻电极最近的绑线,该第二凹槽11可以防止电阻3电极的焊锡14流动至其相邻绑线1的地方,可以使得整个半导体模块的稳定性更好。
本实施例中,功率芯片4为IGBT,在IGBT的门极设置电阻3可以调节IGBT的导通和关断时间,电阻3对IGBT的影响详见下表,电阻3用Rg表示:
各模块中的IGBT性能不完全一致,导致了功率元件IGBT导通时的电压变化率、关断时的电流变化率等均不一致,进而可能影响系统稳定性,根据上表可以通过调节电阻的大小来调节IGBT导通和关断时间、电压或电流变化率等,以满足系统对功率半导体的应用要求,从而系统稳定性进一步增强;并可以根据不同需要来调整电阻大小,这样降低了研发成本,缩短了研发周期。
上述的电阻3均为普通电阻,本实施例还提供另一种电阻,如图4是本实用新型第三实施例功率半导体器件的封装结构示意图,图5则是该第三实施例中电阻区域放大示意图,还是以电阻3设置于散热基板8上为例,电阻3与散热基板8接触的一面设置有绝缘层15,并通过胶(图中未画出)与者散热基板8固定;电阻3与散热基板8非接触一面中的两个电极设置有可以绑线的金属层16,通过该金属层16可以与驱动芯片2和功率芯片4电连接,由于金属层16通过绑线与驱动芯片2和功率芯片4电连接,将金属层16设置为镀金层,即在电阻3需要设置金属层的区域镀金处理,这样便不需要在散热基板8上设置凹槽,制作散热基板8的过程简化,进一步缩短了制作周期,从而降低成本。
以上所述仅为本实用新型的较佳实施例而已,并不用以限制本实用新型,凡在本实用新型的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本实用新型的保护范围之内。
Claims (9)
1.一种功率半导体器件的封装结构,其特征在于,包括:
引线框架,所述引线框架包括引脚和本体;
设置于所述引线框架本体上的驱动芯片;
散热基板;
设置于散热基板上的功率芯片,
设置于引线框架本体或者散热基板上的电阻,所述电阻连接驱动芯片和功率芯片,所述引线框架本体、驱动芯片、散热基板、功率芯片和电阻均密封于树脂内。
2.根据权利要求1所述的功率半导体器件的封装结构,其特征在于,所述电阻电极之间的引线框架本体或散热基板上设置有第一凹槽。
3.根据权利要求2所述的功率半导体器件的封装结构,其特征在于,所述第一凹槽为V型槽。
4.根据权利要求2所述的功率半导体器件的封装结构,其特征在于,所述第一凹槽为矩形槽。
5.根据权利要求1所述的功率半导体器件的封装结构,其特征在于,所述驱动芯片、功率芯片和电阻均通过绑线电连接。
6.根据权利要求5所述的功率半导体器件的封装结构,其特征在于,所述电阻电极与其相邻的绑线之间设置有第二凹槽。
7.根据权利要求1所述的功率半导体器件的封装结构,其特征在于,所述功率芯片为IGBT。
8.根据权利要求1至7任一项所述的功率半导体器件的封装结构,其特征在于,所述电阻与引线框架本体或散热基板接触的一面设置有绝缘层,并通过胶与引线框架本体或者散热基板固定;电阻与引线框架本体或散热基板非接触一面中的两个电极设置有可以绑线的金属层。
9.根据权利要求8所述的功率半导体器件的封装结构,其特征在于,所述金属层为镀金层。
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CN106856218A (zh) * | 2016-12-20 | 2017-06-16 | 创维液晶器件(深圳)有限公司 | 一种免封装led结构及其制作方法 |
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