WO2014002625A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2014002625A1
WO2014002625A1 PCT/JP2013/063444 JP2013063444W WO2014002625A1 WO 2014002625 A1 WO2014002625 A1 WO 2014002625A1 JP 2013063444 W JP2013063444 W JP 2013063444W WO 2014002625 A1 WO2014002625 A1 WO 2014002625A1
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WIPO (PCT)
Prior art keywords
wiring
gate
wirings
semiconductor
semiconductor device
Prior art date
Application number
PCT/JP2013/063444
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English (en)
French (fr)
Inventor
久人 道越
平方　宣行
浩史 野津
Original Assignee
住友電気工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 住友電気工業株式会社 filed Critical 住友電気工業株式会社
Priority to EP13810046.6A priority Critical patent/EP2869340A4/en
Priority to CN201380026637.1A priority patent/CN104321867B/zh
Publication of WO2014002625A1 publication Critical patent/WO2014002625A1/ja

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Definitions

  • the present invention relates to a semiconductor device.
  • a semiconductor device including a MOSFET semiconductor chip As an example of a semiconductor device, a semiconductor device including a MOSFET semiconductor chip is known (see Patent Document 1). In such a semiconductor device, a semiconductor chip mounted on a die pad is connected to a gate lead via a gate wire and connected to a source lead via a plurality of source wires.
  • the length of the source wire closest to the gate wire is the same as or longer than the lengths of the other source wires. For this reason, when the currents flowing through the plurality of source wires change with time, the influence of the mutual inductance that the gate wire receives from the plurality of source wires due to the electromagnetic induction effect increases. As a result, in the semiconductor device, the temporal variation of the gate voltage applied to the gate wire becomes large.
  • a semiconductor device includes at least one semiconductor chip, a gate wiring connected to the at least one semiconductor chip, a first wiring connected to the at least one semiconductor chip, and the at least one semiconductor chip.
  • the first wiring is disposed between the second wiring, the first wiring is the wiring closest to the gate wiring, and the length of the first portion of the gate wiring facing the first wiring is The length is shorter than the length of the second portion of the gate wiring facing the second wiring.
  • the first portion of the gate wiring may be a portion located at the intersection of the perpendicular and the gate wiring when a perpendicular is drawn from each point of the first wiring to the gate wiring.
  • the second portion of the gate wiring may be a portion located at the intersection of the perpendicular and the gate wiring when a perpendicular is drawn from each point of the second wiring to the gate wiring.
  • the gate wiring is affected by the mutual inductance from the first wiring and the second wiring due to the electromagnetic induction effect.
  • the mutual inductance is determined by the distance between the gate wiring, the first wiring, and the second wiring, and the length of the portion of the gate wiring that faces the first wiring and the second wiring.
  • the distance between the gate wiring and the first wiring and the second wiring is short, the mutual inductance increases.
  • the length of the portion of the gate wiring facing the first wiring and the second wiring is long, the mutual inductance increases.
  • the length d1 of the first portion of the gate wiring facing the first wiring closest to the gate wiring is larger than the length d2 of the second portion of the gate wiring facing the second wiring. short. Therefore, since the influence of the mutual inductance that the gate wiring receives from the first wiring due to the electromagnetic induction effect is small, the temporal variation of the gate voltage is suppressed.
  • the at least one semiconductor chip is a plurality of semiconductor chips, the plurality of semiconductor chips are arranged along a first direction, and a second direction perpendicular to the first direction between adjacent semiconductor chips
  • the gate wiring, the first wiring, and the second wiring may be inverted with respect to an axis extending along the line.
  • the influence of the mutual inductance that the gate wiring of each semiconductor chip receives from the first wiring and the second wiring due to the electromagnetic induction effect is made uniform, so that variations in gate voltage between adjacent semiconductor chips are reduced.
  • the material of the at least one semiconductor chip may include a wide band gap semiconductor.
  • the semiconductor device may further include a wiring pattern connected to the gate wiring.
  • the length of the gate wiring can be shortened by setting the distance between the semiconductor chip and the wiring pattern small. Therefore, since the influence of the mutual inductance which a gate wiring receives from a 1st wiring and a 2nd wiring by an electromagnetic induction effect is further reduced, the temporal fluctuation
  • the semiconductor device includes a first lead electrically connected to the gate wiring, a second lead electrically connected to the first wiring and the second wiring, and the at least one semiconductor. And a die pad having a chip mounting surface on which the chip is mounted.
  • the present invention it is possible to provide a semiconductor device capable of suppressing temporal fluctuation of the gate voltage.
  • FIG. 1 is a plan view schematically showing a semiconductor device according to a first embodiment. It is a figure which shows an example of the time change of the gate voltage in the semiconductor device which concerns on 1st Embodiment. It is a top view which shows typically the semiconductor device for a reference. It is a figure which shows an example of the time fluctuation
  • FIG. 1 is a plan view schematically showing the semiconductor device according to the first embodiment.
  • a semiconductor device 10 shown in FIG. 1 is a resin-encapsulated semiconductor device.
  • the semiconductor device 10 includes a plurality of semiconductor chips 14a to 14d.
  • the semiconductor chips 14a to 14d can be connected in parallel.
  • the semiconductor device 10 may include a die pad 12 having a chip mounting surface 12a on which semiconductor chips 14a to 14d are mounted.
  • the die pad 12 can be electrically connected to the semiconductor chips 14a to 14d.
  • the die pad 12 has a plate shape, for example.
  • the chip mounting surface 12a is, for example, a rectangle.
  • Examples of the material of the die pad 12 include metals such as copper (Cu) and a copper alloy.
  • a through-hole 26 that penetrates the die pad 12 in the thickness direction can be formed in the die pad 12.
  • the through hole 26 is a hole through which a screw is passed when the semiconductor device 10 is fixed to another member (for example, a heat sink or the like) by, for example, a screw.
  • the semiconductor chips 14a to 14d are mounted at predetermined positions on the chip mounting surface 12a.
  • Examples of the semiconductor chips 14a to 14d include a transistor such as a MOS-FET and an insulated gate bipolar transistor (IGBT), a diode such as a PN junction diode and a Schottky barrier diode.
  • the semiconductor chips 14a to 14d can be mounted on the chip mounting surface 12a via an adhesive layer made of a material including lead-containing metal solder, lead-free metal solder, conductive resin, or the like.
  • Examples of the material of the semiconductor chips 14a to 14d include a wide band gap semiconductor, silicon and other semiconductors.
  • a wide band gap semiconductor has a band gap larger than that of silicon. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and diamond.
  • Each of the semiconductor chips 14a to 14d may have a gate electrode pad GP and an electrode pad SP.
  • the gate electrode pad GP can be formed at the end of the main surface of the semiconductor chips 14a to 14d.
  • a gate liner GL may be connected to the gate electrode pad GP.
  • the electrode pad SP can be formed in a region where the gate electrode pad GP and the gate liner GL are not formed on the main surfaces of the semiconductor chips 14a to 14d.
  • the electrode pad SP corresponds to the source electrode pad.
  • the electrode pad SP corresponds to an emitter electrode pad.
  • Further electrode pads such as drain electrode pads or collector electrode pads can be formed on the entire back surface of the semiconductor chips 14a to 14d.
  • a gate wiring 30a, a first wiring 32a, and a second wiring 34a are connected to the semiconductor chip 14a.
  • the gate wiring 30a can be connected to the gate electrode pad GP of the semiconductor chip 14a.
  • the first wiring 32a and the second wiring 34a can be connected to the electrode pad SP of the semiconductor chip 14a.
  • gate wirings 30b to 30d can be connected to the gate electrode pads GP of the semiconductor chips 14b to 14d, respectively.
  • First wirings 32b to 32d can be connected to the electrode pads SP of the semiconductor chips 14b to 14d, respectively.
  • Second wirings 34b to 34d can be connected to the electrode pads SP of the semiconductor chips 14b to 14d, respectively.
  • the first wirings 32a to 32d and the second wirings 34a to 34d are wirings for supplying current to the semiconductor chips 14a to 14d.
  • the gate wirings 30a to 30d are wirings for switching currents flowing through the first wirings 32a to 32d and the second wirings 34a to 34d.
  • the first wirings 32a to 32d and the second wirings 34a to 34d may be distributed in the electrode pad SP in order to suppress current concentration.
  • the first wirings 32a to 32d and the second wirings 34a to 34d extend along the gate wirings 30a to 30d.
  • the gate wirings 30a to 30d, the first wirings 32a to 32d, and the second wirings 34a to 34d may extend along the XY plane.
  • the first wirings 32a to 32d are arranged between the gate wirings 30a to 30d and the second wirings 34a to 34d.
  • the first wiring 32a is disposed between the gate wiring 30a and the second wiring 34a.
  • the first wirings 32a to 32d are wirings closest to the gate wirings 30a to 30d, respectively.
  • the length d1 of the first portion 30x of the gate wirings 30a to 30d facing the first wirings 32a to 32d is the length of the second portion 30y of the gate wirings 30a to 30d facing the second wirings 34a to 34d. Shorter than d2.
  • the length d2 may be not less than 1.2 times the length d1.
  • the lengths d1 and d2 can be measured by looking at the first wirings 32a to 32d and the second wirings 34a to 34d from the Z direction perpendicular to the main surfaces of the semiconductor chips 14a to 14d.
  • the first portion 30x of the gate wirings 30a to 30d is located at the intersection of the vertical line and the gate wirings 30a to 30d when a vertical line is drawn from each point of the first wirings 32a to 32d to the gate wirings 30a to 30d. Can be part.
  • the second portion 30y of the gate wirings 30a to 30d is located at the intersection of the perpendicular and the gate wirings 30a to 30d when a perpendicular is drawn from each point of the second wirings 34a to 34d to the gate wirings 30a to 30d. Can be part.
  • the semiconductor chips 14a to 14d can be arranged along the X direction (first direction).
  • An axis Ax extending along the Y direction (second direction perpendicular to the first direction) is disposed between adjacent semiconductor chips 14a to 14d.
  • the gate wirings 30a to 30d, the first wirings 32a to 32d, and the second wirings 34a to 34d can be arranged so as to be inverted with respect to the axis Ax.
  • the gate electrode pad GP and the electrode pad SP can also be arranged in an inverted manner with respect to the axis Ax.
  • the gate line 30a is disposed at a position symmetrical to the gate line 30b with respect to the axis Ax.
  • the semiconductor device 10 may include a first lead 18, a second lead 20, and a third lead 16.
  • the leads 16, 18, and 20 extend along the Y direction, and are arranged along the X direction.
  • the lead 16 is located between the leads 18 and 20.
  • the leads 16, 18, 20 and the die pad 12 may constitute a lead frame.
  • the semiconductor device 10 is a power semiconductor device used for a power source or the like, for example.
  • An example of the package form of the semiconductor device 10 is a general TO series. Examples of TO series include TO-247, TO-220, TO-263 (D2-PAK), and TO-252 (D-PAK).
  • the lead 18 is electrically connected to the gate wirings 30a to 30d.
  • the lead 20 is electrically connected to the first wirings 32a to 32d and the second wirings 34a to 34d.
  • the inner end of the lead 16 is mechanically and integrally connected to the die pad 12. Since the die pad 12 has conductivity, the lead 16 and the die pad 12 are electrically connected. Examples of the material of the lead 16 include the same material as that of the die pad 12.
  • the lead 16 corresponds to the drain electrode terminal
  • the lead 18 corresponds to the gate electrode terminal
  • the lead 20 corresponds to the source electrode terminal.
  • the semiconductor chips 14a to 14d include IGBTs
  • the lead 16 corresponds to the collector electrode terminal
  • the lead 18 corresponds to the gate electrode terminal
  • the lead 20 corresponds to the emitter electrode terminal.
  • the material of the leads 18 and 20 include metals such as copper and copper alloys.
  • the semiconductor device 10 can include a wiring pattern 36 connected to the gate wirings 30a to 30d, and an insulating member 38 disposed between the die pad 12 and the wiring pattern 36.
  • the wiring pattern 36 is connected to the lead 18 through the wiring 40.
  • the insulating member 38 is interposed between the die pad 12 and the wiring pattern 36 in the Z direction.
  • the insulating member 38 is, for example, an insulating substrate or an insulating layer. Examples of the material of the insulating member 38 include a resin such as an epoxy resin or ceramics.
  • the die pad 12, the insulating member 38, and the wiring pattern 36 can be connected to each other by an adhesive.
  • the semiconductor device 10 may include a wiring pattern 42 connected to the first wirings 32a to 32d and the second wirings 34a to 34d, and an insulating member 44 disposed between the die pad 12 and the wiring pattern 42.
  • the wiring pattern 42 is connected to the leads 20 via a plurality of wirings 46.
  • the insulating member 44 is interposed between the die pad 12 and the wiring pattern 42 in the Z direction.
  • the insulating member 44 is, for example, an insulating substrate or an insulating layer. Examples of the material of the insulating member 44 include a resin such as an epoxy resin or ceramics.
  • the die pad 12, the insulating member 44, and the wiring pattern 42 can be connected to each other by an adhesive.
  • the wiring patterns 36 and 42 are also called wiring bars. Examples of the material of the wiring patterns 36 and 42 include the same material as that of the die pad 12.
  • the gate wirings 30a to 30d, the first wirings 32a to 32d, the second wirings 34a to 34d, and the wirings 40 and 46 may be wires or bonding ribbons.
  • Examples of materials of the gate wirings 30a to 30d, the first wirings 32a to 32d, the second wirings 34a to 34d, and the wirings 40 and 46 include metals such as aluminum, gold, and copper.
  • the gate wirings 30a to 30d, the first wirings 32a to 32d, the second wirings 34a to 34d, and the wirings 40 and 46 are, for example, wiring patterns 36 and 42, a semiconductor chip by wire bonding using ultrasonic waves or pressure. 14a to 14d or leads 18 and 20.
  • the die pad 12, the semiconductor chips 14a to 14d, the inner end portion of the lead 18, and the inner end portion of the lead 20 can be covered with a resin portion 24. Inner ends of the leads 16, 18, and 20 are inserted into the resin portion 24. Of the leads 16, 18, and 20, the portion inside the resin portion 24 is a so-called inner lead portion. Of the leads 16, 18, and 20, the portion outside the resin portion 24 is an outer lead portion. An example of the outer shape of the resin portion 24 is a substantially rectangular parallelepiped. Examples of the material of the resin portion 24 include thermoplastic resins such as polyphenylene sulfide resin (PPS resin) and liquid crystal polymer.
  • the resin portion 24 can be formed by molding the die pad 12 and the semiconductor chips 14a to 14d with a thermoplastic resin.
  • a through hole 28 is formed in the resin portion 24 with the central axis of the through hole 26 of the die pad 12 as the central axis.
  • the through hole 28 is a hole through which a screw is passed in the case of screwing or the like, like the through hole 26.
  • the diameter of the through hole 28 is smaller than the diameter of the through hole 26.
  • the gate wirings 30a to 30d become the first wirings 32a to 32d and the second wirings 34a to 34d due to the electromagnetic induction effect. Affected by mutual inductance.
  • the gate voltages of the semiconductor chips 14a to 14d vary with time.
  • the mutual inductance is opposed to the distance between the gate wirings 30a to 30d and the first wirings 32a to 32d and the second wirings 34a to 34d, and to the first wirings 32a to 32d and the second wirings 34a to 34d. It is determined by the length of the gate wirings 30a to 30d.
  • the length d1 of the first portion 30x of the gate wiring 30b facing the first wiring 32b closest to the gate wiring 30b is equal to the second length of the gate wiring 30b facing the second wiring 34b. It is shorter than the length d2 of the portion 30y. Therefore, the influence of the mutual inductance that the gate wiring 30b receives from the first wiring 32b due to the electromagnetic induction effect is relatively small. Therefore, temporal variation of the gate voltage is suppressed.
  • the gate wirings 30a to 30d, the first wirings 32a to 32d, and the second wirings 34a to 34d are inverted with respect to the axis Ax extending in the Y direction between the adjacent semiconductor chips 14a to 14d. Can be arranged. In this case, the influence of the mutual inductance that the gate wirings 30a to 30d of the semiconductor chips 14a to 14d receive from the first wirings 32a to 32d and the second wirings 34a to 34d by the electromagnetic induction effect is made uniform. Therefore, variation in gate voltage between adjacent semiconductor chips 14a to 14d is reduced.
  • the material of the semiconductor chips 14a to 14d includes a wide bandgap semiconductor
  • a larger current than the semiconductor chips 14a to 14d made of silicon is allowed to flow through the first wirings 32a to 32d and the second wirings 34a to 34d. It becomes possible. For this reason, in the wide band gap semiconductor, the temporal variation of the gate voltage tends to be large, so that the effect of suppressing the temporal variation of the gate voltage is great.
  • the semiconductor device 10 includes the wiring pattern 36 connected to the gate wirings 30a to 30d, the distance between the semiconductor chips 14a to 14d and the wiring pattern 36 can be set small. As a result, the lengths of the gate wirings 30a to 30d can be shortened. Thereby, the influence of the mutual inductance that the gate wirings 30a to 30d receive from the first wirings 32a to 32d and the second wirings 34a to 34d due to the electromagnetic induction effect is further reduced. Therefore, temporal variation of the gate voltage is further suppressed.
  • the semiconductor device 10 may include leads 18 and 20 and a die pad 12. In this case, it is usually difficult to sufficiently separate the gate wiring from the first wiring and the second wiring. Therefore, since the temporal variation of the gate voltage tends to increase, the effect of suppressing the temporal variation of the gate voltage is great.
  • FIG. 2 is a diagram illustrating an example of temporal variation of the gate voltage in the semiconductor device according to the first embodiment.
  • FIG. 2 shows an example of the influence of mutual inductance that the gate wiring 30b of the semiconductor chip 14b receives from the first wirings 32a to 32d and the second wirings 34a to 34d. The influence of the self-inductance of the gate wiring 30b is not considered.
  • the current value flowing through the semiconductor chips 14a to 14d connected in parallel is 50A. Therefore, a current of 12.5 A flows through each of the semiconductor chips 14a to 14d.
  • the gate voltage during operation of the semiconductor chips 14a to 14d is 15V. Switching time is 20 ns.
  • the length of the gate wiring 30b is 3.2 mm.
  • the length d1 of the first portion 30x of the gate wiring 30b is 2.4 mm.
  • the length d2 of the second portion 30y of the gate wiring 30b is 3.2 mm.
  • the shortest distance is adopted as the distance between the gate wiring 30b and the first wirings 32a to 32d and the second wirings 34a to 34d.
  • the shortest distance is a distance between positions P1 to P8 on the first wirings 32a to 32d and the second wirings 34a to 34d and the gate wiring 30b.
  • the distance between the position P1 on the second wiring 34a and the gate wiring 30b is 3.72 mm.
  • the mutual inductance received by the gate wiring 30b from the second wiring 34a is 0.22 nH.
  • the variation of the gate voltage due to this is 0.14V.
  • the total mutual inductance that the gate wiring 30b receives from the first wirings 32a to 32d and the second wirings 34a to 34d is 1.81 nH.
  • the total fluctuation of the gate voltage in the gate wiring 30b is 1.14V (1.1V in two significant figures).
  • the mutual inductance received by the gate wiring 30a from the first wirings 32a to 32d and the second wirings 34a to 34d is calculated.
  • the total mutual inductance that the gate wiring 30a receives from the first wirings 32a to 32d and the second wirings 34a to 34d is 1.81 nH. Further, the fluctuation of the gate voltage in the gate wiring 30a is calculated. The total gate voltage fluctuation in the gate wiring 30a is 1.1 V (2 significant digits). Therefore, since the gate voltage variation between the adjacent semiconductor chips 14a and 14b is the same, there is no variation in the gate voltage variation between the adjacent semiconductor chips 14a and 14b.
  • FIG. 3 is a plan view schematically showing a semiconductor device for reference.
  • a semiconductor device 110 shown in FIG. 3 includes semiconductor chips 114a to 114d instead of the semiconductor chips 14a to 14d, gate wirings 130a to 130d instead of the gate wirings 30a to 30d, and first wirings 32a to 32d.
  • the semiconductor device 10 has the same configuration as that of the semiconductor device 10 except that the first wirings 132a to 132d are provided, and the second wirings 134a to 134d are provided instead of the second wirings 34a to 34d.
  • the gate wirings 130a to 130d are arranged between the first wirings 132a to 132d and the second wirings 134a to 134d.
  • the lengths of the portions of the gate wirings 130a to 130d facing the first wirings 132a to 132d and the second wirings 134a to 134d are all the same as the length of the gate wiring 130b.
  • FIG. 4 is a diagram illustrating an example of temporal variation of the gate voltage in the reference semiconductor device.
  • FIG. 4 shows an example of the influence of the mutual inductance that the gate wiring 130b of the semiconductor chip 114b receives from the first wirings 132a to 132d and the second wirings 134a to 134d.
  • the influence of the self-inductance of the gate wiring 130b is not considered.
  • the value of current flowing through the semiconductor chips 114a to 114d connected in parallel is 50A. Therefore, a current of 12.5 A flows through each of the semiconductor chips 114a to 114d.
  • the gate voltage during the operation of the semiconductor chips 114a to 114d is 15V. Switching time is 20 ns.
  • the length of the gate wiring 130b is 3.2 mm.
  • the length of the gate wiring 130b facing the first wiring 132a to 132d and the second wiring 134a to 134d is 3.2 mm.
  • the shortest distance is adopted as the distance between the gate wiring 130b and the first wirings 132a to 132d and the second wirings 134a to 134d.
  • the shortest distance is a distance between positions P11 to P18 on the first wirings 132a to 132d and the second wirings 134a to 134d and the gate wiring 130b.
  • the distance between the position P11 on the second wiring 134a and the gate wiring 130b is 4.54 mm.
  • the calculation results of the mutual inductance and the fluctuation of the gate voltage are shown in FIG.
  • the mutual inductance that the gate wiring 130b receives from the second wiring 134a is 0.10 nH.
  • the variation of the gate voltage due to this is 0.07V.
  • the total mutual inductance received by the gate wiring 130b is 1.90 nH.
  • the total fluctuation of the gate voltage in the gate wiring 130b is 1.19V (1.2V in two significant figures).
  • the mutual inductance received by the gate wiring 130a from the first wirings 132a to 132d and the second wirings 134a to 134d is calculated.
  • the total mutual inductance received by the gate line 130a from the first lines 132a to 132d and the second lines 134a to 134d is 1.74 nH. Further, the fluctuation of the gate voltage in the gate wiring 130a is calculated. The total gate voltage fluctuation in the gate wiring 130a is 1.1 V (2 significant digits). Therefore, the variation in the gate voltage between the adjacent semiconductor chips 114a and 114b differs by 0.1 V, and thus the variation in the gate voltage between the adjacent semiconductor chips 114a and 114b varies.
  • FIG. 5 is a plan view schematically showing the semiconductor device according to the second embodiment.
  • a semiconductor device 10a shown in FIG. 5 is a case-type semiconductor device.
  • the semiconductor device 10a includes semiconductor chips 14a to 14l, gate wirings 30a to 30l connected to the semiconductor chips 14a to 14l, first wirings 32a to 32l connected to the semiconductor chips 14a to 14l, and a semiconductor chip, respectively.
  • Second wirings 34a to 34l connected to 14a to 14l, respectively, and a case 60 are provided.
  • the semiconductor chips 14e, 14g, 14i, and 14k can have the same configuration as the semiconductor chip 14a.
  • the semiconductor chips 14f, 14h, 14j, and 14l can have the same configuration as the semiconductor chip 14b.
  • the semiconductor chips 14a to 14f are provided on a wiring pattern 52a formed on the first substrate 50a.
  • Wiring patterns 54a and 56a may be formed on the substrate 50a.
  • the wiring pattern 54a can be connected to the semiconductor chips 14a to 14f by gate wirings 30a to 30f, respectively.
  • the wiring pattern 56a can be connected to the semiconductor chips 14a to 14f by the first wirings 32a to 32f and the second wirings 34a to 34f, respectively.
  • the semiconductor chips 14g to 14l are provided on the wiring pattern 52b formed on the second substrate 50b.
  • Wiring patterns 54b and 56b may be formed on the substrate 50b.
  • the wiring pattern 54b can be connected to the semiconductor chips 14g to 14l by gate wirings 30g to 30l, respectively.
  • the wiring pattern 56b can be connected to the semiconductor chips 14g to 14l by the first wirings 32g to 32l and the second wirings 34g to 34l, respectively.
  • the case 60 may include a bottom portion 60a for mounting the substrates 50a and 50b. On the bottom portion 60a, a base portion 60b for placing the bus bars 72a to 72c may be disposed. The bus bars 72a to 72c can be electrically connected to the semiconductor chips 14a to 14l.
  • the case 60 may include a first side wall 60c that surrounds the substrates 50a and 50b and the base 60b, and a second side wall 60d that surrounds the first side wall 60c.
  • the opening of the case 60 can be sealed with a lid.
  • the material of the case 60 include resins such as engineering plastics such as polybutylene terephthalate (PBT) or polyphenylene sulfide (PPS) resin.
  • the lid material include a thermoplastic resin.
  • a gel such as a silicone gel may be injected into the case 60 for stress relaxation. In the semiconductor device 10a, the same effects as the semiconductor device 10 can be obtained.
  • FIG. 6 is a plan view schematically showing a semiconductor device for reference.
  • the semiconductor device 110a shown in FIG. 6 includes semiconductor chips 114a to 114l instead of the semiconductor chips 14a to 14l, gate gates 130a to 130l instead of the gate wirings 30a to 30l, and the first wirings 32a to 32l.
  • the semiconductor device 10a has the same configuration as the semiconductor device 10a except that the first wirings 132a to 132l are provided and the second wirings 134a to 134l are provided instead of the second wirings 34a to 34l.
  • the gate wirings 130a to 130l are arranged between the first wirings 132a to 132l and the second wirings 134a to 134l.
  • the lengths of the portions of the gate wirings 130a to 130l facing the first wirings 132a to 132l and the second wirings 134a to 134l are all the same as the length of the gate wiring 130b.
  • the semiconductor devices 10 and 10a may include only one semiconductor chip.
  • the semiconductor devices 10 and 10a may include a third wiring connected to the semiconductor chip.
  • the semiconductor chips 14a to 14l may include a horizontal transistor instead of the vertical transistor.
  • electrode pads are not formed on the back surfaces of the semiconductor chips 14a to 14l, and further electrode pads such as drain electrode pads or collector electrode pads are formed on the front surfaces of the semiconductor chips 14a to 14l.
  • the semiconductor device 10 may not include the wiring patterns 36 and 42.
  • the gate wirings 30a to 30d are connected to the leads 18.
  • the first wirings 32 a to 32 d and the second wirings 34 a to 34 d are connected to the lead 20.

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Abstract

半導体装置（１０）は、少なくとも１つの半導体チップ（１４ａ～１４ｄ）と、少なくとも１つの半導体チップに接続されるゲート配線（３０ａ～３０ｄ）と、少なくとも１つの半導体チップに接続される第１の配線（３２ａ～３２ｄ）と、少なくとも１つの半導体チップに接続される第２の配線（３４ａ～３４ｄ）とを備える。第１の配線及び第２の配線は、ゲート配線に沿って延びている。第１の配線はゲート配線と第２の配線との間に配置される。第１の配線はゲート配線に最も近い配線である。第１の配線に対向するゲート配線の第１の部分（３０ｘ）の長さ（ｄ１）は、第２の配線に対向するゲート配線の第２の部分（３０ｙ）の長さ（ｄ２）よりも短い。

Description

半導体装置
　本発明は、半導体装置に関する。
　半導体装置の例として、ＭＯＳＦＥＴの半導体チップを備えた半導体装置が知られている（特許文献１参照）。このような半導体装置では、ダイパッドに搭載された半導体チップが、ゲートワイヤを介してゲートリードに接続され、複数のソースワイヤを介してソースリードに接続される。
特許第４７４６０６１号公報
　上記半導体装置では、ゲートワイヤに最も近いソースワイヤの長さがその他のソースワイヤの長さと同じか又はより長くなっている。そのため、複数のソースワイヤに流れる電流が時間的に変化すると、電磁誘導効果によってゲートワイヤが複数のソースワイヤから受ける相互インダクタンスの影響が大きくなる。その結果、上記半導体装置では、ゲートワイヤに印加されるゲート電圧の時間的な変動が大きくなってしまう。
　本発明は、ゲート電圧の時間的な変動を抑制できる半導体装置を提供することを目的とする。
　本発明の一側面に係る半導体装置は、少なくとも１つの半導体チップと、前記少なくとも１つの半導体チップに接続されるゲート配線と、前記少なくとも１つの半導体チップに接続される第１の配線と、前記少なくとも１つの半導体チップに接続される第２の配線と、を備え、前記第１の配線及び前記第２の配線が、前記ゲート配線に沿って延びており、前記第１の配線が前記ゲート配線と前記第２の配線との間に配置され、前記第１の配線が前記ゲート配線に最も近い配線であり、前記第１の配線に対向する前記ゲート配線の第１の部分の長さが、前記第２の配線に対向する前記ゲート配線の第２の部分の長さよりも短い。ゲート配線の第１の部分は、第１の配線の各点からゲート配線に垂線が引かれたときに垂線とゲート配線との交点に位置する部分であり得る。ゲート配線の第２の部分は、第２の配線の各点からゲート配線に垂線が引かれたときに垂線とゲート配線との交点に位置する部分であり得る。
　第１の配線及び第２の配線に流れる電流が時間的に変化すると、電磁誘導効果によってゲート配線が第１の配線及び第２の配線から相互インダクタンスの影響を受ける。その結果、半導体チップのゲート電圧が時間的に変動する。相互インダクタンスは、ゲート配線と第１の配線及び第２の配線との間の距離と、第１の配線及び第２の配線に対向するゲート配線の部分の長さとによって決定される。ゲート配線と第１の配線及び第２の配線との間の距離が短いと、相互インダクタンスは大きくなる。第１の配線及び第２の配線に対向するゲート配線の部分の長さが長いと、相互インダクタンスは大きくなる。
　上記半導体装置では、ゲート配線に最も近い第１の配線に対向するゲート配線の第１の部分の長さｄ１が、第２の配線に対向するゲート配線の第２の部分の長さｄ２よりも短い。そのため、電磁誘導効果によってゲート配線が第１の配線から受ける相互インダクタンスの影響が小さいので、ゲート電圧の時間的な変動が抑制される。
　前記少なくとも１つの半導体チップが複数の半導体チップであり、前記複数の半導体チップが第１の方向に沿って配列されており、隣接する半導体チップ間において前記第１の方向に垂直な第２の方向に沿って延びる軸に対して、前記ゲート配線、前記第１の配線及び前記第２の配線が反転して配置されてもよい。
　この場合、各半導体チップのゲート配線が電磁誘導効果によって第１の配線及び第２の配線から受ける相互インダクタンスの影響が均一化されるので、隣接する半導体チップ間のゲート電圧のばらつきが低減される。
　前記少なくとも１つの半導体チップの材料が、ワイドバンドギャップ半導体を含んでもよい。
　この場合、シリコンからなる半導体チップに比べて大きな電流を第１の配線及び第２の配線に流すことが可能になる。そのため、ワイドバンドギャップ半導体では、ゲート電圧の時間的な変動が大きくなる傾向にあるので、ゲート電圧の時間的な変動を抑制することによる効果が大きい。
　上記半導体装置が、前記ゲート配線に接続される配線パターンを更に備えてもよい。
　この場合、半導体チップと配線パターンとの間の距離を小さく設定することによって、ゲート配線の長さが短くなり得る。これにより、電磁誘導効果によってゲート配線が第１の配線及び第２の配線から受ける相互インダクタンスの影響が更に低減されるので、ゲート電圧の時間的な変動が更に抑制される。
　上記半導体装置が、前記ゲート配線に電気的に接続される第１のリードと、前記第１の配線及び前記第２の配線に電気的に接続される第２のリードと、前記少なくとも１つの半導体チップが搭載されるチップ搭載面を有するダイパッドと、を更に備えてもよい。
　リードを備えた半導体装置では、通常、ゲート配線を第１の配線及び第２の配線から十分に離すことが困難である。そのため、リードを備えた半導体装置では、ゲート電圧の時間的な変動が大きくなる傾向にあるので、ゲート電圧の時間的な変動を抑制することによる効果が大きい。
　本発明によれば、ゲート電圧の時間的な変動を抑制できる半導体装置が提供され得る。
第１実施形態に係る半導体装置を模式的に示す平面図である。 第１実施形態に係る半導体装置におけるゲート電圧の時間的な変動の一例を示す図である。 参照用の半導体装置を模式的に示す平面図である。 参照用の半導体装置におけるゲート電圧の時間的な変動の一例を示す図である。 第２実施形態に係る半導体装置を模式的に示す平面図である。 参照用の半導体装置を模式的に示す平面図である。
　以下、添付図面を参照しながら本発明の実施形態が詳細に説明される。図面の説明において、同一又は同等の要素には同一符号が用いられ、重複する説明は省略される。図１、図３、図５及び図６にはＸＹＺ直交座標系が示されている。
（第１実施形態）
　図１は、第１実施形態に係る半導体装置を模式的に示す平面図である。図１に示される半導体装置１０は、樹脂封止型の半導体装置である。半導体装置１０は、複数の半導体チップ１４ａ～１４ｄを備える。半導体チップ１４ａ～１４ｄは並列接続され得る。
　半導体装置１０は、半導体チップ１４ａ～１４ｄが搭載されるチップ搭載面１２ａを有するダイパッド１２を備え得る。ダイパッド１２は、半導体チップ１４ａ～１４ｄと電気的に接続され得る。ダイパッド１２は例えば板状を呈している。チップ搭載面１２ａは、例えば長方形である。ダイパッド１２の材料の例は、銅（Ｃｕ）及び銅合金等の金属を含む。ダイパッド１２には、板厚方向にダイパッド１２を貫通する貫通孔２６が形成され得る。貫通孔２６は、例えば螺子によって半導体装置１０を他の部材（例えばヒートシンク等）に固定する際に、螺子を通すための孔である。
　半導体チップ１４ａ～１４ｄは、チップ搭載面１２ａの所定位置に搭載される。半導体チップ１４ａ～１４ｄの例は、ＭＯＳ－ＦＥＴ、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）等のトランジスタ、ＰＮ接合ダイオード、ショットキーバリアダイオード等のダイオードを含む。半導体チップ１４ａ～１４ｄは、鉛入り金属半田、鉛を含まない金属半田又は導電性樹脂等を含む材料から構成される接着層を介してチップ搭載面１２ａに実装され得る。半導体チップ１４ａ～１４ｄの材料の例は、ワイドバンドギャップ半導体、シリコンその他の半導体を含む。ワイドバンドギャップ半導体は、シリコンのバンドギャップよりも大きいバンドギャップを有する。ワイドバンドギャップ半導体の例は、シリコンカーバイド（ＳｉＣ）、窒化ガリウム（ＧａＮ）、ダイヤモンドを含む。
　半導体チップ１４ａ～１４ｄのそれぞれは、ゲート電極パッドＧＰ及び電極パッドＳＰを有し得る。ゲート電極パッドＧＰは、半導体チップ１４ａ～１４ｄの主面における端部に形成され得る。ゲート電極パッドＧＰにはゲートライナーＧＬが接続されてもよい。電極パッドＳＰは、半導体チップ１４ａ～１４ｄの主面においてゲート電極パッドＧＰ及びゲートライナーＧＬが形成されていない領域に形成され得る。
　半導体チップ１４ａ～１４ｄがＭＯＳ－ＦＥＴを含む場合、電極パッドＳＰはソース電極パッドに対応する。半導体チップ１４ａ～１４ｄがＩＧＢＴを含む場合、電極パッドＳＰはエミッタ電極パッドに対応する。半導体チップ１４ａ～１４ｄの裏面全体には、例えばドレイン電極パッド又はコレクタ電極パッド等の更なる電極パッドが形成され得る。
　半導体チップ１４ａには、ゲート配線３０ａ、第１の配線３２ａ及び第２の配線３４ａが接続される。ゲート配線３０ａは半導体チップ１４ａのゲート電極パッドＧＰに接続され得る。第１の配線３２ａ及び第２の配線３４ａは、半導体チップ１４ａの電極パッドＳＰに接続され得る。同様に、半導体チップ１４ｂ～１４ｄのゲート電極パッドＧＰには、それぞれゲート配線３０ｂ～３０ｄが接続され得る。半導体チップ１４ｂ～１４ｄの電極パッドＳＰには、それぞれ第１の配線３２ｂ～３２ｄが接続され得る。半導体チップ１４ｂ～１４ｄの電極パッドＳＰには、それぞれ第２の配線３４ｂ～３４ｄが接続され得る。第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄは、半導体チップ１４ａ～１４ｄに電流を供給するための配線である。ゲート配線３０ａ～３０ｄは、第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄに流れる電流をスイッチングするための配線である。第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄは、電流集中を抑制するために電極パッドＳＰにおいて分散配置されてもよい。
　第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄは、ゲート配線３０ａ～３０ｄに沿って延びている。ゲート配線３０ａ～３０ｄ、第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄは、ＸＹ平面に沿って延びてもよい。第１の配線３２ａ～３２ｄは、ゲート配線３０ａ～３０ｄと第２の配線３４ａ～３４ｄとの間に配置される。例えば、第１の配線３２ａはゲート配線３０ａと第２の配線３４ａとの間に配置される。第１の配線３２ａ～３２ｄは、それぞれゲート配線３０ａ～３０ｄに最も近い配線である。第１の配線３２ａ～３２ｄに対向するゲート配線３０ａ～３０ｄの第１の部分３０ｘの長さｄ１は、第２の配線３４ａ～３４ｄに対向するゲート配線３０ａ～３０ｄの第２の部分３０ｙの長さｄ２よりも短い。長さｄ２は長さｄ１の１．２倍以上であってもよい。長さｄ１及びｄ２は、半導体チップ１４ａ～１４ｄの主面に垂直なＺ方向から第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄを見て測定され得る。ゲート配線３０ａ～３０ｄの第１の部分３０ｘは、第１の配線３２ａ～３２ｄの各点からゲート配線３０ａ～３０ｄに垂線が引かれたときに垂線とゲート配線３０ａ～３０ｄとの交点に位置する部分であり得る。ゲート配線３０ａ～３０ｄの第２の部分３０ｙは、第２の配線３４ａ～３４ｄの各点からゲート配線３０ａ～３０ｄに垂線が引かれたときに垂線とゲート配線３０ａ～３０ｄとの交点に位置する部分であり得る。
　半導体チップ１４ａ～１４ｄはＸ方向（第１の方向）に沿って配列され得る。隣接する半導体チップ１４ａ～１４ｄ間には、Ｙ方向（第１の方向に垂直な第２の方向）に沿って延びる軸Ａｘが配置される。ゲート配線３０ａ～３０ｄ、第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄは、軸Ａｘに対して反転して配置され得る。ゲート電極パッドＧＰ及び電極パッドＳＰも軸Ａｘに対して反転して配置され得る。例えば、ゲート配線３０ａは軸Ａｘに対してゲート配線３０ｂと対称な位置に配置される。
　半導体装置１０は、第１のリード１８、第２のリード２０、第３のリード１６を備えてもよい。リード１６，１８，２０は、Ｙ方向に沿って延びており、Ｘ方向に沿って配列される。リード１６は、リード１８，２０の間に位置する。リード１６，１８、２０及びダイパッド１２は、リードフレームを構成し得る。半導体装置１０は、例えば電源等に使用されるパワー半導体装置である。半導体装置１０のパッケージ形態の例は一般的なＴＯシリーズである。ＴＯシリーズの例はＴＯ－２４７、ＴＯ－２２０、ＴＯ－２６３（Ｄ２―ＰＡＫ）、ＴＯ－２５２（Ｄ－ＰＡＫ）を含む。
　リード１８は、ゲート配線３０ａ～３０ｄに電気的に接続される。リード２０は、第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄに電気的に接続される。リード１６の内側端部は、ダイパッド１２に機械的に一体的に連結されている。ダイパッド１２は導電性を有するので、リード１６とダイパッド１２とは電気的に接続されている。リード１６の材料の例はダイパッド１２の材料と同じ材料を含む。
　半導体チップ１４ａ～１４ｄがＭＯＳ－ＦＥＴを含む場合、リード１６はドレイン電極端子に対応し、リード１８はゲート電極端子に対応し、リード２０はソース電極端子に対応する。半導体チップ１４ａ～１４ｄがＩＧＢＴを含む場合、リード１６はコレクタ電極端子に対応し、リード１８はゲート電極端子に対応し、リード２０はエミッタ電極端子に対応する。リード１８，２０の材料の例は、銅及び銅合金等の金属を含む。
　半導体装置１０は、ゲート配線３０ａ～３０ｄに接続される配線パターン３６と、ダイパッド１２と配線パターン３６との間に配置された絶縁部材３８とを備え得る。配線パターン３６は、配線４０を介してリード１８に接続される。絶縁部材３８は、Ｚ方向においてダイパッド１２と配線パターン３６との間に介在する。絶縁部材３８は、例えば絶縁基板又は絶縁層である。絶縁部材３８の材料の例は、エポキシ樹脂等の樹脂又はセラミックスを含む。ダイパッド１２と絶縁部材３８と配線パターン３６とは互いに接着剤により接続され得る。
　半導体装置１０は、第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄに接続される配線パターン４２と、ダイパッド１２と配線パターン４２との間に配置された絶縁部材４４とを備え得る。配線パターン４２は、複数の配線４６を介してリード２０に接続される。絶縁部材４４は、Ｚ方向においてダイパッド１２と配線パターン４２との間に介在する。絶縁部材４４は、例えば絶縁基板又は絶縁層である。絶縁部材４４の材料の例は、エポキシ樹脂等の樹脂又はセラミックスを含む。ダイパッド１２と絶縁部材４４と配線パターン４２とは互いに接着剤により接続され得る。配線パターン３６及び４２は配線バーとも呼ばれる。配線パターン３６及び４２の材料の例はダイパッド１２の材料と同じ材料を含む。
　ゲート配線３０ａ～３０ｄ、第１の配線３２ａ～３２ｄ、第２の配線３４ａ～３４ｄ、配線４０及び４６は、ワイヤ又はボンディングリボンであってもよい。ゲート配線３０ａ～３０ｄ、第１の配線３２ａ～３２ｄ、第２の配線３４ａ～３４ｄ、配線４０及び４６の材料の例は、アルミニウム、金、銅等の金属を含む。ゲート配線３０ａ～３０ｄ、第１の配線３２ａ～３２ｄ、第２の配線３４ａ～３４ｄ、配線４０及び４６は、例えば超音波又は加圧等を用いたワイヤボンディングにより、配線パターン３６及び４２、半導体チップ１４ａ～１４ｄ、又はリード１８，２０に接続される。
　ダイパッド１２、半導体チップ１４ａ～１４ｄ、リード１８の内側端部及びリード２０の内側端部は、樹脂部２４によって覆われ得る。リード１６，１８，２０の内側端部は、樹脂部２４に挿入される。リード１６，１８，２０のうち樹脂部２４の内側の部分は、いわゆるインナーリード部である。リード１６，１８，２０のうち樹脂部２４の外側の部分は、アウターリード部である。樹脂部２４の外形形状の一例は、略直方体である。樹脂部２４の材料の例は、ポリフェニレンサルファイド樹脂（ＰＰＳ樹脂）、液晶ポリマー等の熱可塑性樹脂を含む。樹脂部２４は、ダイパッド１２及び半導体チップ１４ａ～１４ｄを熱可塑性樹脂でモールドすることによって形成され得る。樹脂部２４には、ダイパッド１２の貫通孔２６の中心軸線を中心軸線とする貫通孔２８が形成されている。貫通孔２８は、貫通孔２６と同様に螺子止めなどの際などに螺子が通される孔である。貫通孔２８の直径は、貫通孔２６の直径より小さい。
　第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄに流れる電流が時間的に変化すると、電磁誘導効果によってゲート配線３０ａ～３０ｄが第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄから相互インダクタンスの影響を受ける。その結果、半導体チップ１４ａ～１４ｄのゲート電圧が時間的に変動する。相互インダクタンスは、ゲート配線３０ａ～３０ｄと第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄとの間の距離と、第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄに対向するゲート配線３０ａ～３０ｄの部分の長さとによって決定される。ゲート配線３０ａ～３０ｄと第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄとの間の距離が短いと、相互インダクタンスは大きくなる。第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄに対向するゲート配線３０ａ～３０ｄの部分の長さが長いと、相互インダクタンスは大きくなる。
　半導体装置１０では、例えばゲート配線３０ｂに最も近い第１の配線３２ｂに対向するゲート配線３０ｂの第１の部分３０ｘの長さｄ１が、第２の配線３４ｂに対向するゲート配線３０ｂの第２の部分３０ｙの長さｄ２よりも短い。そのため、電磁誘導効果によってゲート配線３０ｂが第１の配線３２ｂから受ける相互インダクタンスの影響が比較的小さい。よって、ゲート電圧の時間的な変動が抑制される。
　半導体装置１０では、隣接する半導体チップ１４ａ～１４ｄ間においてＹ方向に沿って延びる軸Ａｘに対して、ゲート配線３０ａ～３０ｄ、第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄが反転して配置され得る。この場合、各半導体チップ１４ａ～１４ｄのゲート配線３０ａ～３０ｄが電磁誘導効果によって第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄから受ける相互インダクタンスの影響が均一化される。よって、隣接する半導体チップ１４ａ～１４ｄ間のゲート電圧のばらつきが低減される。
　半導体チップ１４ａ～１４ｄの材料が、ワイドバンドギャップ半導体を含む場合、シリコンからなる半導体チップ１４ａ～１４ｄに比べて大きな電流を第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄに流すことが可能になる。そのため、ワイドバンドギャップ半導体では、ゲート電圧の時間的な変動が大きくなる傾向にあるので、ゲート電圧の時間的な変動を抑制することによる効果が大きい。
　半導体装置１０がゲート配線３０ａ～３０ｄに接続される配線パターン３６を備える場合、半導体チップ１４ａ～１４ｄと配線パターン３６との間の距離が小さく設定され得る。その結果、ゲート配線３０ａ～３０ｄの長さが短くなり得る。これにより、電磁誘導効果によってゲート配線３０ａ～３０ｄが第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄから受ける相互インダクタンスの影響が更に低減される。よって、ゲート電圧の時間的な変動が更に抑制される。
　半導体装置１０はリード１８及び２０とダイパッド１２とを備え得る。この場合、通常、ゲート配線を第１の配線及び第２の配線から十分に離すことが困難である。そのため、ゲート電圧の時間的な変動が大きくなる傾向にあるので、ゲート電圧の時間的な変動を抑制することによる効果が大きい。
　図２は、第１実施形態に係る半導体装置におけるゲート電圧の時間的な変動の一例を示す図である。図２には、半導体チップ１４ｂのゲート配線３０ｂが第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄから受ける相互インダクタンスの影響の一例が示される。ゲート配線３０ｂの自己インダクタンスによる影響は考慮されていない。
　並列接続された半導体チップ１４ａ～１４ｄに流れる電流値は５０Ａである。よって、半導体チップ１４ａ～１４ｄのそれぞれには、１２．５Ａの電流が流れる。半導体チップ１４ａ～１４ｄの動作時のゲート電圧は１５Ｖである。スイッチング時間は２０ｎｓである。ゲート配線３０ｂの長さは３．２ｍｍである。ゲート配線３０ｂの第１の部分３０ｘの長さｄ１は２．４ｍｍである。ゲート配線３０ｂの第２の部分３０ｙの長さｄ２は３．２ｍｍである。
　ゲート配線３０ｂと第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄとの間の距離は、最短距離が採用される。最短距離は、図１及び図２に示されるように、第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄ上の位置Ｐ１～Ｐ８とゲート配線３０ｂとの間の距離である。例えば、第２の配線３４ａ上の位置Ｐ１とゲート配線３０ｂとの距離は３．７２ｍｍである。この距離及び長さｄ１及びｄ２を用いて、ゲート配線３０ｂが第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄから受ける相互インダクタンスが算出される。相互インダクタンスをＬ、電流をｉ、時間をｔとした場合、ゲート電圧の変動Ｖは以下の式から算出される。
Ｖ＝Ｌ×ｄｉ／ｄｔ
　相互インダクタンス及びゲート電圧の変動の算出結果は図２に示される。例えば、ゲート配線３０ｂが第２の配線３４ａから受ける相互インダクタンスは０．２２ｎＨである。これによるゲート電圧の変動は０．１４Ｖである。ゲート配線３０ｂが第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄから受ける相互インダクタンスの合計は１．８１ｎＨである。ゲート配線３０ｂにおけるゲート電圧の変動の合計は１．１４Ｖ（有効数字２桁では１．１Ｖ）である。同様に、ゲート配線３０ａが第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄから受ける相互インダクタンスが算出される。ゲート配線３０ａが第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄから受ける相互インダクタンスの合計は１．８１ｎＨである。さらに、ゲート配線３０ａにおけるゲート電圧の変動が算出される。ゲート配線３０ａにおけるゲート電圧の変動の合計は１．１Ｖ（有効数字２桁）である。よって、隣接する半導体チップ１４ａ及び１４ｂ間のゲート電圧の変動は同じであるため、隣接する半導体チップ１４ａ及び１４ｂ間のゲート電圧の変動のばらつきがない。
　図３は、参照用の半導体装置を模式的に示す平面図である。図３に示される半導体装置１１０は、半導体チップ１４ａ～１４ｄに代えて半導体チップ１１４ａ～１１４ｄを備え、ゲート配線３０ａ～３０ｄに代えてゲート配線１３０ａ～１３０ｄを備え、第１の配線３２ａ～３２ｄに代えて第１の配線１３２ａ～１３２ｄを備え、第２の配線３４ａ～３４ｄに代えて第２の配線１３４ａ～１３４ｄを備えること以外は半導体装置１０と同様の構成を備える。
　ゲート配線１３０ａ～１３０ｄは、第１の配線１３２ａ～１３２ｄと第２の配線１３４ａ～１３４ｄとの間に配置されている。第１の配線１３２ａ～１３２ｄ及び第２の配線１３４ａ～１３４ｄに対向するゲート配線１３０ａ～１３０ｄの部分の長さはいずれもゲート配線１３０ｂの長さと同じである。
　図４は、参照用の半導体装置におけるゲート電圧の時間的な変動の一例を示す図である。図４には、半導体チップ１１４ｂのゲート配線１３０ｂが第１の配線１３２ａ～１３２ｄ及び第２の配線１３４ａ～１３４ｄから受ける相互インダクタンスの影響の一例が示される。ゲート配線１３０ｂの自己インダクタンスによる影響は考慮されていない。
　並列接続された半導体チップ１１４ａ～１１４ｄに流れる電流値は５０Ａである。よって、半導体チップ１１４ａ～１１４ｄのそれぞれには、１２．５Ａの電流が流れる。半導体チップ１１４ａ～１１４ｄの動作時のゲート電圧は１５Ｖである。スイッチング時間は２０ｎｓである。ゲート配線１３０ｂの長さは３．２ｍｍである。第１の配線１３２ａ～１３２ｄ及び第２の配線１３４ａ～１３４ｄに対向するゲート配線１３０ｂの長さは３．２ｍｍである。
　ゲート配線１３０ｂと第１の配線１３２ａ～１３２ｄ及び第２の配線１３４ａ～１３４ｄとの間の距離は、最短距離が採用される。最短距離は、図３及び図４に示されるように、第１の配線１３２ａ～１３２ｄ及び第２の配線１３４ａ～１３４ｄ上の位置Ｐ１１～Ｐ１８とゲート配線１３０ｂとの間の距離である。例えば、第２の配線１３４ａ上の位置Ｐ１１とゲート配線１３０ｂとの距離は４．５４ｍｍである。この距離及びゲート配線１３０ｂの長さを用いて、ゲート配線１３０ｂが第１の配線１３２ａ～１３２ｄ及び第２の配線１３４ａ～１３４ｄから受ける相互インダクタンスが算出される。相互インダクタンス及びゲート電圧の変動の算出結果は図４に示される。例えば、ゲート配線１３０ｂが第２の配線１３４ａから受ける相互インダクタンスは０．１０ｎＨである。これによるゲート電圧の変動は０．０７Ｖである。ゲート配線１３０ｂが受ける相互インダクタンスの合計は１．９０ｎＨである。ゲート配線１３０ｂにおけるゲート電圧の変動の合計は１．１９Ｖ（有効数字２桁では１．２Ｖ）である。同様に、ゲート配線１３０ａが第１の配線１３２ａ～１３２ｄ及び第２の配線１３４ａ～１３４ｄから受ける相互インダクタンスが算出される。ゲート配線１３０ａが第１の配線１３２ａ～１３２ｄ及び第２の配線１３４ａ～１３４ｄから受ける相互インダクタンスの合計は１．７４ｎＨである。さらに、ゲート配線１３０ａにおけるゲート電圧の変動が算出される。ゲート配線１３０ａにおけるゲート電圧の変動の合計は１．１Ｖ（有効数字２桁）である。よって、隣接する半導体チップ１１４ａ及び１１４ｂ間のゲート電圧の変動は０．１Ｖ異なるため、隣接する半導体チップ１１４ａ及び１１４ｂ間のゲート電圧の変動のばらつきがある。
（第２実施形態）
　図５は、第２実施形態に係る半導体装置を模式的に示す平面図である。図５に示される半導体装置１０ａは、ケース型の半導体装置である。半導体装置１０ａは、半導体チップ１４ａ～１４ｌと、半導体チップ１４ａ～１４ｌにそれぞれ接続されるゲート配線３０ａ～３０ｌと、半導体チップ１４ａ～１４ｌにそれぞれ接続される第１の配線３２ａ～３２ｌと、半導体チップ１４ａ～１４ｌにそれぞれ接続される第２の配線３４ａ～３４ｌと、ケース６０とを備える。半導体チップ１４ｅ，１４ｇ，１４ｉ，１４ｋは、半導体チップ１４ａと同様の構成を備え得る。半導体チップ１４ｆ，１４ｈ，１４ｊ，１４ｌは、半導体チップ１４ｂと同様の構成を備え得る。
　半導体チップ１４ａ～１４ｆは、第１の基板５０ａ上に形成された配線パターン５２ａ上に設けられる。基板５０ａ上には配線パターン５４ａ及び５６ａが形成され得る。配線パターン５４ａは、それぞれゲート配線３０ａ～３０ｆによって半導体チップ１４ａ～１４ｆに接続され得る。配線パターン５６ａは、第１の配線３２ａ～３２ｆ及び第２の配線３４ａ～３４ｆによって半導体チップ１４ａ～１４ｆにそれぞれ接続され得る。
　同様に、半導体チップ１４ｇ～１４ｌは、第２の基板５０ｂ上に形成された配線パターン５２ｂ上に設けられる。基板５０ｂ上には配線パターン５４ｂ及び５６ｂが形成され得る。配線パターン５４ｂは、それぞれゲート配線３０ｇ～３０ｌによって半導体チップ１４ｇ～１４ｌに接続され得る。配線パターン５６ｂは、第１の配線３２ｇ～３２ｌ及び第２の配線３４ｇ～３４ｌによって半導体チップ１４ｇ～１４ｌにそれぞれ接続され得る。
　ケース６０は、基板５０ａ及び５０ｂを載置するための底部６０ａを備え得る。底部６０ａ上には、バスバー７２ａ～７２ｃを載置するための台部６０ｂが配置され得る。バスバー７２ａ～７２ｃは半導体チップ１４ａ～１４ｌに電気的に接続され得る。ケース６０は、基板５０ａ及び５０ｂ及び台部６０ｂを取り囲む第１側壁部６０ｃと、第１側壁部６０ｃを取り囲む第２側壁部６０ｄとを備え得る。ケース６０の開口は、蓋によって封止され得る。ケース６０の材料の例は、ポリブチレンテレフタレート（ＰＢＴ）又はポリフェニレンサルファイド（ＰＰＳ）樹脂といったエンジニヤリングプラスチック等の樹脂を含む。蓋の材料の例は熱可塑性樹脂を含む。ケース６０の内側には、応力緩和のため、例えばシリコーンゲル等のゲルが注入され得る。半導体装置１０ａでは、半導体装置１０と同様の作用効果が得られる。
　図６は、参照用の半導体装置を模式的に示す平面図である。図６に示される半導体装置１１０ａは、半導体チップ１４ａ～１４ｌに代えて半導体チップ１１４ａ～１１４ｌを備え、ゲート配線３０ａ～３０ｌに代えてゲート配線１３０ａ～１３０ｌを備え、第１の配線３２ａ～３２ｌに代えて第１の配線１３２ａ～１３２ｌを備え、第２の配線３４ａ～３４ｌに代えて第２の配線１３４ａ～１３４ｌを備えること以外は半導体装置１０ａと同様の構成を備える。
　ゲート配線１３０ａ～１３０ｌは、第１の配線１３２ａ～１３２ｌと第２の配線１３４ａ～１３４ｌとの間に配置されている。第１の配線１３２ａ～１３２ｌ及び第２の配線１３４ａ～１３４ｌに対向するゲート配線１３０ａ～１３０ｌの部分の長さはいずれもゲート配線１３０ｂの長さと同じである。
　以上、本発明の好適な実施形態について詳細に説明されたが、本発明は上記実施形態に限定されない。
　例えば、半導体装置１０，１０ａは、１つの半導体チップのみを含んでもよい。半導体装置１０，１０ａは、半導体チップに接続される第３の配線を備えてもよい。
　半導体チップ１４ａ～１４ｌは、縦型トランジスタに代えて横型トランジスタを含んでもよい。この場合、半導体チップ１４ａ～１４ｌの裏面には電極パッドが形成されず、半導体チップ１４ａ～１４ｌの表面に例えばドレイン電極パッド又はコレクタ電極パッド等の更なる電極パッドが形成される。
　半導体装置１０は、配線パターン３６及び４２を備えなくてもよい。この場合、ゲート配線３０ａ～３０ｄはリード１８に接続される。第１の配線３２ａ～３２ｄ及び第２の配線３４ａ～３４ｄはリード２０に接続される。
　１０，１０ａ…半導体装置、１４ａ～１４ｌ…半導体チップ、１２…ダイパッド、１２ａ…チップ搭載面、１８…第１のリード、２０…第２のリード、３０ａ～３０ｌ…ゲート配線、３０ｘ…ゲート配線の第１の部分、３０ｙ…ゲート配線の第２の部分、３２ａ～３２ｌ…第１の配線、３４ａ～３４ｌ…第２の配線、３６…配線パターン、Ａｘ…軸。

Claims (5)

  1. 　少なくとも１つの半導体チップと、
    　前記少なくとも１つの半導体チップに接続されるゲート配線と、
    　前記少なくとも１つの半導体チップに接続される第１の配線と、
    　前記少なくとも１つの半導体チップに接続される第２の配線と、
    を備え、
    　前記第１の配線及び前記第２の配線が、前記ゲート配線に沿って延びており、
    　前記第１の配線が前記ゲート配線と前記第２の配線との間に配置され、
    　前記第１の配線が前記ゲート配線に最も近い配線であり、
    　前記第１の配線に対向する前記ゲート配線の第１の部分の長さが、前記第２の配線に対向する前記ゲート配線の第２の部分の長さよりも短い、半導体装置。
  2. 　前記少なくとも１つの半導体チップが複数の半導体チップであり、
    　前記複数の半導体チップが第１の方向に沿って配列されており、
    　隣接する半導体チップ間において前記第１の方向に垂直な第２の方向に沿って延びる軸に対して、前記ゲート配線、前記第１の配線及び前記第２の配線が反転して配置される、請求項１に記載の半導体装置。
  3. 　前記少なくとも１つの半導体チップの材料が、ワイドバンドギャップ半導体を含む、請求項１又は２に記載の半導体装置。
  4. 　前記ゲート配線に接続される配線パターンを更に備える、請求項１～３のいずれか一項に記載の半導体装置。
  5. 　前記ゲート配線に電気的に接続される第１のリードと、
    　前記第１の配線及び前記第２の配線に電気的に接続される第２のリードと、
    　前記少なくとも１つの半導体チップが搭載されるチップ搭載面を有するダイパッドと、
    を更に備える、請求項１～４のいずれか一項に記載の半導体装置。
PCT/JP2013/063444 2012-06-28 2013-05-14 半導体装置 WO2014002625A1 (ja)

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JP2014011227A (ja) 2014-01-20
EP2869340A1 (en) 2015-05-06
CN104321867A (zh) 2015-01-28
US20140001481A1 (en) 2014-01-02
EP2869340A4 (en) 2015-08-19
JP5991045B2 (ja) 2016-09-14
CN104321867B (zh) 2017-05-10
US9087817B2 (en) 2015-07-21

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