CN104282626A - 制造具有器件分离结构的半导体器件的方法及半导体器件 - Google Patents
制造具有器件分离结构的半导体器件的方法及半导体器件 Download PDFInfo
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Abstract
公开了制造具有器件分离结构的半导体器件的方法及半导体器件。一种制造半导体器件的方法,包括:至少将包括阵列沟槽的第一沟槽图案和第二沟槽图案从第一表面引入到半导体衬底中,其中,所述半导体衬底的阵列隔离部分分离所述第一沟槽图案和第二沟槽图案。在距所述第一表面的一定距离处的所述第一沟槽图案和第二沟槽图案中提供掩埋栅极电极结构。在单个蚀刻处理中,将具有第一宽度的器件分离沟槽引入到所述阵列隔离部分中,并且将至多具有比所述第一宽度更小的第二宽度的单元分离沟槽引入到所述各阵列沟槽之间的半导体翅片中。可以在通过成本有效的方式形成同一半导体管芯中所集成的开关器件。
Description
技术领域
本发明涉及一种制造具有器件分离结构的半导体器件的方法以及半导体器件。
背景技术
功率半导体器件(比如MOSFET(金属氧化物半导体场效应晶体管))在阻断模式下维持高击穿电压,而在导电模式下具有低的开态电阻。功率半导体器件因此通常包括在电压受控主体区域与漏极区域之间的漂移区域。增加漂移区带的长度增加了电压阻断能力,但是同时增加了开态电阻。功率半导体器件可以集成实现晶体管功能并且在同一半导体管芯中被以串行、并行或其它配置布置以实现特定功能和/或获得特定器件特性的两个或更多个功能块。各功能块之间的结构维持各功能块之间的电势差。期望提供可靠的半导体器件和提供简单并且成本有效的制造处理的方法。
发明内容
根据实施例,一种制造半导体器件的方法,包括:至少将包括阵列沟槽的第一沟槽图案和第二沟槽图案从第一表面引入到半导体衬底中,其中,所述半导体衬底的阵列隔离部分分离所述第一沟槽图案和第二沟槽图案。在距所述第一表面的一定距离处的所述第一沟槽图案和第二沟槽图案中提供掩埋栅极电极结构。在单个蚀刻处理中,将具有第一宽度的器件分离沟槽引入到所述阵列隔离部分中,并且还将至多具有比所述第一宽度更小的第二宽度的单元分离沟槽引入到所述各阵列沟槽之间的半导体翅片中。
另一实施例涉及一种半导体器件。包括平行阵列条带的第一栅极电极结构被掩埋在第一单元阵列中的半导体部分中、在距所述半导体部分的第一表面的一定距离处。包括平行阵列条带的第二栅极电极结构被掩埋在与所述第一单元阵列接近的第二单元阵列中的所述半导体部分中。在所述第一单元阵列与第二单元阵列之间的器件分离结构具有第一宽度。在所述第一表面处,对从所述各阵列沟槽之间的半导体部分的区段所形成的半导体翅片进行切口的单元分离结构至多具有比所述第一宽度更小的第二宽度。
在阅读以下详细描述并且查看随附的附图时,本领域技术人员将认识到附加的特征和优点。
附图说明
随附的附图被包括以提供本公开的进一步理解,并且附图被并入在本说明书中并构成本说明书的一部分。附图示出本公开的实施例,并且连同描述一起用来说明本公开的原理。由于通过参照以下详细描述其它实施例以及意图的优点变得更好理解,因此它们将容易被领会。
图1A是半导体衬底的部分的示意性透视图,用于示出在将沟槽图案引入到半导体衬底中之后制造根据实施例的半导体器件的方法。
图1B是于在沟槽图案中提供掩埋栅极电极结构和填充结构之后,图1A的半导体衬底部分的示意性透视图。
图1C是在引入器件分离沟槽和单元分离沟槽之后,图1B的半导体衬底部分的示意性透视图。
图1D是在提供填充单元分离沟槽的绝缘体层之后,图1C的半导体衬底部分的示意性透视图。
图1E是在提供器件分离沟槽的延伸部分之后,图1D的半导体衬底部分的示意性透视图。
图2A是集成增强型IFGET(绝缘栅极场效应晶体管)和耗尽型IGFET的根据实施例的半导体器件的示意电路图。
图2B是图2A的半导体器件的部分的示意性平面图。
图2C是包括深器件分离结构的根据实施例的沿着线X-Y-Z的图2B的半导体器件部分的示意性截面图。
图3是包括瓶状器件分离结构的根据实施例的半导体器件的部分的示意性截面图。
图4A是ADZFET(有源漂移区带场效应晶体管)的电路图。
图4B是根据本发明进一步实施例的图4A的ADZFET的布线平面的示意性平面图。
具体实施方式
在以下详细描述中,参照形成在此的一部分的随附的附图,并且在附图中以图示的方式示出其中可以实践本公开的具体实施例。应理解可以利用其它实施例,并且可以在不脱离本发明的范围的情况下作出结构或逻辑改变。例如,针对一个实施例示出或描述的特征可以用于其它实施例或与其它实施例结合,以得到另一实施例。意图由本公开包括这样的修改和变形。使用具体的语言来描述示例,示例不应被解释为限制所附权利要求的范围。附图并非成比例并且仅用于例示的目的。为了清楚,如果没有另外声明,则在不同附图中通过对应的参考标号来指定相同或相似要素。
术语“具有”、“包含”、“包括”、“含有”等是开放式的,并且这些术语指示所声明的结构、要素或特征的存在,而非排除附加要素或特征的存在。数量词和代词“一个”、“某个”以及“这个”意图包括复数以及单数,除非上下文另外清楚地指示。
术语“电连接”描述电连接的元件之间的恒定低欧姆连接,例如所关注的各元件之间的直接接触或经由金属和/或高掺杂半导体的低欧姆连接。术语“电耦接”包括可以在电耦接的各元件(例如暂时在第一状态下提供低欧姆连接而在第二状态下提供高欧姆电退耦的元件)之间存在适用于信号传输的一个或多个中间元件。
所述图通过在掺杂类型“n”或“p”旁指示 “+”或“-”来示出相对掺杂浓度。例如,“n-”表示比“n”掺杂区域的掺杂浓度更低的掺杂浓度,而“n+”掺杂区域具有比“n”掺杂区域更高的掺杂浓度。相同的相对掺杂浓度的掺杂区域不一定具有相同的绝对掺杂浓度。例如,两个不同的“n”掺杂区域可以具有相同或不同的绝对掺杂浓度。
图1A至图1E所示出的方法提供一种构成自或包含单晶半导体材料的半导体层100a的半导体衬底500a。通过示例的方式,单晶半导体材料可以是硅Si、碳化硅SiC、锗Ge、硅锗晶体SiGe、氮化镓GaN或砷化镓GaAs。例如,半导体衬底500a可以是硅晶片。可以从半导体衬底500a获得多个完全相同的半导体管芯。除了半导体层100a之外,半导体衬底500a可以进一步包括另外的半导体和介电层。
半导体层100a具有平坦的第一表面101以及与第一表面101平行的平坦的第二表面102。第一表面101和第二表面102的法线限定垂直方向,以及与垂直方向正交的方向是横向方向。
至少将第一沟槽图案410和第二沟槽图案420从第一表面101引入到半导体层100a中。可以例如与第一沟槽图案410和第二沟槽图案420同时地在半导体衬底500a的其它部分中形成另外的沟槽图案。半导体层100a的阵列隔离部分490将第一沟槽图案410和第二沟槽图案420彼此在空间上分离。另外的阵列隔离部分490可以将第一沟槽图案410和/或第二沟槽图案420与一个或多个另外的沟槽图案和/或一些或所有另外的沟槽图案彼此在空间上分离。每一个沟槽图案410、420以及另外的沟槽图案可以在横向方向上完全由阵列隔离部分490包围,其中,每个阵列隔离部分490包围一个单个的沟槽图案。
第一沟槽图案410和第二沟槽图案420包括阵列沟槽411,其中,邻近成对的阵列沟槽411之间的半导体层100a的部分形成半导体翅片418。沟槽图案410、420中的每一个可以还包括与相应的沟槽图案410的阵列沟槽411在结构上连接的一个或多个接触沟槽413、连接阵列沟槽411的一个或多个辅助沟槽414以及将接触沟槽413与所关注的沟槽图案410、420的辅助沟槽414或阵列沟槽411连接的一个或多个间隔壁沟槽412。
例如,掩模层可以沉积在第一表面101上,并且通过光刻技术被图案化,以生成具有暴露出与第一沟槽图案410和第二沟槽图案420的沟槽对应的第一表面101的部分的掩模开口的蚀刻掩模。主要各向异性蚀刻(predominantly anisotropic etch)去除在掩模开口的垂直投影中的半导体层100a的半导体材料。
图1A示出第一沟槽图案410和第二沟槽图案420以及将第一沟槽图案410和第二沟槽图案420彼此分离的阵列隔离部分490。阵列沟槽411可以是规律地间隔开的平行条带。阵列沟槽411可以具有相等的宽度,并且可以相等地以20nm至500nm之间(例如150nm至250nm之间)的中心到中心距离(间距)而间隔开。例如,宽度d1可以是宽度d2的至少两倍。沟槽图案410、420中的每一个可以限定一个或多个半导体翅片418(例如一千个或更多个半导体翅片418)。
第一沟槽图案410的阵列沟槽411被分配给第一开关器件,并且形成于第一单元区441内。第二沟槽图案420的阵列沟槽411被分配给第二开关器件,并且形成于第二单元区442内。另外的沟槽图案的阵列沟槽可以被分配给另外的开关器件。一个、两个或更多个在与阵列沟槽411相交的方向上延伸的辅助沟槽414可以将同一沟槽图案410、420的阵列沟槽411彼此连接。
在单元区441、442外部的接触区449中形成接触沟槽413。接触沟槽413可以与阵列沟槽411垂直或平行而行进,并且可以直接邻接或可以不直接邻接相应的单元区441、442。根据所示出的实施例,第一沟槽图案410的接触沟槽413与第一单元区441间隔开,并且一个、两个或更多个间隔壁沟槽412在结构上将接触沟槽413与阵列沟槽411和/或第一沟槽图案410的一个或更多个辅助沟槽414连接。接触沟槽413的宽度可以等于或大于最宽阵列沟槽411的宽度d1。
沿着可以与由阵列沟槽411的纵轴所限定的第二横向方向的正交的第一横向方向来布置第一沟槽图案410和第二沟槽图案420。可以沿着第一横向方向在第一沟槽图案410的投影中布置第二沟槽图案420。例如,可以沿着同一横向轴布置单元区441、442。可以沿着同一横向轴形成另外的沟槽图案,其在结构上与第一沟槽图案410和第二沟槽图案420不相连。
可以在半导体层100a的暴露半导体材料上形成栅极介电层205。栅极介电层205的形成可以包括:半导体层100a的半导体材料的热氧化,或介电材料(例如氧化硅)的沉积,或二者。根据实施例,提供栅极介电层205包括:半导体层100a的半导体材料的热氧化,使用例如TEOS(正硅酸乙酯)作为前体材料来沉积氧化硅,以及另外的热处理。形成栅极介电层205可以包括:氮化硅或氮氧化硅的形成,和/或其它介电材料的沉积。
导电栅极材料沉积在栅极介电层205上,并且填充第一沟槽图案410和第二沟槽图案420。导电栅极材料可以是重掺杂多晶硅。根据其它实施例,沉积多于一个的栅极材料以形成层状结构,其可以包括一个或多个含有金属的层。使栅极材料凹陷以在每个沟槽图案410、420中形成距第一表面101一定距离、被完全掩埋在第一表面101和第二表面102之间的相邻栅极电极结构150,由此,单元区441、442中的栅极电极结构150通过在第一表面101处发生的凹陷和/或抛光处理而被分离。
沉积填充材料(例如半导体氧化物)。根据实施例,填充材料是例如使用TEOS作为前体材料所获得的氧化硅。填充材料可以是一种单一材料,或可以包括两种或更多种不同材料的子层。根据实施例,填充材料是例如来自氧化硅的同质介电层。
各向异性蚀刻可以去除沟槽图案410、420外部的填充材料209a和栅极介电层205二者的水平多余部分,以及薄牺牲氧化物层可以形成在半导体翅片418的暴露表面上。根据其它实施例,可以保持沟槽图案外部的填充材料209a的水平多余部分,以用于以下处理。
图1B示出衬连沟槽图案410、420的共形栅极介电层205以及在沟槽图案410、420的下区段中形成相邻栅极电极结构150的凹陷栅极材料。栅极电极结构150可以与第一表面101间隔开多于0nm,例如间隔开至少500nm并且至多1.5µm。填充材料在栅极电极结构150与第一表面101之间形成填充结构209。
参照图1C,在单个共享蚀刻处理中,具有第一宽度w1的器件分离沟槽191被引入到阵列隔离部分490中,并且至多具有比第一宽度w1更小的第二宽度w2的单元分离沟槽170被引入,以沿着第一表面101至少对半导体翅片418进行切口。
例如,平版印刷处理提供分离蚀刻掩模,其具有:第一开口,沿着第一横向方向延伸,并且在单元区441、442内穿过半导体翅片418;以及第二开口,在分配给不同开关器件的单元区441、442之间沿着第二横向方向延伸。
主要各向异性蚀刻处理去除分离蚀刻掩模中的第一开口和第二开口的垂直投影中的材料,以在第一开口的垂直投影中形成单元分离沟槽170,并且在第二开口的垂直投影中形成器件分离沟槽191。各向异性蚀刻可以是或可以不是材料选择性的。例如,蚀刻处理可以在半导体翅片418的材料与填充结构209的填充材料之间具有高蚀刻选择性,从而在填充结构209保持基本上不受影响的同时,仅使半导体翅片418被凹陷。所得单元分离沟槽170是在相应单元区441、442内按矩阵所布置的孔沟槽。根据另一实施例,蚀刻处理没有蚀刻选择性,从而单元分离沟槽170是沿着第一方向延伸并且对半导体翅片418和填充结构209二者进行切口的条带。
图1C示出沿着与切口的半导体翅片180的定向正交的第一横向方向延伸的条带形单元分离沟槽170。单元分离沟槽170比阵列沟槽411更浅,并且可以比填充结构209更深地延伸到半导体层100a中。器件分离沟槽191在单元区441、442之间沿着第二横向方向行进。器件分离沟槽191可以比单元分离沟槽170更深。例如,器件分离沟槽191可以比沟槽图案410、420更深。
可以以主要共形方式来沉积绝缘体层192,其中,绝缘体层192的厚度至少是单元分离沟槽170的宽度w2的一半,并且至多是器件分离沟槽191的宽度w1的一半。绝缘体层192可以是同质层,或可以包括两个或更多个子层。绝缘体层192针对半导体部分100的半导体材料是选择性可蚀刻的,并且可以是非导电材料(例如本征多晶硅或介电材料)。可以稍后在处理中从器件分离沟槽191去除绝缘体层192,或绝缘体层192的至少一部分可以在最终器件的器件分离结构中形成残余层。
根据实施例,绝缘体层192包括氧化硅层、氮化硅层和/或氮氧化硅层。可以控制用于沉积绝缘体层192的处理,从而在器件分离沟槽191的底部比在第一表面101上沉积更少的材料。
图1D示出衬连器件分离沟槽191的绝缘体层192,其在至少切口的半导体翅片180的上区段中形成单元分离结构175并且覆盖第一表面101。单元分离结构175可以通过切口的填充结构209和切口的半导体翅片180的切口形成条带。根据其它实施例,单元分离沟槽175专门对切口的半导体翅片180进行切口,并且对于每个单元区441、442形成介电插塞的矩阵。器件分离沟槽191外部的绝缘体层192的部分可以比覆盖器件分离沟槽191的底部部分的绝缘体层192的部分更厚。
可以执行蚀刻处理,其可以薄化第一表面101上的绝缘体层192的厚部分,并且其完全去除在器件分离沟槽191的底部的绝缘体层192的薄部分。
使用所得的被图案化的绝缘体层192c作为蚀刻掩模,可以通过形成蚀刻到半导体层100a中的延伸部分191z来加深器件分离沟槽191。延伸蚀刻可以具有各向异性成分,从而延伸部分191z可以具有比被图案化的绝缘体层192c的开口更宽的横截面区。可以提供钝化层195,例如通过热氧化所暴露的半导体材料,来覆盖由延伸蚀刻所暴露半导体材料。通过示例的方式,可以利用介电材料或本征半导体材料来完全地或部分地填充器件分离沟槽191。根据另一实施例,通过形成封闭器件分离沟槽191的开口的介电插塞而在器件分离沟槽191中提供器件分离空区。
图1E示出薄化的、被图案化的绝缘体层192c,其仍然覆盖第一表面101和在器件分离沟槽191的第一区段的底部的绝缘体层192c中的开口。器件分离结构190包括由被图案化的绝缘体层192c所衬连的第一区段和由钝化层195所衬连的延伸部分191z。延伸部分191z可以到达或可以不到达衬底层,并且可以具有比被图案化的绝缘体层192c的开口更宽的横截面区。器件分离结构190可以包括由介电插塞所封闭的器件分离空区。根据其它实施例,器件分离结构190包括介电材料或本征半导体材料的填充部分。填充部分可以部分地或完全地填充被图案化的绝缘体层192c和钝化层195内的空间。
在常规方法依赖于用于限定半导体翅片、单元分离结构和器件隔离结构的三个关键光掩模的情况下,该实施例仅通过两个光掩模而得到。此外,为了分离分配给不同单元区441、442的栅极电极结构150,常规方法使用在沟槽中暴露栅极材料的蚀刻掩模,并且器件分离蚀刻沿着半导体层100a的垂直侧壁去除材料,具有的风险是:在器件分离沟槽的侧壁处的栅极材料的残余物在结构上连接邻近单元区441、442的所关注的栅极电极结构150,并且将其短路。与之对照,上面描述的处理在阵列隔离部分490上以及沟槽外部固有地分离分配给不同单元区441、442的栅极电极结构150。因此,该方法以更少的付出来提供更可靠地分离的栅极电极结构。
实施例包括相同类型或不同类型的两个或更多个晶体管器件的组合,包括例如增强型和耗尽型的p沟道FET以及增强型和耗尽型的n沟道FET。如图2A所示,根据实施例的功率半导体器件500b可以包括至少两个半导体开关器件,例如可以通过共源共栅连接而布置的增强型IGFET
TB和耗尽型IGFET TA。IGFET
TA的源极s与IGFET
TB的漏极d之间的负载路径串行布置在功率半导体器件500b的漏极端子D与源极端子S之间,提供IGFET功能。半导体器件500b的栅极端子G或集成栅极驱动器的输出电连接或耦接到增强型IGFET
TB的栅极电极g。增强型IGFET
TB的源极s可以电连接或耦接到耗尽型IGFET
TA的栅极电极g。增强型IGFET
TB的漏极d与增强型IGFET
TA的源极s电连接。IGFET
TA、TB可以是n沟道IGFET,如以下进一步描述的那样。等同的考虑应用于p沟道IGFET。
在阻断模式下,IGFET TA、TB中的每一个维持总阻断电压的一部分。在导电模式下,其负载路径被串行地电布置的两个IGFET TA、TB可以提供下述的开态电阻,该开态电阻比具有可比较的阻断电压能力的单个IGFET器件的开态电阻更低,或至少在具有可比较的阻断电压能力的单个IGFET器件的开态电阻的范围中。由于可以通过被串行地电布置并且在横向方向上在同一半导体管芯中所集成的晶体管的数量来修改总阻断电压,因此能够在不通过昂贵的研磨和抛光处理来修改半导体衬底100的厚度的情况下修改设备参数(比如用于IGFET设计的阻断电压能力和开态电阻)。
图2B和图2C示出基于单晶半导体材料的具有半导体部分100的半导体器件500b。半导体部分100具有第一表面101以及与第一表面平行的第二表面102。在半导体部分100中,第一单元阵列451包括分配给第一开关器件的晶体管单元TC(通过示例的方式,其可以是图2A的增强型IGFET TB),以及第二单元阵列452包括分配给第二开关器件的晶体管单元TC(通过示例的方式,其可以是图2A的耗尽型IGFET TA)。
单元阵列451、452包括具有定向到第一表面101的晶体管单元TC的源极区域s1、s2和漏极区域d1、d2的切口的半导体翅片180。
可以沿着第一横向轴来布置第一单元阵列451和第二单元阵列452。在每个单元阵列451、452内,晶体管单元TC被布置成矩阵,其中,沿着第一横向方向布置接近晶体管单元TC的子集的源极区域s1、s2,以及关于相应的晶体管单元TC的源极区域s1、s2沿着与第一横向方向正交的第二横向方向布置漏极区域d1、d2。第一单元阵列451的源极区域s1可以处于沿着第一横向方向的第二单元阵列452的漏极区域d2的投影中,以及第二单元阵列452的源极区域s2可以处于沿着第一横向方向的第一单元阵列451的漏极区域d1的投影中。
在每一个单元阵列451、452中,相应的栅极电极结构150的阵列条带151形成有源栅极电极。阵列条带151在包括晶体管单元TC的有源晶体管区的邻近的被切口的半导体翅片180之间沿着第二横向方向行进。栅极介电层205将栅极电极结构150与半导体部分100的周围半导体材料介质绝缘。
对半导体翅片180进行切口的分离结构175分离分配给同一对阵列条带151之间的同一半导体翅片180的源极和漏极区域s1、d1或s2、d2。
第一布线连接WC1沿着第一横向方向延伸,并且可以将在第一单元阵列451中沿着第一横向方向所布置的第一源极区域s1彼此电连接,并且与源极连接器电连接。第二布线连接WC2可以将沿着第一横向方向所布置的第一单元阵列451中的第一漏极区域d1彼此电连接,并且与第二单元阵列452中的第二源极区域s2电连接。第三布线连接WC3可以将第二单元阵列452中沿着第一横向方向所布置的第二漏极区域d2彼此电连接,并且例如与分配给同一半导体管芯中所集成的另外的开关器件的另外的单元阵列的漏极连接器或源极区域电连接。源极连接器SC可以连接到半导体器件500的源极端子S,以及漏极连接器可以连接到半导体器件500的漏极端子D。
在单元阵列451、452外部,栅极电极结构150可以包括结构上与阵列条带151连接的接触条带,其中,一个、两个或更多个间隔壁条带可以在结构上将阵列条带与接触条带153连接。
填充结构209在空间上将栅极电极结构150与第一表面101分离。漏极区域d1、d2是重掺杂漏极区带120,直接邻接切口的半导体翅片180的第一区段中的第一表面101。源极区域s1、s2是切口的半导体翅片180的第二区段中的重掺杂源极区带110,并且从第一表面101向上延伸距第一表面101的一定距离,其近似与栅极电极结构150与第一表面101之间的距离对应。每个源极区带110可以是杂质区带,或可以包括直接邻接第一表面101的重掺杂多晶第一区段以及直接邻接第一区段的单晶第二区段。
半导体部分100可以进一步包括沿着第二表面102的衬底层140。衬底金属化320可以直接邻接或可以不直接邻接第二表面102。衬底层140可以具有与源极区带110和漏极区带120的杂质类型相反的杂质类型。在一侧上的源极区带110和漏极区带120与在另一侧上的衬底层140之间,半导体部分100可以包括直接邻接源极区带110和漏极区带120的沟道/主体层115。对于增强型的晶体管,沟道/主体层115包括源极区带110和漏极区带120的相反导电类型的主体部分,其中,主体部分连接相应的晶体管单元TC的源极区带110和漏极区带120。对于耗尽型晶体管,沟道/主体层115包括具有与源极区带110和漏极区带120同一导电类型的沟道部分。沟道/主体层115可以进一步包括杂质区带和层,例如形成用于器件分离的pn结。
对于耗尽型晶体管,在栅极电极结构150处所施加的合适的电压充分耗尽源极区带110与漏极区带120之间的沟道部分,从而晶体管单元TC处于关闭状态下。否则,电流在每个晶体管单元TC的源极区带110与漏极区带120之间流动。对于增强型晶体管,如果在栅极电极结构150处所施加的电势足够高,则可以在主体部分中形成少数电荷载流子的导电沟道。
第一布线连接WC1、第二布线连接WC2和第三布线连接WC3可以直接邻接第一表面101或由第一表面101所跨越的平面。其它实施例可以提供布线连接WC1、WC2、WC3与第一表面之间的介电层220,其中,通过介电层220中的开口延伸的接触结构将第一布线连接WC1、第二布线连接WC2和第三布线连接WC3与源极区带110和漏极区带120电连接。
在第一单元阵列451和第二单元阵列452与另外的单元阵列之间,器件分离结构190或器件分离结构190的部分沿着第二横向方向延伸。根据实施例,至少一个器件分离结构190在横向方向上完全包围单元阵列451、452之一。例如,另一器件分离结构190完全包围每一个单元阵列451、452,其中,邻近单元阵列的器件分离结构190可以共享公共部分。根据实施例,多个单元阵列的器件分离结构190形成具有在各阶梯(rung)之间所形成的单元阵列的类似梯子的结构。
被图案化的绝缘体层192c可以衬连定向到第一表面101的器件分离结构190的第一区段。钝化层195可以衬连定向到第二表面102的延伸部分191z。延伸部分191z可以到达或可以不到达衬底层140。第一表面101与器件分离结构的掩埋边沿之间的距离可以是至少3µm,例如10µm或更大。器件分离结构190可以包含沿着第一表面101由介电插塞199所封闭的器件分离空区198。根据其它实施例,器件分离结构190可以包括介电材料和/或本征半导体材料的填充部分。填充部分可以部分地或完全地填充被图案化的绝缘体层192c和钝化层195所包封的空间。
器件分离结构190维持邻近单元阵列451、452的各结构之间以及单元阵列451、452的结构与半导体器件500中的另外的结构之间的电势差,其中,提供器件分离结构190在没有附加平版印刷掩模的情况下得到。
图3示出具有瓶状器件分离结构190的半导体器件500c,其中,延伸部分191z具有比被图案化的绝缘体层192c的开口更宽的横截面区。可以在第一表面101与布线连接WC之间提供介电层220,其中,延伸通过介电层220中的开口的接触结构305将布线连接WC与源极区带110和漏极区带120电连接。
图4A示出包括基于在共源共栅配置中电布置的多个开关器件的ADZFET的半导体器件500d。根据所示实施例,半导体器件500d包括增强型IGFET E和多个耗尽型IGFET D1、D2、Dn。
图4B示出在上面描述图案之后,图4A的半导体器件500d的布线连接的平面图。IGFET E、D1、D2、Dn中的每一个可以在横向方向上完全由器件分离结构190包围。栅极连接GC可以将增强型IGFET的栅极电极结构150的电耦接与内部栅极驱动器电路的输出端子或栅极端子电连接,或可以是增强型IGFET的栅极电极结构150的电耦接的一部分。上面描述的器件分离结构190维持邻近开关器件中的各结构之间的相应的电压差。
尽管已经在此示出并且描述了具体实施例,但本领域技术人员应领会,可以在不脱离本发明的范围的情况下由各种替换和/或等同的实现来代替所示出并且描述的具体实施例。本申请意图覆盖在此所讨论的具体实施例的任何适配和变形。因此,仅意图仅由权利要求及其等同物来限制本发明。
Claims (19)
1.一种制造半导体器件的方法,所述方法包括:
至少将第一沟槽图案和第二沟槽图案从第一表面引入到半导体衬底中,其中,所述沟槽图案包括阵列沟槽,并且其中,所述半导体衬底的阵列隔离部分分离所述第一沟槽图案和第二沟槽图案;
在所述第一沟槽图案和第二沟槽图案中提供掩埋栅极电极结构;以及
在单个蚀刻处理中,将具有第一宽度的器件分离沟槽引入到所述阵列隔离区域中,并且将至多具有比所述第一宽度更小的第二宽度的单元分离沟槽引入到各阵列沟槽之间的半导体翅片中。
2.如权利要求1所述的方法,还包括:
提供填充所述单元分离沟槽的绝缘体层,
衬连所述器件分离沟槽的侧壁,以及
暴露所述器件分离沟槽的底部部分。
3.如权利要求1所述的方法,还包括:沉积绝缘体层,其中,控制所述沉积,以填充所述单元分离沟槽,以至少衬连直接邻接所述第一表面的所述器件分离沟槽的侧壁的区段,以及使所述器件分离沟槽的底部部分暴露。
4.如权利要求1所述的方法,还包括:
沉积绝缘体层,其中,控制所述沉积,以填充所述单元分离沟槽并且衬连所述器件分离沟槽,其中,在所述器件分离沟槽的底部处所沉积的所述绝缘体层的部分比在所述第一表面上所沉积的所述绝缘体层的部分更薄;以及
使所述绝缘体层凹陷,其中,暴露所述器件分离沟槽的底部,并且所述绝缘体层的薄化部分覆盖所述第一表面。
5.如权利要求2所述的方法,还包括:通过提供延伸部分来加深所述器件分离沟槽,其中,所述绝缘体层用作蚀刻掩模。
6.如权利要求5所述的方法,还包括瓶蚀刻以加宽所述延伸部分。
7.如权利要求1所述的方法,其中,所述器件分离沟槽提供得比所述第一沟槽图案和第二沟槽图案更深。
8.如权利要求1所述的方法,其中,所述单元分离沟槽提供得比所述第一沟槽图案和第二沟槽图案更浅。
9.如权利要求1所述的方法,还包括:
在引入所述单元分离沟槽和器件分离沟槽之前,在所述第一表面与所述栅极电极结构之间的所述沟槽图案中提供介电填充结构,其中,
引入所述单元分离沟槽包括:将所述半导体翅片的材料选择性地去除到所述介电填充结构的材料。
10.如权利要求1所述的方法,还包括:
在引入所述单元分离沟槽和器件分离沟槽之前,在所述第一表面与所述栅极电极结构之间的所述沟槽图案中提供介电填充结构,其中,
引入所述单元分离沟槽包括:去除所述半导体翅片的材料和所述介电填充结构的材料。
11.一种半导体器件,包括:
第一栅极电极结构,掩埋在距半导体部分的第一表面一定距离处的第一单元阵列中的半导体部分中,所述第一栅极电极结构包括平行阵列条带;
第二栅极电极结构,掩埋在与所述第一单元阵列邻近的第二单元阵列中的半导体部分中,所述第二栅极电极结构包括平行阵列条带;
器件分离结构,在所述第一单元阵列与第二单元阵列之间,所述器件分离结构具有第一宽度;以及
单元分离结构,至多具有比所述第一宽度更小的第二宽度,并且在所述第一表面处,对由各阵列沟槽之间的半导体部分的区段所形成的半导体翅片进行切口。
12.如权利要求11所述的半导体器件,其中,所述器件分离结构包括:第一区段,定向到所述第一表面;以及延伸区段,定向到与所述第一表面平行的半导体部分的第二表面,所述延伸区段具有比所述延伸区段更小的与所述第一表面平行的横截面区。
13.如权利要求11所述的半导体器件,其中,所述器件分离结构包括:第一区段,定向到所述第一表面;以及延伸区段,定向到与所述第一表面平行的半导体部分的第二表面,所述延伸区段具有比所述延伸区段更大的与所述第一表面平行的横截面区。
14.如权利要求11所述的半导体器件,其中:
所述器件分离结构包括:绝缘体层,在定向到所述第一表面的第一区段中,所述绝缘体层平行于与半导体部分的半导体材料的垂直界面而延伸,以及其中,
由相同的材料制成所述绝缘体层和所述单元分离结构。
15.如权利要求11所述的半导体器件,其中,所述器件分离结构包括空区。
16.如权利要求11所述的半导体器件,其中,所述器件分离结构的掩埋边沿与所述栅极电极结构的掩埋边沿相比具有更大的距所述第一表面的距离。
17.如权利要求11所述的半导体器件,其中,由半导体部分的各部分所形成的脊将所述器件分离结构与所述第一单元阵列和第二单元阵列分离。
18.如权利要求11所述的半导体器件,其中,所述器件分离结构在与所述第一表面平行的横向方向上完全包围所述第一单元阵列。
19.一种有源漂移区带场效应晶体管(ADZFET),包括:
第一栅极电极结构,掩埋在距半导体部分的第一表面一定距离处的第一单元阵列中的半导体部分中,所述第一栅极电极结构包括平行阵列条带;
第二栅极电极结构,掩埋在与所述第一单元阵列邻近的第二单元阵列中的半导体部分中,所述第二栅极电极结构包括平行阵列条带;
器件分离结构,在所述第一单元阵列与第二单元阵列之间,所述器件分离结构具有第一宽度;以及
单元分离结构,至多具有比所述第一宽度更小的第二宽度,并且在所述第一表面处对由各阵列沟槽之间的半导体部分的区段所形成的半导体翅片进行切口。
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