CN104137244A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN104137244A
CN104137244A CN201280070478.0A CN201280070478A CN104137244A CN 104137244 A CN104137244 A CN 104137244A CN 201280070478 A CN201280070478 A CN 201280070478A CN 104137244 A CN104137244 A CN 104137244A
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spot area
semiconductor device
zone line
density
solder joint
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CN104137244B (zh
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远井茂男
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

本发明所涉及的半导体装置，具有：半导体元件，其具有在俯视观察时直线地形成的多个栅极、与该多个栅极绝缘的发射极图案、以及在该发射极图案上形成的发射极电极，并且形成为主电流经由该发射极图案流向该发射极电极；第1焊点，其形成在该发射极电极的一部分上；第2焊点，其与该第1焊点隔离地形成在该发射极电极的一部分上；以及端子，其经由该第1焊点以及该第2焊点与该发射极电极连接。该半导体元件具有形成有该第1焊点的第1焊点区域、形成有该第2焊点的第2焊点区域、以及该第1焊点区域和该第2焊点区域之间的区域即中间区域，该第1焊点区域的该栅极的密度、该第2焊点区域的该栅极的密度和该中间区域的该栅极的密度相等，该半导体元件形成为，该中间区域的该主电流的电流密度低于该第1焊点区域以及该第2焊点区域的该主电流的电流密度。

Description

半导体装置
技术领域
本发明涉及一种在大电流的开关等中使用的半导体装置。
背景技术
在专利文献1中公开了一种在半导体元件上形成有接触电极的半导体装置。半导体元件具有在其一部分上未形成元件的非加工部。由于非加工部成为非通电区域，因此不发热。专利文献1所公开的半导体装置，通过在半导体元件的一部分上设置不发热的非加工部，从而抑制半导体装置的最高温度。
专利文献1：日本特开2008－277523号公报
发明内容
在半导体元件的表面电极上焊接端子的技术称为直接引脚结合(Direct Lead Bonding)。如果使用一个大型焊点将表面电极与端子连接，则热收缩时的应力会增大，因此有时使用多个焊点将表面电极与端子连接。在该情况下，在半导体装置工作时，存在下述问题，即，夹在焊点和另一个焊点之间的半导体元件的区域温度上升。为了抑制半导体元件的温度上升，需要限制半导体装置的动作。
本发明就是为了解决上述问题而提出的，其目的在于，提供一种在利用多个焊点将表面电极与端子连接的半导体装置，该半导体装置能够抑制半导体元件的温度上升。
本发明所涉及的半导体装置具有：半导体元件，其具有在俯视观察时直线地形成的多个栅极、与该多个栅极绝缘的发射极图案、以及在该发射极图案上形成的发射极电极，并且形成为主电流经由该发射极图案流向该发射极电极；第1焊点，其形成在该发射极电极的一部分上；第2焊点，其与该第1焊点隔离地形成在该发射极电极的一部分上；以及端子，其经由该第1焊点以及该第2焊点与该发射极电极连接。而且，该半导体装置的特征在于，该半导体元件具有形成有该第1焊点的第1焊点区域、形成有该第2焊点的第2焊点区域、以及该第1焊点区域和该第2焊点区域之间的区域即中间区域，该第1焊点区域的该栅极的密度、该第2焊点区域的该栅极的密度和该中间区域的该栅极的密度相等，该半导体元件形成为，该中间区域的该主电流的电流密度低于该第1焊点区域以及该第2焊点区域的该主电流的电流密度。
本发明的其他特征在下面明示。
发明的效果
根据本发明，由于降低在半导体元件中被形成有焊点的区域夹着的区域即中间区域的主电流，因此能够抑制半导体元件的温度上升。
附图说明
图1是本发明的实施方式1所涉及的半导体装置的斜视图。
图2是包含图1的半导体装置的第1焊点以及第2焊点的部分处的剖面图。
图3是详细示出图2的半导体元件的剖面图。
图4是第1焊点区域、第2焊点区域、以及中间区域中的栅极、发射极图案、基极层的俯视图。
图5是本发明的实施方式2所涉及的半导体装置的剖面图。
图6是本发明的实施方式3所涉及的半导体装置的剖面图。
图7是本发明的实施方式4所涉及的半导体装置的剖面图。
图8是本发明的实施方式5所涉及的半导体装置的剖面图。
图9是本发明的实施方式6所涉及的半导体元件的剖面图。
具体实施方式
参照附图对本发明的实施方式所涉及的半导体装置进行说明。对相同或对应的构成要素标注相同的标号，有时省略重复说明。
实施方式1
图1是本发明的实施方式1所涉及的半导体装置的斜视图。半导体装置10具有在基板12上形成的基底板14。在基底板14上固定半导体元件16。半导体元件16例如是由Si形成的纵型IGBT。在半导体元件16的表面上，形成有分离地设置的4个焊点。4个焊点中包含第1焊点18以及第2焊点20。由该4个焊点将半导体元件16与端子22连接。
图2是包含图1的半导体装置10的第1焊点18以及第2焊点20的部分处的剖面图。半导体元件16具有：形成有第1焊点16的第1焊点区域50、形成有第2焊点20的第2焊点区域52、以及第1焊点区域50和第2焊点区域52之间的区域即中间区域54。
图3是详细示出图2的半导体元件的剖面图。半导体元件16具有n-层60。在n-层60上形成有电荷积蓄层62。在电荷积蓄层62上形成有基极层64。
以将基极层64和电荷积蓄层62贯穿而达到n-层60的方式形成栅极66。栅极66经由栅极绝缘膜与基极层64接触。能够通过对栅极66施加电压而使基极层64的导电型反转。以夹持栅极66的方式形成发射极图案70a、70b。栅极66与发射极图案70a、70b绝缘。在栅极66上形成有绝缘膜72。在发射极图案70a、70b上形成有发射极电极74。
在n-层60下面形成有缓冲层80。在缓冲层80的下面形成有集电极层82。缓冲层8是为了调整从集电极层82向n-层60的空穴的注入量而形成的。在集电极层82的下面形成有集电极电极84。如上所述，半导体元件16由纵型IGBT形成，在其正面形成有发射极电极74，在其背面形成有集电极电极84。
第1焊点18形成在发射极电极74的一部分上。第2焊点20与第1焊点18隔离而形成在发射极电极74的一部上。而且，端子22通过第1焊点18以及第2焊点20与发射极电极74连接。半导体元件16的主电流经由发射极图案70a、70b流向发射极电极74。
图4是第1焊点区域、第2焊点区域、以及中间区域中的栅极、发射极图案、基极层的俯视图。在各区域中栅极66形成有多个，并在俯视观察时分别直线地形成。栅极66在第1焊点区域50、第2焊点区域52、以及中间区域54的所有区域中以相等的间隔平行地排列。因此，第1焊点区域50的栅极66的密度、第2焊点区域52的栅极66的密度以及中间区域54的栅极66的密度相等。
中间区域54的发射极图案70a与第1焊点区域50以及第2焊点区域52的发射极图案70b相比，面积形成为较小。由此，对于俯视观察时每个单位面积中的发射极图案和发射极电极的接触面积，与第1焊点区域50以及第2焊点区域52相比，中间区域54中的接触面积较小。
根据本发明的实施方式1所涉及的半导体装置，中间区域54的发射极图案70a形成得较小，并且在中间区域54中难以流过大于第1焊点区域50以及第2焊点区域52的电流，因此能够抑制焊点之间(中间区域)的温度上升。另外，通过在中间区域中不形成栅极、使中间区域的栅极不起作用，也能够抑制中间区域的温度上升。在该情况下，中间区域成为对半导体元件的动作没有贡献的无效区域。另外，根据本发明的实施方式1所涉及的半导体装置10，能够在中间区域54中流过电流而使中间区域54对半导体元件16的动作有贡献，并且降低在中间区域54中流过的电流，从而抑制中间区域54的温度上升。
在本发明的实施方式1所涉及的半导体装置10中，在中间区域54中将发射极图案70a形成为小于第1焊点区域50的发射极图案70b以及第2焊点区域52的发射极图案70b，但是本发明不限定于此。即，只要将半导体元件16形成为中间区域54的主电流的电流密度低于第1焊点区域50以及第2焊点区域52的主电流的电流密度，就能实现本发明的效果，因此可以在具有该特征的范围内进行各种变形。
将本发明的实施方式1所涉及的半导体元件16设为由Si形成，但是也可以由与Si相比带隙宽的宽带隙半导体而形成。作为宽带隙半导体例如有碳化硅、氮化镓类材料或者金刚石。另外，半导体元件16不限定于纵型IGBT，例如，可以由MOSFET形成。另外，可以使半导体元件的各部分的导电型适当反转。
实施方式2
图5是本发明的实施方式2所涉及的半导体装置的剖面图。以与实施方式1所涉及的半导体装置的不同点为中心进行说明。
在中间区域54中的发射极图案70c的杂质密度，低于第1焊点区域50中的发射极图案70b的杂质密度以及第2焊点区域52中的发射极图案70b的杂质密度。在这里所谓杂质密度是指施主密度。
此外，施主密度可以设为实际有效施主密度。
根据本发明的实施方式2所涉及的半导体装置，也能够使中间区域54的主电流的电流密度低于第1焊点区域50以及第2焊点区域52的主电流的电流密度。因此，能够抑制焊点之间(中间区域)的温度上升。
实施方式3
图6是本发明的实施方式3所涉及的半导体装置的剖面图。以与实施方式1所涉及的半导体装置的不同点为中心进行说明。
在中间区域54中的基极层64a的杂质密度，高于在第1焊点区域50中的基极层64的杂质密度以及在第2焊点区域52中的基极层64的杂质密度。在这里所谓杂质密度是指受主密度。此外，受主密度可以设为实际有效受主密度。
根据本发明的实施方式3所涉及的半导体装置，能够提高中间区域54的栅极阀值电压，并使中间区域54的主电流的电流密度低于第1焊点区域50以及第2焊点区域52的主电流的电流密度。因此，能够抑制焊点之间(中间区域)的温度上升。
实施方式4
图7是本发明的实施方式4所涉及的半导体装置的剖面图。以与实施方式1所涉及的半导体装置的不同点为中心进行说明。
在中间区域54中，通过照射电子束等带电粒子而形成有带电粒子照射区域100。由于形成有带电粒子照射区域100，中间区域54的主电流的路径，与第1焊点区域50以及上述第2焊点区域52的主电流的路径相比，晶格缺陷增多。
由于晶格缺陷具有使在半导体物质内的电子-空穴载体再结合的功能，因此可以通过最优化晶格缺陷密度而实现载体的寿命控制。根据本发明的实施方式4所涉及的半导体装置，能够通过在中间区域54中导入晶格缺陷而进行中间区域54的载体的寿命控制，从而使中间区域54的导通电压上升。因此，能够使中间区域54的主电流的电流密度低于第1焊点区域50以及第2焊点区域52的主电流的电流密度，从而抑制焊点之间(中间区域)的温度上升。
实施方式5
图8是本发明的实施方式5所涉及的半导体装置的剖面图。以与实施方式1所涉及的半导体装置的不同点为中心进行说明。
中间区域54中的n-层110的电阻率与在第1焊点区域50以及第2焊点区域52中的n-层60的电阻率相比较高。因此，中间区域54的主电流路径的电阻率，与第1焊点区域50的主电流路径的电阻率以及第2焊点区域52的主电流路径的电阻率相比，较高。
根据本发明的实施方式5所涉及的半导体装置，能够使中间区域54的导通电压上升。因此，使中间区域54的主电流的电流密度低于第1焊点区域50以及第2焊点区域52的主电流的电流密度，从而能够抑制焊点之间(中间区域)的温度上升。
实施方式6
图9是本发明的实施方式6所涉及的半导体元件的剖面图。以与实施方式1所涉及的半导体装置的不同点为中心进行说明。
将中间区域54的宽度(X1)形成为大于或等于第1焊点区域50的宽度(X2)或第2焊点区域52的宽度(X3)的一半。通过使第1焊点区域50与第2焊点区域52充分隔离，从而使得在第1焊点区域50中产生的热量与在第2焊点区域52中产生的热量不干涉。因此，能够抑制焊点之间(中间区域)的温度上升。
宽度X1并不特别限定于大于或等于宽度X2或宽度X3的一半。此外，本发明的实施方式2至6所涉及的半导体装置可以进行至少与实施方式1相同程度的变形。另外，可以适当地组合各实施方式所涉及的半导体装置的特征。
标号的说明
10半导体装置，12基板，14基底板，16半导体元件，22端子，50第1焊点区域，52第2焊点区域，54中间区域，60 n-层，62电荷积蓄层，64、64a基极层，66栅极，70a、70b、70c发射极图案，72绝缘膜，74发射极电极，80缓冲层，82集电极层，84集电极电极，100带电粒子照射区域，110 n-层

Claims (10)

1.一种半导体装置的特征在于，具有：
半导体元件，其具有在俯视观察时直线地形成的多个栅极、与所述多个栅极绝缘的发射极图案、以及在所述发射极图案上形成的发射极电极，并且形成为主电流经由所述发射极图案流向所述发射极电极；
第1焊点，其形成在所述发射极电极的一部分上；
第2焊点，其与所述第1焊点隔离地形成在所述发射极电极的一部分上；以及
端子，其经由所述第1焊点以及所述第2焊点与所述发射极电极连接，
所述半导体元件具有形成有所述第1焊点的第1焊点区域、形成有所述第2焊点的第2焊点区域、以及所述第1焊点区域和所述第2焊点区域之间的区域即中间区域，
所述第1焊点区域的所述栅极的密度、所述第2焊点区域的所述栅极的密度和所述中间区域的所述栅极的密度相等，
所述半导体元件形成为，所述中间区域的所述主电流的电流密度低于所述第1焊点区域以及所述第2焊点区域的所述主电流的电流密度。
2.根据权利要求1所述的半导体装置，其特征在于，
对于俯视观察时的每个单位面积中的所述发射极图案和所述发射极电极的接触面积，与所述第1焊点区域以及所述第2焊点区域相比，所述中间区域中的所述接触面积较小。
3.根据权利要求1所述的半导体装置，其特征在于，
在所述中间区域中的所述发射极图案的杂质密度，低于所述第1焊点区域中的所述发射极图案的杂质密度以及所述第2焊点区域中的所述发射极图案的杂质密度。
4.根据权利要求1所述的半导体装置，其特征在于，
具有基极层，该基极层与所述栅极接触而形成，通过对所述栅极施加电压而导电型反转，
所述中间区域中的所述基极层的杂质密度，高于所述第1焊点区域中的所述基极层的杂质密度以及所述第2焊点区域中的所述基极层的杂质密度。
5.根据权利要求1所述的半导体装置，其特征在于，
与所述第1焊点区域、以及所述第2焊点区域的所述主电流的路径相比，所述中间区域的所述主电流的路径的晶格缺陷较多。
6.根据权利要求1所述的半导体装置，其特征在于，
所述中间区域的所述主电流的路径的电阻率，高于所述第1焊点区域的所述主电流的路径的电阻率以及所述第2焊点区域的所述主电流的路径的电阻率。
7.根据权利要求1所述的半导体装置，其特征在于，
所述中间区域的宽度大于或等于所述第1焊点区域或者所述第2焊点区域的宽度的一半。
8.根据权利要求1至7中任一项所述的半导体装置，其特征在于，
所述半导体元件是纵型IGBT，在其正面形成有所述发射极电极，在其背面形成有所述集电极电极。
9.根据权利要求1至8中任一项所述的半导体装置，其特征在于，
所述半导体元件由宽带隙半导体形成。
10.根据权利要求9所述的半导体装置，其特征在于，
所述宽带隙半导体是碳化硅、氮化镓类材料或者金刚石。
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