CN104078502A - 半导体功率器件及其制作方法 - Google Patents

半导体功率器件及其制作方法 Download PDF

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CN104078502A
CN104078502A CN201310159523.6A CN201310159523A CN104078502A CN 104078502 A CN104078502 A CN 104078502A CN 201310159523 A CN201310159523 A CN 201310159523A CN 104078502 A CN104078502 A CN 104078502A
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林永发
张家豪
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Anpec Electronics Corp
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Abstract

本发明公开了一种半导体功率器件的制作方法，包含有一晶胞区域，设于一半导体基底上；至少一晶体管器件，设于所述晶胞区域内；一周边耐压区域，环绕所述晶胞区域；多个岛状的第一外延层，设于所述周边耐压区域内；以及一格状的第二外延层，设于所述周边耐压区域内且环绕各所述岛状外延层，将所述多个岛状的第一外延层彼此区隔开。

Description

半导体功率器件及其制作方法
技术领域
本发明涉及一种半导体功率器件及其制作方法，尤其涉及一种具有超结(super junction)结构的半导体功率器件(例如功率晶体管)及其制作方法。
背景技术
已知，在功率器件中，其基底的设计通常为P型与N型半导体交替设置，因此在基底中会存在有多个垂直于基底表面的PN结，且该些PN结是互相平行的，又称为超结结构，此种结构具有耐压低阻抗的优点。
然而，采用上述超结结构来设计功率器件时，由于器件的耐压终止区(withstanding termination region)基底的浓度已经提高，故对于现有的浮置环(floating ring)或场效电板(field plate)的终止区设计来说，其耐压效果已明显不足。
发明内容
本发明的目的，即提供一种改良的半导体功率器件及其制作方法，以解决现有技术的不足与缺点。
为达上述目的，本发明提出一种半导体功率器件，包含有一晶胞区域，设于一半导体基底上；至少一晶体管器件，设于所述晶胞区域内；一周边耐压区域，环绕所述晶胞区域；多个岛状的第一外延层，设于所述周边耐压区域内；以及一格状的第二外延层，设于所述周边耐压区域内且环绕各所述第一外延层，将多个所述岛状的第一外延层彼此区隔开。
其中所述多个岛状的第一外延层具有第一导电型，所述半导体基底具有第二导电型，所述格状的第二外延层具有所述第二导电型。其中可进一步包含有一第二导电型的第三外延层，介于所述第一外延层、第二外延层与所述半导体基底之间。
为让本发明的上述目的、特征及优点能更明显易懂，下文中特举优选实施方式并配合附图作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制。
附图说明
图1为超结功率晶体管的布局仰视图。
图2为图1的局部放大示意图。
图3为沿着图2中切线I-I’所作的横断面示意图。
图4为超结功率晶体管的局部放大仰视图。
图5为沿着图4中切线II-II’所作的横断面示意图。
图6为依据本发明第三实施例所绘示的超结功率晶体管的横断面示意图。
图7为依据本发明第四实施例所绘示的超结功率晶体管的横断面示意图。
图8为超结功率晶体管的局部放大仰视图。
图9为沿着图8中切线III-III’所作的横断面示意图。
图10至图19例示出超结功率晶体管的制作方法，其中以制作图6中的超结功率晶体管为例来做说明。
图20为晶圆在外延层中进行沟槽刻蚀后的仰视示意图。
其中，附图标记说明如下：
1～5  超结功率晶体管 111  图案化硬掩膜
10    半导体基底     111a 开口
11    外延层         112  外延层
22    栅极氧化层     112a 沟槽结构
24    栅极           112b 沟槽结构
26    场氧化层       120  岛状外延层
30    层间介电层     130  离子井
34    金属层         132  源极掺杂区
34a   接触插塞       230  接触洞
60    芯片区域       330  掺杂带
90    划线区域       430  掺杂带
100   晶胞区域       602  栅极结构
101   过渡区         630  护环掺杂区
102   周边耐压区域   634  金属层
110   外延层         634a 接触插塞
110’ 端部           702  场效电板
110a  外延层
具体实施方式
下文中将借由附图来详细说明本发明的技术特征，其中各附图中相同的组件或部位会沿用相同的符号来表示。需注意的是，各附图是以说明为目的，其并未依照原尺寸作图。此外，下文中所提及的“第一导电型”以及“第二导电型”是用以描述不同材料间的相对导电型种类。举例而言，其可分别对应至P型以及N型，然而，其也可分别对应至N型以及P型。
请参阅图1至图3，其为依据本发明第一实施例所绘示的超结功率晶体管的示意图，其中图1为超结功率晶体管的布局仰视图，图2为图1的局部放大示意图，图3为沿着图2中切线I-I’所作的横断面示意图。首先，如图1所示，超结功率晶体管1的布局结构，包括一晶胞区域(cell region)100以及一环绕晶胞区域100的周边耐压区域(termination region)102，其中晶胞区域100是用于设置具有开关功能的晶体管器件，而周边耐压区域102是具有延缓高强度电场向外扩散的耐压结构。为简化说明，图1中仅绘示出位于晶胞区域100内直线交替排列的第一导电型(例如P型)外延层110及第二导电型(例如N型)外延层112，以及位于周边耐压区域102内的多个第一导电型(例如P型)的岛状外延层120。
如图2及图3所示，根据第一实施例，超结功率晶体管1包括一半导体基底10，其具有第二导电型，例如重掺杂的N+硅基底，其可作为超结功率晶体管1的漏极。半导体基底10上设有一第二导电型(例如N型)的外延层11，外延层11上则为一垂直交替的外延层，其包括第一导电型(例如P型)的外延层110、第一导电型(例如P型)的岛状外延层120，及第二导电型(例如N型)的外延层112。其中，根据第一实施例，外延层110及外延层112在晶胞区域100内呈直线交替排列且彼此互相平行，构成超结结构。岛状外延层120则是位于周边耐压区域102，一圈一圈的层层环绕晶胞区域100，呈阵列排列态样。在图中，岛状外延层120的圈数仅绘示有六圈，但此仅为例示，不限于六圈。根据第一实施例，外延层112在周边耐压区域102中则为格状或井字形，围绕着各岛状外延层120。
晶胞区域100内还具有第一导电型(例如P型)离子井130位于各个外延层110的上部区域，以及源极掺杂区132位于离子井130内。根据第一实施例，最外面且靠近周边耐压区域102的外延层110a上的离子井130内不会有源极掺杂区132形成。
根据第一实施例，在晶胞区域100内，栅极24正位于外延层112上，栅极氧化层22则位于栅极24与外延层112之间。根据第一实施例，周边耐压区域102内另有连续、环状的第一导电型(例如P型)掺杂带330，将各圈的岛状外延层120串连起来，其中掺杂带330可以仅部分重叠于各圈的岛状外延层120。层间介电层30覆盖晶胞区域100及周边耐压区域102，位于层间介电层30上的金属层34经由形成在接触洞230内的接触插塞34a来与晶胞区域100内的源极掺杂区132及离子井130电连接。根据第一实施例，周边耐压区域102内另有一场氧化层26，位于层间介电层30下方。
图4及图5为依据本发明第二实施例所绘示的超结功率晶体管示意图，其中图4为超结功率晶体管的局部放大仰视图，图5为沿着图4中切线II-II’所作的横断面示意图。如图4所示，超结功率晶体管2的布局结构包括一晶胞区域100以及一环绕晶胞区域100的周边耐压区域102，根据第二实施例，晶胞区域100以及周边耐压区域102之间另有一过渡区101。
如图4及图5所示，超结功率晶体管2同样包括一半导体基底10，其具有第二导电型，例如重掺杂N+硅基底，其可作为超结功率晶体管2的漏极。半导体基底10上设有一第二导电型(例如N型)的外延层11，外延层11上则设有第一导电型(例如P型)的外延层110、第一导电型(例如P型)的岛状外延层120，及第二导电型(例如N型)的外延层112。其中，根据第一实施例，外延层110及外延层112在晶胞区域100内呈直线交替排列且彼此互相平行，岛状外延层120则是位于周边耐压区域12，其呈阵列排列态样。晶胞区域100内还有第一导电型(例如P型)的离子井130位于各个外延层110的上部区域，以及源极掺杂区132位于离子井130内。最外面的外延层110a上的离子井130内不会有源极掺杂区132形成。
根据第二实施例，在晶胞区域100内，栅极24位于外延层112上，栅极氧化层22则位于栅极24与外延层112之间。同样的，在周边耐压区域102内，各圈的岛状外延层120被连续、环状的第一导电型(例如P型)掺杂带330串连起来。层间介电层30覆盖晶胞区域100及周边耐压区域102，位于层间介电层30上的金属层34经由接触洞230内的接触插塞34a来与晶胞区域100内的源极掺杂区132及离子井130电连接。周边耐压区域102内另有一场氧化层26位于层间介电层30下方。
过渡区101内具有横跨外延层110a及最靠近晶胞区域100的第一圈、第二圈岛状外延层120的第一导电型(例如P型)掺杂带430。此掺杂带430为一环状布局，在此例中为矩形态样，范围可以涵盖最内的第一圈、第二圈岛状外延层120，外延层110a，以及晶胞区域100内的外延层110的端部110’。根据第二实施例，掺杂带430经由接触洞230内的接触插塞34a来电连接金属层34。过渡区101可以进一步减缓晶胞区域100与周边耐压区域102之间的电场强度。
图6为依据本发明第三实施例所绘示的超结功率晶体管的横断面示意图。图6中的第三实施例的超结功率晶体管3与图5的第二实施例主要差异在于：(1)过渡区101内，横跨外延层110a及最靠近晶胞区域100的第一圈、第二圈岛状外延层120的第一导电型(例如P型)护环掺杂区630，其中护环掺杂区630的掺杂浓度、深度可大于外延层110a上的离子井130；(2)离子井130与护环掺杂区630重叠；(3)在护环掺杂区630上设有一栅极结构602，且栅极结构602横跨过渡区101与周边耐压区域102，并延伸至场氧化层26上，其中栅极结构602经由接触插塞634a电连接金属层634。
图7为依据本发明第四实施例所绘示的超结功率晶体管的横断面示意图。图7中第四实施例的超结功率晶体管4与图6的第三实施例主要差异在于：场氧化层26上靠近栅极结构602处另设有一场效电板702，其中，栅极结构602与场效电板702可以是环状的，且可由多晶硅所构成。根据第四实施例，场效电板702是位于周边耐压区域102内。
图8及图9为依据本发明第五实施例所绘示的超结功率晶体管的示意图，其中图8为超结功率晶体管5的局部放大仰视图，图9为沿着图8中切线III-III’所作的横断面示意图。图8～9中第五实施例的超结功率晶体管5与图7的第四实施例的主要差异在于：位于周边耐压区域102的岛状外延层120是各自独立的，其不再经由连续、环状的第一导电型(例如P型)掺杂带330串连起来。从图9可看出，周边耐压区域102的岛状外延层120上方为外延层112。
图10至图19例示出超结功率晶体管的制作方法，其中以制作图6中的超结功率晶体管为例来说明。首先，如图10所示，提供一半导体基底10，其具有第二导电型，例如重掺杂N+硅基底，其可作为超结功率晶体管1的漏极。半导体基底10上形成有一第二导电型(例如N型)的外延层11，接着在外延层11上形成一第一导电型(例如P型)的外延层110。
如图11所示，于外延层110上形成一图案化硬掩膜111。接着利用图案化硬掩膜111作为刻蚀屏蔽，进行干刻蚀工艺，经由图案化硬掩膜111的开口111a向下刻蚀出沟槽结构112a及沟槽结构112b，并同时界定出晶胞区域100内直线排列的第一导电型外延层110，以及周边耐压区域102内的多个第一导电型岛状外延层120。其中沟槽结构112a为平行于第一导电型外延层110的直线型沟槽，而沟槽结构112b则为环绕第一导电型的岛状外延层120的网状或格状沟槽，如图20所示。值得注意的是，沟槽结构112a及沟槽结构112b的刻蚀步骤是对整片晶圆同时进行，而且是跨越不同芯片区域60来进行，如图20所示，芯片区域60之间为划线区域90，而沟槽结构112b可形成在划线区域90，并与沟槽结构112a对齐。
如图12所示，在形成沟槽结构112a及沟槽结构112b之后，可以选择性地于沟槽表面形成牺牲氧化层(未示于图中)，再将牺牲氧化层去除。然后，在沟槽结构112a及沟槽结构112b内填满第二导电型(例如N型)的外延层112，并且使外延层112覆盖第一导电型外延层110。另外，也可以继续进行化学机械抛光(chemical mechanical polishing,CMP)工艺，先抛光去除部分厚度的外延层112，再进行氧化工艺形成一氧化膜(未示于图中)，然后去除所述氧化膜，接着再进行一次第一导电型外延工艺。
如图13所示，进行离子注入工艺在周边耐压区域102内形成连续环状的第一导电型(例如P型)掺杂带330。掺杂带330是形成在外延层112中，将各圈的岛状外延层120串连起来，其中掺杂带330可以仅部分重叠于各圈的岛状外延层120。
如图14所示，接着于外延层112上形成场氧化层26，再以光刻工艺及刻蚀工艺大致将晶胞区域100及过渡区101内的场氧化层26去除，显露出位于晶胞区域100及过渡区101内的外延层112，留下位于周边耐压区域102内的场氧化层26。
如图15所示，利用光刻及离子注入工艺在过渡区101内的外延层112注入第一导电型(例如P型)的掺质，例如硼，形成第一导电型护环掺杂区630。此护环掺杂区630为一环状布局。
如图16所示，接着进行一氧化工艺，于外延层112表面形成一栅极氧化层22。然后，进行化学气相沉积(chemical vapor deposition,CVD)工艺，全面沉积一多晶硅层，再以光刻工艺及刻蚀工艺，将多晶硅层刻蚀界定为晶胞区域100内的栅极24以及周边耐压区域102内的栅极结构602。
如图17所示，利用光刻及离子注入工艺于晶胞区域100内各个外延层110的上部区域以及外延层110a的上部区域形成第一导电型(例如P型)的离子井130，其中外延层110a上的离子井130与护环掺杂区630重叠。上述形成离子井130的离子注入工艺是自动对准于栅极24，而在周边耐压区域102内则是被光刻胶所覆盖，不会形成离子井130。
如图18所示，接着再次利用光刻及离子注入工艺，于离子井130内形成源极掺杂区132。最后，如图19所示，沉积层间介电层30，使其覆盖在栅极24与栅极结构602上。接着，利用光刻工艺及刻蚀工艺，于层间介电层30中形成接触洞230，再以金属层34填满接触洞230构成接触插塞34a及634a，使金属层34与晶胞区域100内的源极掺杂区132及离子井130电连接，而且使金属层634与栅极结构602电连接。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

1.一种半导体功率器件，其特征在于，包含：
一晶胞区域，设于一半导体基底上；
至少一晶体管器件，设于所述晶胞区域内；
一周边耐压区域，环绕所述晶胞区域；
多个岛状的第一外延层，设于所述周边耐压区域内；以及
一格状的第二外延层，设于所述周边耐压区域内且环绕并隔开各所述岛状的第一外延层。
2.根据权利要求1所述的半导体功率器件，其特征在于，所述第一外延层具有第一导电型，所述半导体基底具有第二导电型，所述第二外延层具有所述第二导电型。
3.根据权利要求2所述的半导体功率器件，其特征在于，所述第一导电型为P型，所述第二导电型为N型。
4.根据权利要求2所述的半导体功率器件，其特征在于，另包含一第三外延层，介于所述第一外延层、第二外延层与所述半导体基底之间。
5.根据权利要求4所述的半导体功率器件，其特征在于，所述第三外延层具有所述第二导电型。
6.根据权利要求1所述的半导体功率器件，其特征在于，所述晶体管器件至少包含一直线型的所述第一外延层与至少一直线型的所述第二外延层、一离子井设于所述第一外延层的上部区域，以及源极掺杂区位于所述离子井内。
7.根据权利要求1所述的半导体功率器件，其特征在于，另包含至少一连续、环状的掺杂带，位于所述周边耐压区域内，将所述多个岛状的第一外延层串连起来。
8.根据权利要求7所述的半导体功率器件，其特征在于，所述掺杂带具有所述第一导电型。
9.根据权利要求1所述的半导体功率器件，其特征在于，另包含一过渡区，位于所述晶胞区域以及所述周边耐压区域之间。
10.根据权利要求9所述的半导体功率器件，其特征在于，所述过渡区为环状布局。
11.根据权利要求9所述的半导体功率器件，其特征在于，另包含一护环掺杂区，位于所述过渡区。
12.根据权利要求11所述的半导体功率器件，其特征在于，所述护环掺杂区具有所述第一导电型。
13.根据权利要求11所述的半导体功率器件，其特征在于，在所述护环掺杂区上设有一栅极结构，且所述栅极结构横跨所述过渡区与所述周边耐压区域并延伸至一场氧化层上。
14.根据权利要求13所述的半导体功率器件，其特征在于，另包含一场效电板，位于所述场氧化层上。
15.根据权利要求14所述的半导体功率器件，其特征在于，所述栅极结构与所述场效电板都为多晶硅层。
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