CN114512403A - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
CN114512403A
CN114512403A CN202011280137.9A CN202011280137A CN114512403A CN 114512403 A CN114512403 A CN 114512403A CN 202011280137 A CN202011280137 A CN 202011280137A CN 114512403 A CN114512403 A CN 114512403A
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layer
insulating layer
type semiconductor
source
semiconductor layer
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CN114512403B (zh
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龚轶
刘伟
毛振东
徐真逸
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Suzhou Dongwei Semiconductor Co ltd
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Suzhou Dongwei Semiconductor Co ltd
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Priority to CN202011280137.9A priority Critical patent/CN114512403B/zh
Priority to KR1020227001136A priority patent/KR102568095B1/ko
Priority to JP2021569956A priority patent/JP7263644B2/ja
Priority to PCT/CN2020/130600 priority patent/WO2022099765A1/zh
Priority to US17/614,253 priority patent/US20230268432A1/en
Publication of CN114512403A publication Critical patent/CN114512403A/zh
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Abstract

本发明公开了一种半导体器件的制造方法，首先，栅极沟槽和源极沟槽在同一步刻蚀工艺中同时形成，并且可以在源极沟槽内自对准的接触p型半导体层和p型掺杂区，工艺过程简单；其次，在栅极沟槽的下部内形成第一绝缘层和第一栅极，在栅极沟槽的上部内形成第二绝缘层和第二栅极，厚的第一绝缘层可以保护第二栅极不容易被击穿，第一栅极可以增加栅极沟槽底部附近的电场，提高半导体器件的耐压；再次，源极沟槽的底部可以深入第二n型半导体层内，源极沟槽下方的p型掺杂区可以增加源极沟槽底部附近的电场，把半导体器件内的最高电场限定在源极沟槽的底部附近，保护栅极沟槽内的栅极不容易被击穿并提高半导体器件的耐压。

Description

半导体器件的制造方法
技术领域
本发明属于半导体器件技术领域，特别是涉及一种半导体器件的制造方法。
背景技术
碳化硅具有不同于传统硅半导体材料的诸多特点，其能带间隙为硅的2.8倍,绝缘击穿场强为硅的5.3倍,因此在高压功率器件领域，碳化硅器件可以使用相对于硅材料更薄的外延层来达到传统硅器件相同的耐压水平，同时拥有更低的导通电阻。目前，利用碳化硅制备沟槽功率器件的主要问题在于，在器件运行时会有很大的电场施加在栅极沟槽内的栅介质层上，这使得栅极容易被击穿，影响了器件的耐压。
发明内容
有鉴于此，本发明的目的是提供一种半导体器件的制造方法，以降低半导体器件的栅极被击穿的风险，并提高半导体器件的耐压。
为达到本发明的上述目的，本发明提供了一种半导体器件的制造方法，包括：
提供一半导体衬底，所述半导体衬底包括依次层叠设置的第一n型半导体层、第二n型半导体层、p型半导体层和第三n型半导体层；
进行光刻和刻蚀，在所述半导体衬底内同时形成交替间隔设置的栅极沟槽和源极沟槽，所述栅极沟槽的底部和所述源极沟槽的底部均位于所述第二n型半导体层内，所述源极沟槽的宽度大于所述栅极沟槽的宽度；
形成覆盖所述栅极沟槽的内壁并覆盖所述源极沟槽的内壁的第一绝缘层；
形成第一导电层并回刻，刻蚀后剩余的所述第一导电层在所述栅极沟槽内形成第一栅极；
对所述第一绝缘层进行各向异性刻蚀，将所述源极沟槽下方的所述第二n型半导体层暴露出来；
进行p型离子注入，在所述第二n型半导体层内形成位于所述源极沟槽下方的p型掺杂区；
对所述栅极沟槽内的所述第一绝缘层进行刻蚀，使得所述栅极沟槽内的所述第一绝缘层的上表面不高于所述p型半导体层的下表面；
形成第二绝缘层，并对所述第二绝缘层进行刻蚀，去除掉所述源极沟槽内的所述第二绝缘层；
形成第二导电层，然后对所述第二导电层进行刻蚀，刻蚀后剩余的所述第二导电层在所述栅极沟槽内形成第二栅极并在所述源极沟槽内形成源极。
可选的，所述第一n型半导体层、所述第二n型半导体层、所述p型半导体层和所述第三n型半导体层均为碳化硅层。
可选的，形成所述第一导电层时，所述第一导电层填满所述栅极沟槽但不填满所述源极沟槽。
可选的，在形成所述第二绝缘层前，先刻蚀掉所述栅极沟槽内的所述第一栅极。
可选的，去除掉所源极沟槽内的所述第二绝缘层后，继续对所述源极沟槽内的所述第一绝缘层进行各向异性刻蚀，使得所述p型半导体层在所述源极沟槽的侧壁位置处暴露出来。
可选的，所述第一绝缘层的厚度大于所述第二绝缘层的厚度。
可选的，所述第一绝缘层的材料为氧化硅。
可选的，所述第二绝缘层的材料为氧化硅、氮化硅、氮氧化硅和氧化铪中的至少一种。
可选的，所述第一导电层的材料为导电性多晶硅。
可选的，所述第二导电层的材料为钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。
本发明提供的一种半导体器件的制造方法，首先，栅极沟槽和源极沟槽在同一步刻蚀工艺中同时形成，并且可以在源极沟槽内自对准的接触p型半导体层和p型掺杂区，工艺过程简单；其次，在栅极沟槽的下部内形成第一绝缘层和第一栅极，在栅极沟槽的上部内形成第二绝缘层和第二栅极，厚的第一绝缘层可以保护第二栅极不容易被击穿，第一栅极可以增加栅极沟槽底部附近的电场，提高半导体器件的耐压；再次，源极沟槽的底部可以深入第二n型半导体层内，源极沟槽下方的p型掺杂区可以增加源极沟槽底部附近的电场，把半导体器件内的最高电场限定在源极沟槽的底部附近，保护栅极沟槽内的第二栅极不容易被击穿并提高半导体器件的耐压。
附图说明
为了更加清楚地说明本发明示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1-图7是本发明提供的半导体器件的制造方法的一个实施例的制造工艺中的主要技术节点的剖面结构示意图；
图8是通过本发明的半导体器件的制造方法制造得到的半导体器件的另一个实施例的剖面结构示意图。
具体实施方式
以下将结合本发明实施例中的附图，完整地描述本发明的技术方案。应当理解，本发明所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在。同时，为清楚地说明本发明的具体实施方式，说明书附图中所列示意图，放大了本发明所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。
图1-图7是本发明提供的半导体器件的制造方法的一个实施例的制造工艺中的主要技术节点的剖面结构示意图，首先，如图1所示，提供一个半导体衬底，该半导体衬底包括依次层叠设置的第一n型半导体层20、第二n型半导体层21、p型半导体层22和第三n型半导体层23，第一n型半导体层20作为半导体器件的n型漏区，可选的，第一n型半导体层20、第二n型半导体层21、p型半导体层22和第三n型半导体层23均为碳化硅层。
接下来，如图2所示，进行光刻和刻蚀，在半导体衬底内同时形成交替间隔设置的栅极沟槽51和源极沟槽52，栅极沟槽51的底部和源极沟槽52的底部均位于第二n型半导体层21内，源极沟槽52的宽度大于栅极沟槽51的宽度。栅极沟槽51和源极沟槽52的数量由所设计的半导体器件的具体规格确定，本发明实施例中仅示例性的示出了一个栅极沟槽51和两个源极沟槽52。
栅极沟槽51和源极沟槽52之间的p型半导体层22作为半导体器件的p型体区，栅极沟槽51和源极沟槽52之间的第三n型半导体层23作为半导体器件的n型源区。
接下来，如图3所示，形成第一绝缘层24，第一绝缘层24应覆盖栅极沟槽的内壁并覆盖源极沟槽的内壁。可选的，第一绝缘层24的材料为氧化硅，通过淀积工艺形成。然后形成第一导电层并回刻，刻蚀后剩余的第一导电层在栅极沟槽内形成第一栅极25。可选的，第一导电层为导电性多晶硅。由于源极沟槽的宽度大于栅极沟槽的宽度，在形成第一导电层时，可以使第一导电层填满栅极沟槽但不填满源极沟槽，因此在刻蚀第一导电层时，通过各向异性的刻蚀方法可以直接刻蚀掉源极沟槽内的第一导电层，而在栅极沟槽内剩余一部分第一导电层以形成第一栅极25。图3中，以第一栅极25的上表面低于p型半导层22的下表面示出，但是本发明对第一栅极25的上表面与p型半导层22的下表面的位置关系不做限定。
接下来，如图4所示，对第一绝缘层24进行各向异性刻蚀，将源极沟槽下方的第二n型半导体层21暴露出来；然后进行p型离子注入，在第二n型半导体层21内形成位于源极沟槽下方的p型掺杂区26。图4中，以刻蚀后剩余的第一绝缘层24的上表面高于p型半导体层22的上表面示出，可选的，也可以使刻蚀后剩余的第一绝缘层24的上表面低于p型半导体层22的上表面，或者使刻蚀后剩余的第一绝缘层24的上表面与p型半导体层22的上表面位置相同。
接下来，如图5所示，淀积一层光刻胶42，通过光刻工艺将栅极沟槽暴露出来，然后对栅极沟槽内的第一绝缘层24进行刻蚀，使得栅极沟槽内剩余的第一绝缘层24的上表面不高于p型半导体层22的下表面。
接下来，如图6所示，去除掉光刻胶后形成第二绝缘层27，然后淀积一层光刻胶43，通过光刻工艺将源极沟槽暴露出来，然后对源极沟槽内的第二绝缘层进行刻蚀，去除掉源极沟槽内的第二绝缘层。之后，继续对源极沟槽内的第一绝缘层24进行各向异性刻蚀，使得p型半导体层22在源极沟槽的侧壁位置处暴露出来。可选的，在对第一绝缘层24进行各向异性刻蚀将源极沟槽下方的第二n型半导体层21暴露出来时，若同时将p型半导体层22在源极沟槽的侧壁位置处暴露出来，则在去除掉源极沟槽内的第二绝缘层后，可以不再对源极沟槽内的第一绝缘层进行刻蚀。第二绝缘层27作为半导体器件的栅介质层，其厚度可以小于第一绝缘层24的厚度，第二绝缘层27的材料可以为氧化硅、氮化硅、氮氧化硅和氧化铪中的至少一种，也可以为其它高介电常数的绝缘介质。
接下来，如图7所示，形成第二导电层28，并对第二导电层28进行刻蚀，刻蚀后剩余的第二导电层28在栅极沟槽内形成第二栅极并在源极沟槽内形成源极。可选的，第二导电层28的材料可以为钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。由于p型半导体层22和p型掺杂区26在源极沟槽内被暴露出来，因此形成第二导电层28时，第二导电层28可以自对准的接触p型半导体层22、第三n型半导体层23和p型掺杂区26。
本发明提供的半导体器件的制造方法，在形成第二绝缘层27前，可以先刻蚀掉栅极沟槽内的第一栅极，然后再形成第二绝缘层27，最后再形成第二导电层28，由此形成的半导体器件的结构如图8所示。
以上具体实施方式及实施例是对本发明技术思想的具体支持，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本发明技术方案保护的范围。

Claims (10)

1.半导体器件的制造方法，其特征在于，包括：
提供一半导体衬底，所述半导体衬底包括依次层叠设置的第一n型半导体层、第二n型半导体层、p型半导体层和第三n型半导体层；
进行光刻和刻蚀，在所述半导体衬底内同时形成交替间隔设置的栅极沟槽和源极沟槽，所述栅极沟槽的底部和所述源极沟槽的底部均位于所述第二n型半导体层内，所述源极沟槽的宽度大于所述栅极沟槽的宽度；
形成覆盖所述栅极沟槽的内壁并覆盖所述源极沟槽的内壁的第一绝缘层；
形成第一导电层并回刻，刻蚀后剩余的所述第一导电层在所述栅极沟槽内形成第一栅极；
对所述第一绝缘层进行各向异性刻蚀，将所述源极沟槽下方的所述第二n型半导体层暴露出来；
进行p型离子注入，在所述第二n型半导体层内形成位于所述源极沟槽下方的p型掺杂区；
对所述栅极沟槽内的所述第一绝缘层进行刻蚀，使得所述栅极沟槽内的所述第一绝缘层的上表面不高于所述p型半导体层的下表面；
形成第二绝缘层，并对所述第二绝缘层进行刻蚀，去除掉所述源极沟槽内的所述第二绝缘层；
形成第二导电层，然后对所述第二导电层进行刻蚀，刻蚀后剩余的所述第二导电层在所述栅极沟槽内形成第二栅极并在所述源极沟槽内形成源极。
2.如权利要求1所述的制造方法，其特征在于，所述第一n型半导体层、所述第二n型半导体层、所述p型半导体层和所述第三n型半导体层均为碳化硅层。
3.如权利要求1所述的制造方法，其特征在于，形成所述第一导电层时，所述第一导电层填满所述栅极沟槽但不填满所述源极沟槽。
4.如权利要求1所述的制造方法，其特征在于，在形成所述第二绝缘层前，先刻蚀掉所述栅极沟槽内的所述第一栅极。
5.如权利要求1所述的制造方法，其特征在于，去除掉所源极沟槽内的所述第二绝缘层后，继续对所述源极沟槽内的所述第一绝缘层进行各向异性刻蚀，使得所述p型半导体层在所述源极沟槽的侧壁位置处暴露出来。
6.如权利要求1所述的制造方法，其特征在于，所述第一绝缘层的厚度大于所述第二绝缘层的厚度。
7.如权利要求1所述的制造方法，其特征在于，所述第一绝缘层的材料为氧化硅。
8.如权利要求1所述的制造方法，其特征在于，所述第二绝缘层的材料为氧化硅、氮化硅、氮氧化硅和氧化铪中的至少一种。
9.如权利要求1所述的制造方法，其特征在于，所述第一导电层的材料为导电性多晶硅。
10.如权利要求1所述的制造方法，其特征在于，所述第二导电层的材料为钛、镍、铜、铝、银、金、氮化钛和钨中的至少一种。
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