CN103972197A - 半导体器件及其制造方法、引线和制作该引线的方法 - Google Patents

半导体器件及其制造方法、引线和制作该引线的方法 Download PDF

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Publication number
CN103972197A
CN103972197A CN201410034046.5A CN201410034046A CN103972197A CN 103972197 A CN103972197 A CN 103972197A CN 201410034046 A CN201410034046 A CN 201410034046A CN 103972197 A CN103972197 A CN 103972197A
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China
Prior art keywords
lead
wire
semiconductor device
fet chip
chip
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CN201410034046.5A
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中村公一
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Chuangshifang Electronic Japan Co., Ltd.
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Fujitsu Semiconductor Ltd
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Publication of CN103972197A publication Critical patent/CN103972197A/zh
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Abstract

本发明公开了一种半导体器件、一种制造该半导体器件的方法、一种引线和一种制作该引线的方法。该半导体器件包括：FET芯片；焊盘，设置在所述FET芯片上；多个凸块，设置在至少一个所述焊盘上；引线，包括通过凸块连接到所述FET芯片并且沿所述FET芯片的上表面延伸的第一部分，以及与沿所述FET芯片的上表面的所述第一部分接触并且沿所述FET芯片侧面延伸的第二部分，所述第一部分和第二部分通过压制或切割而形成；以及密封层，密封所述FET芯片和所述引线，并且密封所述引线的暴露所述第二部分的表面，所述密封层的表面位于所述FET芯片的下表面上。本发明公开的半导体器件能提高器件的可靠性。

Description

半导体器件及其制造方法、引线和制作该引线的方法
技术领域
本发明涉及一种半导体器件、一种制造该半导体器件的方法、一种引线和一种制作该引线的方法。
背景技术
近来，已在大量地制造其中通过凸块将半导体芯片与引线倒装芯片连接倒装芯片连接。例如，众所周知将半导体芯片倒装芯片连接至弯曲引线（参见日本特开专利公开号11-340373）。还知道的是对各种形状的引线（半导体芯片与其进行倒装芯片连接）的使用（参见日本特开专利号7-130918、2003-258187、2005-252018和2005-311099）。
FET（场效应晶体管）芯片在其上表面上具有焊盘，用于连接至源极、漏极和栅极。FET芯片与引线的倒装芯片连接在相邻端子之间仅具有短距离，而具有FET的半导体器件可能会出故障。可能会想到使用经受弯曲处理的引线以增大端子间距离。但是，该引线有可能经受不住大量电流，而半导体器件的可靠性会变差。
当FET芯片倒装芯片连接到引线时，在进行连接时可能会发生诸如孔隙（void）等连接故障，半导体器件的可靠性因此变差。
发明内容
为克服现有技术的缺陷，根据本发明的一个方案，提供一种半导体器件包括：FET芯片；多个焊盘，设置在所述FET芯片上；凸块，设置在至少一个所述焊盘上；引线，包括通过凸块连接到所述FET芯片并且沿所述FET芯片的上表面延伸的第一部分，以及与沿所述FET芯片的上表面的所述第一部分的表面接触并且沿所述FET芯片侧面延伸的第二部分，所述第一部分和第二部分通过压制或切割而形成；以及密封层，密封所述FET芯片和所述引线，并且密封暴露所述引线的第二部分的表面，所述密封层的表面位于所述FET芯片的下表面上。
本发明公开的半导体器件能够提高器件的可靠性。
通过权利要求中指出的元件和组合实现并获得本发明的目的和优点。
附图说明
图1A至图1D分别是根据第一至第四对比示例的半导体器件的剖视图；
图2是从其上表面看时根据第五对比示例的半导体器件的平面图；
图3A是从其上表面看时根据第一实施例的半导体器件的平面图，并且图3B是沿图3A中线A-A的剖视图；
图4A是FET芯片的俯视图，并且图4B是由虚线包围的一部分区域的放大俯视图；
图5A和图5B是示出制作引线框架的方法的剖视图，并且图5C和5D是示出制作引线框架的方法的俯视图；
图6是示出根据图5A至图5D的步骤制作引线框架的方法的俯视图；
图7A至图7D是示出制造半导体器件的方法的剖视图；
图8是根据第六对比示例的半导体器件的剖视图；
图9A是从其上表面看时根据第一实施例的第一变型的半导体器件的平面图，并且图9B是沿图9A中的线A-A的剖视图；
图10A是根据第二示例的半导体器件的俯视图，图10B是该半导体器件的仰视图，并且图10C是沿图10B中线A-A的剖视图；
图11是示出制作引线框架的方法的剖视图；
图12A至图12D是示出制造半导体器件的方法的剖视图。
图13是由第二实施例的两个堆叠的半导体器件组成的器件的剖视图；
图14A是根据第二实施例的第一变型的半导体器件的俯视图，图14B是该半导体器件的仰视图，并且图14C是沿图14A中线A-A的剖视图；
图15是由第二实施例的第一变型的两个堆叠的半导体器件组成的器件剖视图；以及
图16A是根据第二实施例的第一变型的半导体器件的俯视图，以及图16B是沿图16A中线A-A的剖视图。
具体实施方式
现在对对比示例进行描述。图1A是根据第一对比示例的半导体器件的剖视图。图1B是根据第二对比示例的半导体器件的剖视图。如图1A和图1B所示，安装在由金属制成的散热板101上的FET芯片102通过导线104电连接到引线106。使用封装层108封装FET芯片102和导线104。
因为导线104的大电感，以导线接合方式进行的FET芯片102与引线106的连接会影响FET芯片102的高速运行。如果FET芯片102是诸如高电子迁移率晶体管（HEMT）等高速运行器件，这种副作用尤为显著。因此可能会想到不使用任何导线进行FET芯片102与引线106的倒装芯片连接。
图1C是根据第三对比示例的半导体器件的剖视图。如图1C所示，FET芯片102通过凸块110倒装芯片连接到引线106。第三对比示例不使用任何引线而是通过凸块110连接引线106，从而能够抑制电感。FET芯片102是在同一表面（例如上表面）上具有分别与源极、漏极和栅极连接的源极焊盘、漏极焊盘和栅极焊盘的结构。该结构不利地导致与源极焊盘连接的引线106的端子和与漏极焊盘连接的引线106的端子之间的短距离X。例如端子间距离X短至1mm至2mm。短距离X会导致FET芯片102发生故障。当FET芯片102是以高电压运行的器件（例如使用GaN基半导体器件的HEMT芯片等）时，FET芯片102很可能会发生故障。所述GaN基半导体器件是包括GaN的半导体器件。
图1D是根据第四对比示例的半导体器件的剖视图。如图1D所示，引线106已经经受了弯曲处理并且具有大的端子间距离X。然而，引线106具有减少的剖面，这会增大电流密度。结果是，引线106经受不住大量的电流，而半导体器件的可靠性降低。
由于FET芯片102被源极焊盘、漏极焊盘和栅极焊盘占据的面积很大，在进行倒装芯片连接时可能会发生接合故障。图2是从其上表面看时根据第五对比示例的半导体器件的平面图。当FET芯片102的整个源极焊盘通过焊料112与源极的引线106a连接时，因为源极焊盘的面积大，在界面处可能会出现孔隙114。相似地，当FET芯片102的整个漏极焊盘通过焊料112与漏极的引线106b连接时，因为漏极焊盘的面积大，在界面处会出现孔隙114。如果FET芯片102的栅极焊盘的面积小，可能会抑制在与栅极的引线106c的界面处的孔隙的出现。如上所述，诸如在FET芯片102的焊盘与引线之间的界面处的孔隙等的连接故障使半导体器件的可靠性变差。
现在描述旨在提高半导体器件的可靠性的实施例。
第一实施例
图3A是从其上表面看时根据第一实施例的半导体器件的平面图，并且图3B是沿图3A中线A-A的剖视图。如图3A和图3B所示，第一实施例的半导体器件200具有FET芯片10，其利用凸块40倒装芯片连接到引线42a至引线42c。FET芯片10例如是使用GaN基半导体器件的HEMT芯片。凸块40例如是焊料凸块。引线42a至引线42c由诸如铜等金属形成。
现在对FET芯片10作进一步的描述。图4A是FET芯片的俯视图，并且图4B是由虚线包围的一部分区域18的放大俯视图。参考图4A和图4B，FET芯片10在上表面11上具有源极焊盘12、漏极焊盘和栅极焊盘16。被曲线包围的并且介于源极焊盘12与漏极焊盘14之间的区域18是FET芯片10的晶体管部分。FET芯片10的晶体管部分包括梳齿（comb-tooth）结构的聚集（aggregate），每一个FET芯片10的晶体管部分具有让栅极24介于源极20和漏极22之间的布局。源极互连线26（多个源极20与其连接）电连接到源极焊盘12。类似地，漏极互连线28（多个漏极22与其连接）电连接到漏极焊盘14。栅极互连线30（多个栅极24与其连接）电连接到栅极焊盘16。如上所述，FET芯片10具有一个晶体管部分，并且在FET芯片10的上表面上的焊盘电连接到所述晶体管部分。栅极互连线30跨过漏极22的部分具有三维结构，其中绝缘件（未示出）设置在栅极互连线30与漏电极22之间，两者相互电绝缘。
如图3A和图3B所示，FET芯片10的上表面11上的源极焊盘12通过多个凸块40连接到引线42a。FET芯片10的上表面11上的漏极焊盘14通过多个凸块40连接到引线42b，并且上表面11上的栅极焊盘16通过多个凸块40连接到引线42c。多个凸块40被提供给FET芯片10的上表面11上的源极焊盘12、漏极焊盘14和栅极焊盘16中的每一个。例如，多个凸块40以等间隔规则地排列成行和列。
引线42a至引线42C中的每一个具有第一部分44和第二部分46。第一部分44沿FET芯片10的上表面11延伸。第二部分46与沿FET芯片10的上表面11的所述第一部分44的表面41接触并且沿FET芯片10的侧面延伸。也就是说引线42a至引线42C中的每一个具有L形剖面。凸块40与第一部分44连接。第一部分44的侧面44a和第二部分46的侧面46a形成一单个表面。第一部分44和第二部分46例如是长方体。因此引线42a至引线42C的拐角是直角。例如，第一部分44的厚度T是0.25mm，并且第二部分46的宽度W1是0.5mm。如上所述，第一部分44的厚度T和第二部分46的宽度W1具有彼此不同的值，并且宽度W1大于厚度T。FET芯片10设置在引线42a与引线42b之间和引线42a与引线42c之间，以使得FET芯片10被引线42a至引线42c包围或夹在中间。
FET芯片10和引线42a至引线42c被密封层48密封。密封层48例如由诸如环氧树脂等树脂制成。从密封层48暴露FET芯片10的下表面15以提高散热性能。在FET芯片10的下表面15这一侧，从密封层48暴露引线42a至引线42c的第二部分46，以使第二部分46起到用于使FET芯片10与外部电路之间电连接的端子的作用。FET芯片10的下表面15与从密封层48暴露的第二部分46的表面43齐平。在FET芯片10的相反侧的位置从密封层48暴露引线42a的与FET芯片10的源极焊盘12电连接的第二部分46以及引线42b的与漏极焊盘14连接的第二部分46。例如，引线42a与引线42b之间的端子间距离X是6mm。
下部参考图5A至图5D、图6和图7A至图7D描述根据第一实施例的制造半导体器件的方法。首先，参考图5A至图5D和图6的制作引线框架的方法。图5A至图5B是示出制作引线框架的方法的剖视图，并且图5C、图5D和图6是示出制作引线框架的方法的俯视图。图5A是沿图5C中线A-A的剖视图，并且图5B是沿图5D中线A-A的剖视图。
如图5A和图5C所示，制备诸如铜板等金属板50。金属板50包括条形部以及交替重复设置的沟槽部分52和凸棱（bank）部分54。可以通过压制或切割金属板得到金属板50。例如，金属板50在沟槽部分52中具有0.25mm的厚度，在凸棱部分54中具有0.5mm的厚度。然后金属板50被电镀上金属。电镀可以在金属板50的整个表面或仅在限定的部分进行，所述限定部分可以是条状的凸棱部分54。
如图5B和图5D所示，通过使用模具压制来处理金属板50以限定引线42a至引线42c并且形成多个剪切（cutout）图案56（其中金属板50被去除）。更具体地，压制加工使用具有图案的模具，该图案由第一部分44（用于从长方形中去除引线42a至引线42c）的形状形成（参见图3A和图3B）。例如，形成剪切图案56以使得其在金属板50中排列成行和列。压制模具使得从长方形中去除的部分（也就是与引线42a至引线42c对应的部分）将沟槽部分52和凸棱部分54连接在一起。剪切图案56限定从沟槽部分52延伸至凸棱部分54的引线42a至引线42c。由沟槽部分52和凸棱部分54形成的步骤造成由剪切图案56限定的引线42a至引线42c包括平坦的第一部分44以及第二部分46。第二部分46与第一部分44接触并且沿第二部分46与第一部分交叉的方向延伸。可以通过切割取代压制而形成剪切图案56。
如图6所示，在预定位置切割金属板50。该切割将金属板板50分割成多个区域，每个区域包括多个引线42a至引线42c。每个区域是一个引线框架38。每个引线框架58具有其上可安装FET芯片10的多个区域。
参考图7A至图7D描述制造半导体器件的方法，该半导体器件使用图5A至图5D和图6示出的方法制作引线框架58。图7A至图7D示出制造半导体器件的方法的剖视图。注意，为了清楚起见，图7A至图7D仅描述一个半导体器件。参考图7A，在FET芯片10的上表面11上的每个源极焊盘12、漏极焊盘14和栅极焊盘16（未示出）上形成多个凸块40。所述凸块40例如是焊料凸块。
参考图7B，在FET芯片10的上表面11上的焊盘上的凸块40连接至由各剪切图案56限定的引线42a至引线42c（引线42c未示出）。更具体地，引线42a至引线42c的第一部分44（也就是沟槽部分52）与凸块40连接。这样，FET芯片10设置在引线42a与引线42b之间和引线42a与引线42c之间以使其被引线42a至引线42c包围。优选提前调整沟槽52和凸棱部分54的高度，使得FET芯片10的下表面15与凸棱部分54齐平。
参考图7C，通过切割将金属板50分割成单个芯片。由于剪切图案56排列成行和列，很容易通过切割金属板50而从多个FET芯片10得到单个芯片。切割之后，减压膜（relief film）60被粘附于FET芯片10的下表面15和位于FET芯片10的下表面15一侧的引线42a至引线42c的表面43，由此模塑制成（molded）FET芯片10和引线42a至引线42c。通过该模塑方法，形成用于密封FET芯片10和引线42a至引线42c的密封层48。例如，密封层48是诸如环氧树脂等树脂。
如图7D所示，去除减压膜60。从密封层48暴露FET芯片10的下表面15和引线42a至引线42c的表面。图7D示出第一实施例的封装半导体器件200。
根据第一实施例，如图3B所示，引线42a至引线42c中的每一个具有沿FET芯片10的上表面11延伸的第一部分44，以及与沿FET芯片10的上表面的第一部分44的表面41接触并且沿FET芯片10的侧面13延伸的第二部分46。使用密封层48密封引线42a至引线42c，并且为了使引线42a至引线42c具有起到外部端子作用的第二部分46，密封层48从FET芯片10的下表面15一侧暴露引线42a至引线42c。使用这种结构，在FET芯片10插入其间的位置中，从密封层48暴露与源极焊盘12电连接的引线42a的第二部分46和与漏极焊盘14电连接的引线42b的第二部分46。因此可以提高引线42a与引线42b之间的端子间距离X1，并提高半导体器件的可靠性。
如图3A和图3B所示，为FET芯片10的源极焊盘12、漏极焊盘14和栅极焊盘16中的每一个提供多个凸块40。FET芯片通过多个凸块40与引线42a至引线42c连接。该结构实现了具有小面积的凸块40并且避免了参考图2描述过的孔隙的发生。进而，使用多个凸块40消除（relax）了施加到一个凸块40的应力。因而可以抑制FET芯片10和引线42a至引线42c的接合故障的发生，并提高了半导体器件的可靠性。
如图5A和图5C所示，第一实施例的制造方法使用呈条形的沟槽部分52和凸棱部分54的金属板50。如图5B和图5D所示，通过压制或切割在金属板50中形成用于限定引线42a至引线42c并从沟槽部分52延伸至凸棱部分54的剪切图案56。如图7B所示，设置在FET芯片10的上表面11上的源极焊盘12、漏极焊盘14和栅极焊盘16中的每一个上的凸块40与由剪切图案56限定的引线42a至引线42c的沟槽部分52连接。如图7C和7D所示，通过切割将金属板50分割成单个的FET芯片10，并且密封FET芯片10和引线42a至引线42c，使得FET芯片10的下表面15一侧的引线42a至引线42c的表面43被暴露。
使用上述步骤，可以容易地制造具有通过凸块40与引线42a至引线42c连接的FET芯片10的半导体器件，引线42a至引线42c中的每一个具有沿FET芯片10的上表面11延伸的第一部分44和沿侧面13延伸的第二部分。进而，根据上述的制造方法，通过压制或切割形成引线42a至引线42c。也就是说，通过压制或切割在金属板50中形成限定引线42a至引线42c并且从沟槽部分52延伸至凸棱部分54的剪切图案56，金属板50被切割。通过上述步骤，形成引线42a至引线42c。
图8是根据第六对比示例的半导体器件的剖视图。如图8所示，如果通过弯曲（bending）形成沿FET芯片102的上表面103和侧面105延伸的引线106，使用大剖面的厚导线会导致在拐角120处的大曲率半径，并且在减少半导体器件的尺寸方面具有困难。与此相反，基于减小拐角120处的曲率半径的目的而使用细导线使得剖面得以减小，并增大了电流密度。在通过弯曲形成引线106的情况下，沿FET芯片102的上表面103的第一部分106的厚度等于沿侧面的第二部分118的宽度。
反之，根据第一实施例，通过压制或切割形成引线42a至引线42c。因此可以获得拐角处的小曲率半径和大的剖面的引线42a至引线42c。因此可以减少半导体器件的尺寸并且减小电流密度以提高半导体器件的可靠性。使用压制或切割形成引线42a至引线42c使得可以任意选择第一部分44的厚度T和第二部分46的宽度W1，并且将T和W1设定为不同值。因此，提高了引线42a至引线42c的设计自由度。
第一实施例的制造方法能够容易地形成分别连接至源极焊盘12、漏极焊盘14和栅极焊盘16并且互相之间电绝缘的引线42a至引线42c。
优选剪切图案56在金属板50中排列成行和列。优选FET芯片10通过凸块40连接至由各剪切图案56限定的引线42a至引线42c的沟槽部分52。优选地，在剪切图案56的外围部分（outer portions）中，金属板50被切割成单个FET芯片10。因此可以简化半导体器件的制造工艺并且减少制作成本。
在上述第一实施例中，第一部分44的厚度T与第二部分46的宽度W1不同。第一实施例具有另一示例性结构，其中T等于W1。考虑到对施加到凸块40的应力的消除，优选凸块40排列成行和列，并且互相之间以等间距间隔开。
图9A是从其上表面看时根据第一实施例的第一变型的半导体器件的平面图，并且图9B是沿图9A中的线A-A的剖视图。参考这些图形，半导体器件250使用分离的焊料层作为设置在源极焊盘12和漏极焊盘12的每一个上的凸块40。凸块40可以通过在源极焊盘12和漏极焊盘12的整个表面上形成焊料层并且通过蚀刻或类似方法将焊料层分割成多个部分。由于栅极焊盘16具有比较小的面积，仅有一个凸块40设置在栅极焊盘16上。但是也可以在栅极焊盘16上设置多个凸块40。第一变型的其他结构与第一实施例的半导体器件200的结构相同，这里省略对其的描述。
第一实施例的第一变型能够抑制FET芯片10与焊盘之间的连接界面处出现孔隙，并消除每个凸块40的应力。因此第一变型具有高可靠性。
第二实施例
图10A是根据第二示例的半导体器件的俯视图，图10B是该半导体器件的仰视图，并且图10C是沿图10B中线A-A的剖视图。参考这些图形，第二实施例的半导体器件300具有与第一实施例的半导体器件200的引线42a至引线42c的形状不同的引线72a至引线72c。引线72a至引线72c中的每一个具有第一部分74、第二部分76和第三部分78。第一部分74沿FET芯片10的上表面11延伸。第二部分76沿FET芯片10的上表面11而与第一部分74的表面71接触并且沿FET芯片10的侧面13延伸。第三部分78与表面73接触，该表面73与沿FET芯片10的上表面11的第一部分74的表面71相对，并且沿远离表面73的方向（向上）延伸。第二部分76和第三部分78位于第一部分74的相对侧。第三部分78具有宽度W2，对其的测量与第一部分74的厚度T不同。第三部分78的宽度W2大于第一部分74的厚度T。第二部分76的宽度W1与第一部分74的厚度T不同，并且大于T，就像第一实施例的情形那样。从密封层48暴露第二部分76和第三部分78。也就是说，引线72a至引线72c穿透密封层48。第二实施例的其他结构与第一实施例的半导体器件200的结构相同，这里省略对其的描述。
参考图11和图12A至图12D，对根据第二实施例的制造半导体器件的方法加以描述。首先，参考图11描述制造引线框架的方法。图11是示出制作引线框架的方法的剖视图。制备金属板70。金属板70具有其中交替地重复设置条形的沟槽部分52和凸棱部分54的表面和其中形成有与凸棱部分的侧面匹配的突起（protrusion）66的相对表面。通过对平板金属板施加应力或切割形成金属板70。之后执行与参考图5A至图5D和图6已经描述过的步骤相同的步骤，由此得到引线框架，该引线框架被分割成多个区域，每个区域具有多个引线72a至72c。
参考图12A至图12D，对制造具有上述引线框架的半导体器件的方法加以描述。图12A至图12D是示出制造半导体器件的方法的剖视图。为清楚起见，图12A至图12D仅示出一个半导体器件。如图12A所示，在FET芯片10的上表面11上的每个源极焊盘12、漏极焊盘14和栅极焊盘16（未示出）上形成多个凸块40。
如图12B所示，在FET芯片10的上表面11上的凸块40与由各剪切图案限定的引线72a至72c连接（引线72c未示出）。更具体地，凸块40与引线72a至72c的第一部分74（也就是沟槽部分52）连接。因此，FET芯片10设置在引线72a与引线72b之间和引线72a与引线72c之间，使得其被引线72a至引线72c包围。
如图12C所示，通过切割将金属板50分割成单个FET芯片10。在切割工艺之后，将减压膜60粘附于FET芯片10的下表面15和FET芯片10的下表面15一侧的引线72a至引线72c的表面。之后，对FET芯片10和引线42a至引线42c进行模塑。该模塑方法形成用于密封FET芯片10和引线72a至引线72c的密封层48。
如图12D所示，去除减压膜60。这样，从密封层48暴露FET芯片10的下表面15和引线72a至引线72c的表面77，该表面77与FET芯片10的下表面15一侧的表面75相对。图12D示出第二实施例的封装后的半导体器件300。
在第二实施例的半导体器件300中，引线72a至引线72c穿透密封层48，并且从FET芯片10的下表面15上的引线72a至引线72c的表面和其相对表面暴露。因此，可以将多个半导体器件300加以堆叠，之间形成有电性互连。图13是第二实施例的由两个堆叠的半导体器件组成的器件的剖视图。参考图13，使用焊料64将下部半导体器件300a的引线72a至引线72c的第三部分78与上部半导体器件300b的引线72a至引线72c的第三部分76连接。因此，半导体器件300a和半导体器件300b电性互连并且垂直堆叠。该堆叠不限于两个半导体器件，类似地，可将三个或更多的半导体器件进行堆叠。
根据第二实施例，如图10C所示，引线72a至引线72c中的每一个包括第一部分74、第二部分76和第三部分78。第一部分74连接到设置在FET芯片10的上表面11上的焊盘上的凸块40，并且沿FET芯片10的上表面延伸。第二部分76与沿FET芯片10的上表面11的第一部分74的表面71接触并且沿FET芯片10的侧面13延伸。第三部分78与表面73接触（该表面73与沿FET芯片10的上表面11的第一部分74的表面71相对），并且沿远离表面73的方向（向上）延伸。使用上述结构，引线72a至引线72c穿透密封层48，并且从FET芯片10的下表面15一侧的表面和其相对面暴露。因此，如图13所示，得到堆叠的半导体器件，其中下部半导体器件300a的引线72a至引线72c的第三部分78与上部半导体器件300b的引线72a至引线72c的第二部分76连接。由于引线72a至引线72c穿透密封层48而暴露，堆叠的半导体器件的组件具有降低的导通（ON）电阻。结果是，半导体器件的热辐射得以抑制，并且半导体器件的可靠性得以提高。
如图10C所示，优选引线72a至引线72c中的每一个的第三部分78通过第一部分74面对第二部分76，并且沿第二部分76的虚构的延伸线延伸。因此可以扩大引线72a的第三部分78和引线72b的第三部分78之间的距离X2，并且提高半导体器件的可靠性。
图14A是根据第二实施例的第一变型的半导体器件的俯视图，图14B是该半导体器件的仰视图，并且图14C是沿图14B中线A-A的剖视图。参考这些图形，第二实施例的第一变型的半导体器件400具有突起电极68，其从密封层48突起并且设置在引线72a至引线72c的第三部分上。在图14A的左一侧的突起电极68设置在引线72a的第三部分78上，在右下侧的突起电极68设置在引线72b的第三部分78上，并且在右上侧的突起电极68设置在引线72c的第三部分78上。该半导体器件的其他结构与第二实施例的半导体器件300的相同，这里省略对其的描述。
图15是由第二实施例的第一变型的两个堆叠的半导体器件组成的半导体器件的剖视图。如图15所示，设置在下部的半导体器件400a的引线72a至引线72c的第三部分78上的突起电极68通过使用焊料64连接到上部半导体器件400b的引线72a至引线72c的第二部分76。突起电极68在半导体器件400a和400b之间产生大于图13中示出的半导体器件300a和300b之间间隔的间隔。上述堆叠不限于两个半导体器件，类似地,可将三个或更多的半导体器件进行堆叠。
根据第二实施例的第一变型，如图14C所示。在引线72a至引线72c的第三部分78上设置突起电极68。与图13中的半导体器件300a和300b之间的间隔相比，在图15中，突起电极68实现扩大的半导体器件400a和400b之间的间隔。可以使用较大量的焊料65来接合半导体器件400a和400b，且更能有效地产生自对准效应。因此，半导体器件400a和400b可以更容易地互相对准。
从减少堆叠的半导体器件的组件的尺寸的角度出发，在待要堆叠的半导体器件的易于自对准的效应得以产生时，突起电极68的高度优选等于或大于150μm，更优选地等于或大于175μm，并且进一步优选地等于或大于200μm。为了产生自对准效应，突起电极68的高度等于或小于300μm，更优选地等于或小于250μm，并且进一步优选地等于或小于200μm。
当制造引线72a至引线72c时，可以与引线72a至引线72c整体形成突起电极68。另一种方法使用在引线72a至引线72c上沉积的焊料。在这种情况下，例如，由于引线72a至引线72c的第三部分78从密封层48暴露，可以使用焊料印刷来形成焊料凸起电极68以使其具有长方形形状。
图16A是根据第二实施例的第一变型的半导体器件的俯视图，而图16B是该半导体器件的仰视图，并且图16C是沿图16A中线A-A的剖视图。如图16A和图16B所示，第二实施例的第二变型的半导体器件500具有引线82a至引线82c，且所述引线82a至引线82c具有从密封层48暴露的圆形部分，而突起电极68设置在暴露的圆形部分上。图16A左侧的四个突起电极68设置在引线82a上，图16A右下侧的三个突起电极68设置在引线82b上，并且在右上侧的一个突起电极68设置在引线82c上。第二变型的其他结构与第一变型的半导体器件400的结构相同，这里省略对其的描述。
根据第二实施例的第二变型，引线82a至引线82c呈圆形形式暴露，并且突起电极68设置在暴露的引线82a至引线82c的圆形部分上。如果突起电极68由焊料形成，焊料球被设置在从密封层48暴露的引线82a至引线82c的圆形部分上，因此可以容易地在多个预定位置中形成突起电极。
在第一和第二实施例中，在源极焊盘12、漏极焊盘14和栅极焊盘16中的每一个上设置多个凸块40。但是，本发明不限于上述描述。例如，考虑到凸块的尺寸，在至少每一个焊盘上设置至少两个凸块40。例如，如果半导体器件具有源极焊盘、漏极焊盘和栅极焊盘，多个凸块优选设置在源极焊盘或漏极焊盘中的至少一个上。
FET芯片10不限于使用GaN基半导体的HEMT，也可以是其它类型的FET芯片。例如，FET芯片10是使用GaAs基半导体（包括GaAs的半导体）的HEMT，或者是除了HEMT之外的诸如MESFET和MOSFET等FET芯片。注意，使用GaN基半导体的HEMT芯片能够以高电压运行并且需要具有高的击穿电压。因此，尤其当FET芯片10是使用GaN基半导体的HEMT芯片时，会产生巨大的效果。凸块40不限于焊料凸块，还可以是由诸如金（Au）凸块和铜（Cu）凸块等其它材料制成的凸块。

Claims (11)

1.一种半导体器件，包括：
场效应晶体管（FET）芯片；
多个焊盘，设置在所述FET芯片上；
凸块，设置在至少一个所述焊盘上；
引线，包括通过凸块连接到所述FET芯片并且沿所述FET芯片的上表面延伸的第一部分，以及与沿所述FET芯片的上表面的所述第一部分的表面接触并且沿所述FET芯片的侧面延伸的第二部分，所述第一部分和第二部分通过压制或切割而形成；以及
密封层，密封所述FET芯片和所述引线，并且密封所述引线的暴露所述第二部分的表面，所述密封层的表面位于所述FET芯片的下表面上。
2.根据权利要求1所述的半导体器件，其中所测量的所述引线的第一部分的厚度不同于所述第二部分的宽度。
3.根据权利要求1或2所述的半导体器件，其中在所述FET芯片插入其间的位置中，从密封层暴露与源极焊盘即所述多个焊盘之一连接的一个所述引线的第二部分和与漏极焊盘即所述多个焊盘之另一连接的一个所述引线的第二部分。
4.根据权利要求1或2所述的半导体器件，其中所述FET芯片是使用GaN基半导体的高电子迁移率晶体管芯片。
5.根据权利要求1所述的半导体器件，其中所述引线具有第三部分，针对沿所述FET芯片的上表面的所述第一部分的表面而言，所述第三部分与所述第一部分的相对表面接触，并且在远离所述相对表面的方向上延伸，所述第三部分从所述密封层暴露。
6.根据权利要求5所述的半导体器件，还包括设置在从所述密封层暴露的所述引线的第三部分上的突起电极。
7.一种半导体器件，包括第一半导体器件和第二半导体器件，每一个半导体器件是根据权利要求5或6所述的半导体器件，其中所述第一半导体器件和第二半导体器件具有堆叠结构，在该堆叠结构中所述引线的第三部分或者所述第一半导体器件的突起电极连接到所述第二半导体器件的引线的第二部分。
8.一种制造半导体器件的方法，包括：
制备金属板，包括排列成条形的沟槽部分和凸棱部分；
在所述金属板中通过压制或切割形成剪切图案，该剪切图案限定从所述沟槽部分延伸至所述凸棱部分的引线；
将设置在每个场效应晶体管（FET）芯片的上表面上的焊盘上的凸块连接到由所述剪切图案限定的引线的沟槽部分，所述凸块中的至少两个凸块设置在至少一个所述焊盘上，
通过切割将所述金属板分割成单个的FET芯片；以及
形成密封所述单个FET芯片和所述引线的密封层，使得沿所述单个芯片下表面的所述引线的表面暴露。
9.根据权利要求8所述的方法，其中
形成所述剪切图案是在所述金属板中形成排列成行和列的所述剪切图案；以及
连接所述凸块是将设置在所述FET芯片的上表面上的焊盘的凸块连接至由所述剪切图案限定的引线的沟槽部分。
10.一种制作引线的方法，包括：
金属板包括排列成条形的沟槽部分和凸棱部分；
在所述金属板中通过压制或切割形成剪切图案，所述剪切图案限定从所述沟槽部分延伸至所述凸棱部分的引线；以及
在形成所述剪切图案之后切割所述金属板。
11.一种引线，包括：
第一部分，连接至场效应晶体管（FET）芯片的上表面上的焊盘上的凸块，并且沿所述FET芯片的上表面延伸；
第二部分，与沿所述FET芯片的上表面的所述第一部分的表面接触，并且沿所述FET芯片的侧面延伸；以及
第三部分，针对沿所述FET芯片的上表面的所述第一部分的表面而言，所述第三部分与所述第一部分的相对表面接触，并且在远离所述相对表面的方向上延伸。
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