CN104821303A - 连接器框架以及半导体装置 - Google Patents
连接器框架以及半导体装置 Download PDFInfo
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- CN104821303A CN104821303A CN201410302823.XA CN201410302823A CN104821303A CN 104821303 A CN104821303 A CN 104821303A CN 201410302823 A CN201410302823 A CN 201410302823A CN 104821303 A CN104821303 A CN 104821303A
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- connector
- lead frame
- composition surface
- electrode
- lead
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Abstract
本发明涉及连接器框架以及半导体装置。连接器框架具备框架部、从所述框架部突出并一体地设置于所述框架部的第1连接器、以及从所述框架部突出并一体地设置于所述框架部的第2连接器。所述第1连接器具有第1部分、和设置于所述第1部分与所述框架部之间且比所述第1部分薄的第2部分。所述第2连接器的厚度与所述第1连接器的所述第2部分相同。
Description
关联申请
本申请享受以日本专利申请2014-17327号(申请日:2014年1月31日)为基础申请的优先权。本申请通过参照该基础申请而包括基础申请的全部内容。
技术领域
实施方式涉及连接器框架以及半导体装置。
背景技术
近年来,在功率半导体装置中,为了低电阻化,作为芯片和外部引线的连接构造,提出了不使用引线结合,而使用了铜等的板状的连接器或者连接带(strap)的构造,这样的产品也越来越多。
另外,提出了使在芯片上搭载的连接器从树脂露出,并从安装基板侧的封装下表面和封装上表面这两个表面进行散热的构造。根据散热性这一点,优选从封装上表面露出的部分较厚。另外,在连接器中向引线侧延伸出而与引线连接的部分不位于芯片正上方,所以对散热没有那么多贡献,无需变厚,是与现有的引线框架相同程度的厚度即可。另外,与源极连接器等相比而流过的电流更小的栅极连接器变厚的必要性也低。
发明内容
本发明提供一种材料效率良好的连接器框架以及半导体装置。
根据实施方式,连接器框架具备框架部、从所述框架部突出并与所述框架部一体地设置的第1连接器、以及从所述框架部突出并与所述框架部一体地设置的第2连接器。所述第1连接器具有第1部分、设置于所述第1部分与所述框架部之间且比所述第1部分薄的第2部分。所述第2连接器的厚度与所述第1连接器的所述第2部分相同。
附图说明
图1是实施方式的半导体装置的示意剖面图。
图2A以及B是实施方式的半导体装置的示意顶视图。
图3A以及B是半导体芯片的示意俯视图。
图4是实施方式的连接器框架的示意俯视图。
图5A是实施方式的第1连接器以及第2连接器的示意俯视图,图5B是第1连接器的示意剖面图,图5C是第2连接器的示意剖面图。
图6A是形成有实施方式的连接器框架的金属板的示意俯视图,图6B是金属板的示意剖面图。
图7是另一种实施方式的半导体装置的示意剖面图。
图8A是另一种实施方式的第1连接器以及第2连接器的示意俯视图,图8B是第1连接器的示意剖面图,图8C是第2连接器的示意剖面图。
图9是另一种实施方式的半导体装置的示意剖面图。
图10A是另一种实施方式的第1连接器以及第2连接器的示意俯视图,图10B是第1连接器的示意剖面图,图10C是第2连接器的示意剖面图。
图11是另一种实施方式的半导体装置的示意顶视图。
具体实施方式
以下,参照附图,说明实施方式。另外,在各附图中,对相同的要素附加了相同的符号。
图1是实施方式的半导体装置1的示意剖面图。
图2A是实施方式的半导体装置1的示意顶视图,图2B是去掉了树脂80的示意顶视图。在图2B中,关于树脂80,仅图示了侧面的外形线。
实施方式的半导体装置1具有半导体芯片10、与半导体芯片10电连接的引线框架21、31、41、第1连接器50、第2连接器70、以及对这些要素进行密封的树脂80。
半导体芯片10是在半导体层中的一个面侧设置的第1电极与在另一个面侧设置的第2电极之间进行连接的、在纵向上形成了电流路径的纵向器件。半导体芯片10是例如纵向MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor,金属-氧化物-半导体场效应晶体管)。或者,半导体芯片10是纵向IGBT(InsulatedGate Bipolar Transistor,绝缘栅双极型晶体管)、纵向二极管。
作为半导体而使用硅。或者,也可以使用硅以外的半导体(例如SiC、GaN等化合物半导体)。
图3A是半导体芯片10的第1面12的示意俯视图,图3B是第1面12的相反侧的第2面14的示意俯视图。
如图3A所示,在半导体层11的第1面12形成有第1电极13。例如在MOSFET中,第1电极13是漏电极。第1电极13占据第1面12的大部分地形成。
如图3B所示,在半导体层11的第2面14,第2电极15和第3电极16相互绝缘分离地形成。第2电极15占据第2面14的大部分地形成,在例如MOSFET中是源电极。第3电极16的面积小于第2电极15的面积,在例如MOSFET中是栅电极。
如图2B所示,第1引线框架21具有管芯焊盘22、和多根引线23。管芯焊盘22的平面形状形成为四边形形状,多根引线23从它的一边突出。第1引线框架21通过金属板的模具加工成形,管芯焊盘22以及引线23一体地设置。
在第1引线框架21的引线23的突出方向的相反侧,相对第1引线框架21隔开间隔地设置有第2引线框架31。
第2引线框架31具有在第1引线框架21侧设置的内部引线32、和从内部引线32突出了的多根外部引线33。外部引线33向第1引线框架21的引线23的突出方向的反方向突出。内部引线32在相对于外部引线33的突出方向以及第1引线框架21的引线23的突出方向正交的方向上延伸。
第2引线框架31通过金属板的模具加工成形,内部引线32以及外部引线33一体地设置。
另外,在第1引线框架21的引线23的突出方向的相反侧,也相对第1引线框架21隔开间隔地设置有第3引线框架41。第3引线框架41设置于第2引线框架31的内部引线32的长度方向的旁边。第3引线框架41相对第2引线框架31有间隔。
第3引线框架41具有在第1引线框架21侧设置的内部引线42、和从内部引线42突出了的1个外部引线43。外部引线43向与第2引线框架31的外部引线33的突出方向相同的方向突出。
如图1所示,在第1引线框架21的引线23与管芯焊盘22之间未形成阶梯,引线23的上表面与管芯焊盘22的上表面平面地连接,引线23的下表面与管芯焊盘22的下表面平面地连接。
第2引线框架31在内部引线32与外部引线33之间的部分处弯曲,在内部引线32与外部引线33之间形成有阶梯。第3引线框架41也与第2引线框架31同样地,在内部引线42与外部引线43之间的部分处弯曲,在内部引线42与外部引线43之间形成有阶梯。
第2引线框架31的外部引线33的下表面处于与第1引线框架21的下表面(引线23的下表面以及管芯焊盘22的下表面)相同的高度水平。第3引线框架41的外部引线43的下表面处于与第1引线框架21的下表面、以及第2引线框架31的外部引线33的下表面相同的高度水平。
以外部引线33、43的下表面以及第1引线框架21的下表面作为高度方向(上下方向)的基准,内部引线32、42的上表面相比管芯焊盘22的上表面位于上方。
半导体芯片10搭载于第1引线框架21的管芯焊盘22上。关于半导体芯片10,使形成有第1电极13的第1面12朝向管芯焊盘22侧。
第1电极13经由图1所示的导电性接合材料(例如,焊锡)25与管芯焊盘22接合。因此,半导体芯片10的第1电极13与第1引线框架21电连接。
在半导体芯片10的第2面14上,搭载有第1连接器(在MOSFET中为源极连接器)50。第1连接器50具有第1部分51和第2部分52。关于第1部分51和第2部分52,厚度相对不同,第1部分51比第2部分52更厚。
第1连接器50通过后面叙述的图6A所示的金属板100的冲剪加工成形,第1部分51以及第2部分52一体地设置。第1连接器50由例如电传导以及热传导优良的铜构成。另外,作为第1连接器50,也可以使用以铜为主成分的铜合金。
第1部分51比各引线框架21、31、41的厚度更厚,例如,为大于等于0.5mm且小于等于1mm。第1部分51具有经由例如焊锡等导电性接合材料55与半导体芯片10的第2电极15接合了的第1接合面54。另外,第1部分51具有形成于第1接合面54的相反侧并从树脂80露出了的散热面53。
第2部分52从第1部分51向第2引线框架31侧突出。第2部分52的前端部重叠于第2引线框架31的内部引线32上,经由例如焊锡等导电性接合材料35与内部引线32的上表面接合。
因此,第1连接器50将半导体芯片10的第2电极15与第2引线框架31电连接。
另外,如图2B所示,半导体芯片10的第3电极(栅电极)16和第3引线框架41通过第2连接器(在MOSFET中为栅极连接器)70电连接。
第2连接器70的一端部71经由例如焊锡等导电性接合材料与第3电极16接合。第2连接器70的另一端部72重叠于第3引线框架41的内部引线42上,经由例如焊锡等导电性接合材料与第3引线框架41的内部引线42的上表面接合。
第2连接器70通过后面叙述的图6A所示的金属板100的冲剪加工,与第1连接器50同时成形。因此,第2连接器50由与第1连接器50相同的材料、例如铜或者铜合金构成。
另外,第2连接器70的厚度是与第1连接器50的第2部分52的厚度相同。即,如后面所述,使用金属板100中的相对薄的部分,形成了第2连接器70和第1连接器50的第2部分52。该金属板100中的相对厚的部分成为第1连接器50的第1部分51。
另外,作为上述导电性接合材料,不限于焊锡,也可以使用例如銀膏那样的导电性膏。
半导体芯片10被树脂密封,被保护不受外部环境影响。树脂80覆盖了半导体芯片10、管芯焊盘22的上表面、第2引线框架31的内部引线32、第3引线框架41的内部引线42、第1连接器50的第1部分51的侧面、第1连接器50的第2部分52、第2连接器70。
另外,树脂80覆盖了第1电极13和管芯焊盘22的接合部、第2电极15和第1连接器50的接合部、第1连接器50的第2部分52和第2引线框架31的内部引线32的接合部、第3电极16和第2连接器70的接合部、第2连接器70和第3引线框架41的内部引线42的接合部。
第1引线框架21的下表面(引线23的下表面以及管芯焊盘22的下表面)、第2引线框架31的外部引线33的下表面、以及第3引线框架41的外部引线43的下表面未被树脂80覆盖,而从树脂80露出。
这些第1引线框架21的下表面、第2引线框架31的外部引线33的下表面、以及第3引线框架41的外部引线43的下表面针对未图示的安装基板(布线基板)的导体图案经由例如焊锡而接合。
另外,如图1、图2A所示,第1连接器50的第1部分51的上表面从树脂80露出,作为散热面53发挥功能。还能够在第1连接器50的散热面53上,根据需要接合散热器。
在半导体芯片10中产生的热通过面积比第1电极13宽的管芯焊盘22被散热到安装基板,并且通过第1连接器50的散热面53被散热到半导体装置1的外部(例如空气中)。即,实施方式的半导体装置1具有两面散热封装构造,特别在芯片发热量容易变大的电力用途的情况下,能够提高散热性。
不仅是半导体芯片10和第2引线框架31之间的电连接,第1连接器50的第1部分51还作为承担向安装面的相反方向的散热的散热体发挥功能。该第1连接器50的第1部分51搭载于半导体芯片10的正上方,第2电极15和第1部分51的接合面的面积与半导体芯片10的第2电极15的面积的比是大于等于80%。另外,第1连接器50的散热面53的面积与半导体芯片10的第2电极15的面积的比是大于等于100%。
即,第2电极15的大部分的表面被用作向第1连接器50的热传导面,传导到第1连接器50的热从大于等于第2电极15的面积的散热面53被散热到半导体装置1的外部。因此,能够将第1连接器50有效地用作散热体,散热效率优良。
关于第1连接器50,不是使整体变厚,而是通过设置比第1部分51薄的第2部分52,设置了从第1连接器50的上表面侧由树脂80覆盖的区域。即,在第2部分52中,树脂80覆盖了第1连接器50的上表面。第2部分52为深入到树脂80的构造。因此,相比于使第1连接器50的上表面的全部从树脂80露出的构造,能够抑制树脂80的剥离(第1连接器50的脱落)。
第1连接器50具有一体地设置了厚度相对不同的第1部分51和第2部分52的构造。另外,与第3电极(栅电极)16连接的第2连接器(栅极连接器)70不作为从树脂80露出的散热体发挥功能,并且,相比于与第2电极(源电极)15连接的第1连接器(源极连接器)50,流过的电流更小。因此,关于第2连接器70的厚度,未要求厚到还作为散热体发挥功能的第1连接器50的第1部分51的程度。如果使第2连接器70变厚到所需以上,则导致材料成本上升。
此处,作为比较例,可以举出由不同的金属板制作第1连接器50和第2连接器70的方法。即,第1连接器50利用具有作为第1部分51的厚的部分和作为第2部分52的薄的部分的异形金属板来制作,第2连接器70像一般的引线框架那样能够利用均匀的厚度的金属板来制作。
但是,在该情况下,使用第1连接器50用的金属板和第2连接器70用的金属板这2种金属板,所以材料效率不良。另外,第1连接器50和第2连接器70形成于不同的框架中,所以第1连接器50的安装和第2连接器70的安装也必须分别实施。
因此,根据实施方式,通过研究第1连接器50和第2连接器70的布局,利用相同的金属板同时使第1连接器50和第2连接器70成形。
图4是成形有实施方式的第1连接器50以及第2连接器70的连接器框架90的示意俯视图。
第1连接器50以及第2连接器70一体地设置于框架部91。框架部91在第1方向(X方向)上延伸。第1连接器50以及第2连接器70在相对第1方向(X方向)正交的第2方向(Y方向)上,从框架部91突出。
在X方向上等间距地排列了多个第1连接器50,在X方向上等间距地排列了多个第2连接器70。第1连接器50与第2连接器70的间隔(X方向间隔以及Y方向间隔)恒定。
框架部91、第1连接器50的第2部分52、以及第2连接器70是相同的厚度,第1连接器50的第2部分52和第2连接器70直接设置于框架部91。
第1连接器50的第1部分51在与框架部91之间,在Y方向上夹着第2部分52以及第2连接器70而定位。
在图5A中,放大示出图4中的1个第1连接器50以及1个第2连接器70。
另外,图5B是图5A所示的第1连接器50的沿着Y方向的剖面图,图5C是图5A所示的第2连接器70的沿着Y方向的剖面图。
第1连接器50以及第2连接器70在图5A~C中在如双点划线所示的位置被切断,从框架部91分离。
连接器框架90是通过使用模具对图6A所示的金属板100进行冲剪加工而制作的。图6B示出图6A所示的金属板100的沿着Y方向的剖面。图6A以及B表示通过压延加工形成有厚的部分101以及比其薄的薄的部分102的条形状的金属板100中的一部分。
金属板100是例如铜板或者铜合金的板。首先,将均匀的厚度的金属板100用辊压延的同时,将它做成条(带形状)。此时,对希望变薄的部分,放上对局部进行挤压那样的辊而使其变薄。将这样的工序反复多次,而成形为期望的形状。
之后,对金属板100进行冲剪加工,在图6A中如虚线所示,第1连接器50以及第2连接器70被成形。金属板100中的厚的部分101的一部分作为第1连接器50的第1部分51残留,金属板100中的薄的部分102的一部分作为第1连接器50的第2部分52以及第2连接器70残留。
根据以上说明了的实施方式,利用相同的金属板100制作第1连接器50以及第2连接器70,所以相比于利用不同的金属板来制作它们,材料效率更优良。
另外,在连接器框架90的状态下,使第1连接器50的第2部分52与第2连接器70的X方向间距、以及第1连接器50的第1部分51与第2连接器70的Y方向间距与实际上安装到半导体芯片10、框架31、41时的间距相同。
因此,在将第1连接器50和第2连接器70分别切离之前的连接器框架90的状态下,能够将第1连接器50和第2连接器70同时安装到半导体芯片10、框架31、41,生产效率提高。
另外,第1连接器50的第1部分51的第2部分52侧的端、与第2连接器70的突出方向的前端之间的距离t大于等于0.2mm。
在对金属板100进行冲剪加工时,在厚的部分101与薄的部分102的边界处,形状、尺寸的精度容易降低。因此,根据实施方式,以使第2连接器70的前端位于从金属板100中的厚的部分101和薄的部分102的边界隔开大于等于0.2mm的距离t的位置的方式,对金属板100进行冲剪。由此,能够抑制与第2连接器70中的第3电极16接合的前端部的变形、尺寸精度降低。
另外,在作为第2连接器70的薄的部分102的前端部,如图6B、图5C所示,以使厚的部分103少量残留的方式实施冲剪。向其下方突出,而将厚的部分103用于与第3电极(栅电极)16的接合。因此,不会使第2连接器70弯曲,而能够使它的一端部71的下部103与第3电极16接合。针对小的第2连接器70的弯曲加工有时困难,但在实施方式中也可以不进行该弯曲加工。
图7是另一种实施方式的半导体装置的示意剖面图。
如图7所示,第2部分52的前端部的下表面(第2接合面)52a重叠于第2引线框架31的内部引线32上。在第1连接器50的第2部分52中,在第2接合面52a与下表面52c之间设置了第1阶梯部52b。
在第2引线框架31的内部引线32的上表面32a隔着接合材料35承载了第1连接器50的第2接合面52a的状态下,熔融接合材料35。此时,第2引线框架31的内部引线32的端部碰撞到第1阶梯部52b的侧面,由此第1连接器50的在图7中横向上的位置偏移被限制。第1连接器50的位置偏移的抑制提高经由第1连接器50将半导体芯片10与第2引线框架31之间电连接的可靠性。
在图7所示的实施方式中,也与上述实施方式同样地,利用相同的金属板同时使第1连接器50和第2连接器70成形,所以相比于利用不同的金属板制作第1连接器50以及第2连接器70,材料效率更优良。
图8A是将成形有图7所示的实施方式的半导体装置中的第1连接器50以及第2连接器70的连接器框架放大了的示意俯视图。另外,图8B是图8A所示的第1连接器50的沿着Y方向的剖面图,图8C是图8A所示的第2连接器70的沿着Y方向的剖面图。
如图8A以及图8B所示,第1阶梯部52b在例如相对第2部分52的突出方向正交的方向上连续地延伸。
如图8A以及图8C所示,在第2连接器70的另一端部72侧的下表面,设置了与图2B所示的第3引线框架41的内部引线42接合的第3接合面70a。
第2连接器70与第1连接器50同时形成。因此,在第2连接器70中的第3接合面70a与下表面70c之间,也设置了与第1连接器50的第1阶梯部52b同样的第2阶梯部70b。第2阶梯部70b在例如相对第2连接器70的突出方向正交的方向上连续地延伸。
由此,第3引线框架41的内部引线42的端部碰撞到第2阶梯部70b的侧面,由此与第1连接器50同样地,第2连接器70的位置偏移被限制。第2连接器70的位置偏移的抑制提高经由第2连接器70将半导体芯片10与第3引线框架41之间电连接的可靠性。
图9是又一种实施方式的半导体装置的示意剖面图。
在第1连接器50的第2部分52的下表面,作为朝向第2部分52的上表面侧凹陷的第1凹部,设置了第1槽部61。
图10A是将成形有图9中的第1连接器50以及第2连接器70的连接器框架放大了的示意俯视图。另外,图10B是图10A所示的第1连接器50的沿着Y方向的剖面图,图10C是图10A所示的第2连接器70的沿着Y方向的剖面图。
如图10A以及图10B所示,第1槽部61在例如相对第2部分52的突出方向正交的方向上连续地延伸。
如图10A以及图10C所示,在第2连接器70的下表面,设置了与图2B所示的第3引线框架41的内部引线42接合的第3接合面70a、作为朝向第2连接器70的上表面凹陷的第2凹部的第2槽部73。第2槽部73在例如相对第2连接器70的突出方向正交的方向上连续地延伸。
在图9、10A~C所示的实施方式中,第2连接器70也与第1连接器50同时形成。因此,第1连接器50的第1槽部61、和第2连接器70的第2槽部73同时形成。
图11是在图9的半导体装置中将树脂80去掉了的示意顶视图。在图11中,关于树脂80,仅图示了侧面的外形线。
比第2接合面52a更靠近第1部分51侧,与第2接合面52a接近地设置了第1连接器50的第1槽部61。第1槽部61未重叠于第2引线框架31的内部引线32的上表面32a上,比内部引线32更靠近第1引线框架21侧地形成。
比第3接合面70a更靠近一端部71侧,与第3接合面70a接近地设置了第2连接器70的第2槽部73。第2槽部73未重叠于第3引线框架41的内部引线42的上表面42a上,比内部引线42更靠近第1引线框架21侧地形成。
通过形成第1槽部61以及第2槽部73,在接合材料35被熔融时,得到自对准的效果。
即,通过与第1连接器50的第2接合面52a接近地形成第1槽部61,限制了第2接合面52a的宽度(Y方向上的宽度)。
通过该第1槽部61,抑制了熔融的接合材料35在第1连接器50的第2部分52的下表面蔓延到第1部分51侧。因此,第2部分52的Y方向上的位置偏移被抑制。
相对第2引线框架31的第2部分52的位置偏移的抑制能够抑制第1连接器50整体的位置偏移,还抑制相对半导体芯片10的第1部分51的位置偏移。
同样地,通过与第2连接器70的第3接合面70a接近地形成第2槽部73,限制了第3接合面70a的宽度(Y方向上的宽度)。
通过该第2槽部73,抑制了熔融的接合材料在第2连接器70的下表面蔓延。因此,第2连接器70的Y方向上的位置偏移被抑制。
另外,如图11所示,如果在第1连接器50的第2接合面52a和第2引线框架31的内部引线32的上表面32a处,使第2部分52的突出方向(Y方向)上的宽度a相同,则熔融了的接合材料35不会超过该宽度a而在宽度方向上扩展,第1连接器50的第2部分52没有在宽度方向上偏移的余地。
通过形成上述第1槽部61,能够简单地使第2接合面52a的宽度与第2引线框架31的上表面32a的宽度一致。
进而,如果在第2接合面52a和第2引线框架31的内部引线32的上表面32a处,使相对第2部分52的突出方向正交的方向上的长度b相同,则熔融了的接合材料35不会超过该长度b而在长度方向上扩展,第1连接器50的第2部分52没有在长度方向上偏移的余地。
虽然说明了本发明的几个实施方式,但这些实施方式仅作为例子而提出,并不旨在限定发明的范围。这些新的实施方式能够通过其他各种方式实施,在不脱离发明的主旨的范围内,能够进行各种省略、置换、变更。这些实施方式、实施方式的变形包含于发明的范围、主旨内,并且包含于权利要求书记载的发明和其均等范围内。
Claims (15)
1.一种连接器框架,其特征在于,具备:
框架部;
第1连接器,从所述框架部突出而一体地设置于所述框架部,且具有第1部分、和设置于所述第1部分与所述框架部之间且比所述第1部分薄的第2部分;以及
第2连接器,从所述框架部突出而一体地设置于所述框架部,厚度与所述第1连接器的所述第2部分相同。
2.根据权利要求1所述的连接器框架,其特征在于,
所述第1连接器的所述第1部分的所述第2部分侧的端、与所述第2连接器的突出方向的前端之间的距离大于等于0.2mm。
3.根据权利要求1所述的连接器框架,其特征在于,
所述框架部在第1方向上延伸,
所述第1连接器以及所述第2连接器向与所述第1方向正交的第2方向突出,
在所述第1方向上等间距地排列了多个所述第1连接器,在所述第1方向上等间距地排列了多个所述第2连接器。
4.根据权利要求1所述的连接器框架,其特征在于,
所述框架部的厚度与所述第1连接器的所述第2部分的厚度、以及所述第2连接器的厚度相同。
5.根据权利要求1所述的连接器框架,其特征在于,
所述连接器框架包含铜。
6.一种半导体装置,其特征在于,具备:
第1引线框架;
第2引线框架,相对所述第1引线框架隔开间隔地设置;
第3引线框架,相对所述第1引线框架以及所述第2引线框架隔开间隔地设置;
半导体芯片,设置于所述第1引线框架上,且具备具有第1面和与所述第1面相对的第2面的半导体层、设置于所述第1面并与所述第1引线框架接合了的第1电极、设置于所述第2面的第2电极、以及设置于所述第2面的第3电极;
树脂,对所述半导体芯片进行密封;
第1连接器;以及
第2连接器,
所述第1连接器具有:
第1部分,设置于所述半导体芯片的所述第2面上并与所述第2电极接合,且具有与所述半导体芯片的所述第2电极接合的第1接合面、和与所述第1接合面相对并从所述树脂露出了的散热面;以及
第2部分,通过与所述第1部分相同的材料而与所述第1部分一体地设置,从所述第1部分向所述第2引线框架侧突出,比所述第1部分薄,与所述第2引线框架接合,
所述第2连接器连接所述半导体芯片的所述第3电极和所述第3引线框架,且由与所述第1连接器相同的材料构成,厚度与所述第2部分相同。
7.根据权利要求6所述的半导体装置,其特征在于,
所述第1连接器以及所述第2连接器包含铜。
8.根据权利要求6所述的半导体装置,其特征在于,
所述散热面的面积与所述第2电极的面积的比大于等于100%。
9.根据权利要求6所述的半导体装置,其特征在于,
所述第2部分被所述树脂覆盖。
10.根据权利要求6所述的半导体装置,其特征在于,
所述第1部分的厚度是大于等于0.5毫米且小于等于1毫米。
11.根据权利要求6所述的半导体装置,其特征在于,
所述第1连接器的所述第2部分具有:
第2接合面,重叠于所述第2引线框架上;以及
第1阶梯部,比所述第2接合面更靠近所述第1部分一侧,与所述第2接合面接近地设置,
所述第2连接器具有:
第3接合面,重叠于所述第3引线框架上;以及
第2阶梯部,与所述第3接合面接近地设置。
12.根据权利要求11所述的半导体装置,其特征在于,
在所述第2部分中的与所述第2接合面接近的下表面设置了第1凹部,在所述第1凹部与所述第2接合面之间设置了所述第1阶梯部,
在所述第2连接器中的与所述第3接合面接近的下表面设置了第2凹部,在所述第2凹部与所述第3接合面之间设置了所述第2阶梯部。
13.根据权利要求11所述的半导体装置,其特征在于,
所述第1连接器的所述第2接合面、和与所述第2接合面接合了的所述第2引线框架的上表面的、所述第2部分的突出方向的宽度相同。
14.根据权利要求11所述的半导体装置,其特征在于,
所述第1连接器的所述第2接合面、和与所述第2接合面接合了的所述第2引线框架的上表面的、与所述第2部分的突出方向正交的方向上的长度相同。
15.根据权利要求12所述的半导体装置,其特征在于,
所述第1凹部以及所述第2凹部是在与所述第2部分的突出方向正交的方向上延伸的槽。
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JP2016062904A (ja) * | 2014-09-12 | 2016-04-25 | 株式会社東芝 | 半導体装置 |
JP6558772B2 (ja) * | 2015-10-07 | 2019-08-14 | 新電元工業株式会社 | 接続部材切り離し装置、切断金型、接続部材切り離し方法及び電子デバイスの製造方法 |
JP6695156B2 (ja) * | 2016-02-02 | 2020-05-20 | エイブリック株式会社 | 樹脂封止型半導体装置 |
JP2018113315A (ja) * | 2017-01-11 | 2018-07-19 | Shプレシジョン株式会社 | リードフレームの製造方法、およびリードフレーム |
US10727151B2 (en) * | 2017-05-25 | 2020-07-28 | Infineon Technologies Ag | Semiconductor chip package having a cooling surface and method of manufacturing a semiconductor package |
WO2019082346A1 (ja) * | 2017-10-26 | 2019-05-02 | 新電元工業株式会社 | 半導体装置、及び、半導体装置の製造方法 |
JP7281267B2 (ja) * | 2017-11-06 | 2023-05-25 | ローム株式会社 | 半導体装置、半導体装置の製造方法 |
WO2019092839A1 (ja) | 2017-11-10 | 2019-05-16 | 新電元工業株式会社 | 電子モジュール |
CN111295751B (zh) * | 2017-11-10 | 2023-09-15 | 新电元工业株式会社 | 电子模块 |
US11239127B2 (en) * | 2020-06-19 | 2022-02-01 | Infineon Technologies Ag | Topside-cooled semiconductor package with molded standoff |
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