CN103972170A - 半导体器件及其生产方法 - Google Patents

半导体器件及其生产方法 Download PDF

Info

Publication number
CN103972170A
CN103972170A CN201410043965.9A CN201410043965A CN103972170A CN 103972170 A CN103972170 A CN 103972170A CN 201410043965 A CN201410043965 A CN 201410043965A CN 103972170 A CN103972170 A CN 103972170A
Authority
CN
China
Prior art keywords
chip
wafer
interarea
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410043965.9A
Other languages
English (en)
Other versions
CN103972170B (zh
Inventor
J·科租比
M·莱度特克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of CN103972170A publication Critical patent/CN103972170A/zh
Application granted granted Critical
Publication of CN103972170B publication Critical patent/CN103972170B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02697—Forming conducting materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Dicing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种方法，包括将增强晶片应用于半导体晶片，由此形成复合晶片。该方法还包括分割复合晶片，由此生成多个复合芯片，每个复合芯片包括半导体芯片和增强芯片。

Description

半导体器件及其生产方法
技术领域
本发明涉及半导体器件及其制造方法，并且更具体地涉及处理薄半导体晶片或薄半导体芯片的技术。
背景技术
半导体器件制造商不断努力在降低制造其产品的成本的同时提升其产品的性能。半导体器件制造中的一个成本高的领域在于封装半导体芯片。如本领域技术人员所知，集成电路是在晶片上制作的，晶片随后被单片化（singulated）以生产半导体芯片。由于半导体芯片变得越来越薄，越来越需要能够处理薄半导体晶片或薄半导体芯片。随后，这些薄半导体芯片可以安装在诸如引线框架之类的导电载体上。这些薄半导体芯片还可以用在人工晶片中。希望的是封装方法以低费用提供高产率。
出于这些和其它原因，存在对本发明的需要。
发明内容
根据实施例，提供了一种方法，包括：将增强晶片应用于半导体晶片，由此形成复合晶片；以及分割复合晶片，由此生成多个复合芯片，每个复合芯片包括半导体芯片和增强芯片。
根据实施例，提供了一种复合晶片，包括：半导体晶片，包括第一主面和第二主面；以及增强晶片，被附接到半导体晶片的第一主面，其中半导体晶片具有小于40μm的厚度。
根据实施例，提供了一种复合芯片，包括：半导体芯片，包括第一主面和第二主面；以及增强芯片，被附接到半导体芯片的第一主面，其中半导体芯片具有小于40μm的厚度。
根据实施例，提供了一种方法，包括：提供具有第一主面和第二主面的基板；将半导体芯片附接到基板的第一主面；以及通过向基板的第一主面上沉积金属层来嵌入半导体芯片。
根据实施例，提供了一种半导体器件，包括：基板，具有第一主面和第二主面；半导体芯片，被附接到基板的第一主面；以及金属层，被沉积到基板的第一主面上，由此嵌入半导体芯片。
附图说明
附图被包括用于提供对实施例的进一步的理解，并且被并入并且构成本说明的一部分。附图示出实施例，并且连同说明书一起用于解释实施例的原理。随着它们通过参考以下详细描述而变得更好理解，其它实施例和实施例的许多预期优点将容易明白。
图1A-1C示意性地示出制造半导体器件的方法的一个实施例的截面图；
图2A-2B示意性地示出制造半导体器件的方法的一个实施例的截面图；
图3A-3J示意性地示出制造半导体器件的方法的一个实施例的截面图；
图4A-4F示意性地示出制造半导体器件的方法的一个实施例的截面图；
图5A-5F示意性地示出制造半导体器件的方法的一个实施例的截面图；以及
图6A-6D示意性地示出嵌入半导体芯片的方法的一个实施例的截面图。
具体实施方式
本发明的方面和实施例参考附图描述，其中通篇类似的附图标号通常用于指代类似的元件。在以下描述中，为了解释的目的，阐述大量细节以便提供对实施例的一个或多个方面的彻底理解。然而，对于本领域技术人员可以是显而易见的是可以用较小程度的具体细节来实施实施例。在其它实例中，以示意的形式示出了已知的结构和元件，以便有助于描述实施例的一个或多个方面。因此以下描述不应被视为限制性的，并且保护范围由所附权利要求限定。还应注意到，图中各种芯片、层、载体或基板的表示未必按比例绘制。
在以下细节描述中，对附图进行引用，其形成附图的一部分，并且其中以说明方式示出了本发明可以在其中被实践的具体实施例。就此而言，方向术语，诸如“顶”、“底”、“左”、“右”、“上”、“下”等是参照被描述附图的定向来使用的。因为实施例的部件可以以许多不同的定向来放置，所以方向术语用意在于说明而绝不是限制。应理解，在不偏离本发明的范围的情况下可以利用其它实施例和结构并且可以做出逻辑上的改变。因此，以下具体实施方式不应被视为限制性的，并且本发明的保护范围由所附权利要求限定。
应理解，本文描述的各种示例实施例的特征可以彼此组合，除非特别指出或者除非受技术所限。
如在本说明中所采用的，术语“接合”、“附接”或“连接”并不意味着是指元件必须直接彼此接触在一起；可以在“接合的”、“附接的”或“连接的”元件之间提供居间元件或层。
进一步在下文中描述的半导体芯片可以是不同类型的，可以通过不同技术制造，并且可以包括例如集成的电子、光电或机电电路和/或无源件。
半导体芯片可以包括诸如逻辑集成电路、控制电路、微处理器、存储器设备等之类的集成电路。
具体而言，可以涉及到具有垂直结构的半导体芯片，也就是说可以按电流可以在垂直于半导体芯片的主面的方向上流动这样的方式来制作半导体芯片。具有垂直结构的半导体芯片在其两个主面上具有垂直结构，也就是说在其顶侧和背侧上（背侧在本文中又称作背面）。
半导体芯片例如可以是功率半导体芯片。功率半导体芯片可以具有垂直结构。（一个或多个）垂直功率半导体芯片可以例如被配置为功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）、JFET（结栅场效应晶体管）、功率双极晶体管或者功率二极管。作为示例，功率MOSFET的源极电极和栅极电极可以位于正面主面，而功率MOSFET的漏极电极被布置在背面主面上。
半导体芯片不需要从特定的半导体材料（例如Si、SiC、SiGe、GaAs）制造，并且可以包含不是半导体的无机的和/或有机的材料（诸如例如绝缘体、塑料或金属）。
本文中所考虑的（一个或多个）半导体芯片可以是薄的。为了允许处理或操纵半导体芯片，例如封装所需的处理/操纵、eWLP（嵌入式晶片级封装）或半导体器件组装，半导体芯片可以形成复合芯片的部分。复合芯片可以包括半导体芯片和被固定到半导体芯片的增强芯片。增强芯片为复合芯片增加稳定性和/或强度，以使其可控。
下文所述的器件可以包括一个或多个半导体芯片。作为示例，可以包括一个或多个半导体功率芯片。此外，器件中可以包括一个或多个逻辑集成电路。逻辑集成电路可以被配置用于控制其它半导体芯片的集成电路，例如功率半导体芯片的集成电路。逻辑集成电路可以在逻辑芯片中实现。
半导体芯片可以具有接触焊盘（或电极），其允许做出与半导体芯片中所包括的集成电路的电接触。电极可以都被布置在半导体芯片的仅一个主面处或者被布置在半导体芯片的两个主面处。电极可以包括被应用到半导体芯片的半导体材料的一个或多个电极金属层。电极金属层可以用任意希望的集合形状，和任意希望的材料组成来制造。例如，它们可以包括或者由选自以下项构成的组的材料制成：Cu、Ni、NiSn、Au、Ag、Pt、Pd和这些材料中的一个或多个材料的合金。
（一个或多个）半导体芯片可以被接合到载体。载体可以是用于封装的（永久性的）器件载体。载体可以例如从包括如下各项的组中选择：引线框架、诸如例如DCB（直接铜接合）陶瓷基板和印刷电路板（PCB）之类的陶瓷基板。
将半导体芯片接合到载体可以例如通过焊接、胶合或烧结来做出。在通过焊接来附接半导体芯片的情况下，可以使用软焊接材料或者具体而言使用能够形成扩散焊料接合的焊接材料，例如焊料材料包括从包括如下各项的组中选择的一种或多种金属材料：Sn、SnAg、SnAu、SnCu、In、InAg、InCu和InAu。
可以将半导体芯片嵌入在密封体中。密封体有时在本领域中被称为“人工晶片”或“模制重配置晶片”。在这种情况下，通过将密封体分为多个封装来生产半导体器件。将半导体芯片嵌入在密封体中被称作eWLP。
可以利用eWLP中所使用的密封体来生产扇出（fan-out）型封装。在扇出型封装中外部接触焊盘中的至少一些和/或将半导体芯片连接到外部接触焊盘的导线中的至少一些横向地位于半导体芯片的轮廓的外部或者横向地与半导体芯片的轮廓相交。因此，在扇出型封装中，半导体芯片的封装的外围外部部分通常(额外地)用于将封装电接合到外部应用，例如应用板等。包围半导体芯片封装的该外部部分有效地扩大了封装相对于半导体芯片的占用面积的接触面积，因而导致放松了关于以后的处理（例如二级组装）的、在封装焊盘尺寸和间距方面的约束。
（一个或多个）半导体芯片可以用密封材料覆盖，以便被嵌入在用于eWLP处理的密封体（人工晶片）中，或者在被接合到器件载体（基板）之后覆盖。密封材料可以是电绝缘的。密封材料可以包括或者由任何适当的塑料或聚合物材料（例如硬质塑料、热塑性或热硬性材料或者层压材料（预浸处理的）并且可以例如包含填充材料）制成。可以采用各种技术（例如包括压缩模制、注塑模制、粉末模制、液态模制或层压）以便用密封材料密封半导体芯片。可以使用热和/或压力以便应用封装材料。
图1A-1C示出根据一个实施例的制造多个复合芯片23，每个芯片包括半导体芯片24和增强芯片26的的方法。图1A示出提供具有第一主面12和第二主面14的半导体晶片10。半导体晶片10的第一主面12例如可以是半导体晶片10的背面或正面。反之也同样适用于半导体晶片10的第二主面14。
半导体晶片10可以例如具有小于40μm、30μm、20μm或10μm的厚度T1。半导体晶片10例如可以是具有圆形轮廓的盘形，并且半导体晶片10的横向尺寸（例如直径）可以例如等于或大于200或300mm。
如图1A所示的半导体晶片10可以在之前的步骤（图1A-1C中未示出）中已经被减薄以便具有厚度T1。经减薄的表面例如可以是半导体晶片10的第一主面12。在这种情况下，半导体晶片10的第二主面14可以在前端晶片处理过程中已经被处理以便生产有源结构诸如例如集成电路、pn晶体管、微机械结构等。处理第二主面14可以在减薄半导体晶片10的第一主面12的之前或之后进行。在这种情况下，半导体晶片10的第二主面可以是半导体晶片10的正面。如将在下文中更详细地进一步解释的，在这种情况下，例如可以使用eWLP处理以生产半导体器件。
还有可能，经减薄的表面例如可以是半导体晶片10的第二主面14。在这种情况下，半导体晶片10的第一主面12可以例如在减薄第二主面14之前或之后已经被处理。在这种情况下，半导体晶片10的第一主面12可以是半导体晶片10的正面。
减薄半导体晶片10可以包括从包括以下各项的组中选择的至少一个过程：机械减薄、具体而言是研磨、精磨（lapping）、化学机械剖光（CMP）以及湿法蚀刻。虽然研磨工具使用磨轮，但是精磨工具使用充有在两个表面之间作用的“滚动”磨蚀颗粒的流体（“浆”）。减薄半导体晶片10也可以包括前述过程中的多个过程或所有过程。
参照图1B，将增强晶片16应用在半导体晶片10上。增强晶片16可以是预先制作的部分，其例如通过胶合或其它结合技术而附接或粘合到半导体晶片10。或者在其它实施例中，增强晶片16可以是通过适当的层形成、层生长和/或材料沉积的过程而在半导体晶片10上形成、生长和/或沉积的层。
增强晶片16可以具有第一主面18和第二主面20。可以将增强晶片16的第二主面20应用在半导体晶片10的第一主面12的上面。
增强晶片16可以具有对应于半导体晶片10的横向尺寸的横向尺寸。更具体而言，增强晶片16可以完全地覆盖（例如第一主面12的）整个表面积或者半导体晶片10的至少大部分表面积，例如大于半导体晶片10的表面积的例如70%、80%、90%。增强晶片16可以例如具有可以比半导体晶片10的厚度T1大的厚度T2。作为示例，厚度T2可以例如大于40μm、30μm、20μm或10μm。在其它实施例中，增强晶片16可以例如具有比半导体晶片10的厚度T1小的厚度T2。例如，厚度T2可以例如小于40μm、30μm、20μm或10μm。厚度T2可以在增强晶片16的横向延伸上基本上保持恒定。
增强晶片16可以例如包括从包括如下各项的组中选择的材料或者由该材料制成：玻璃、树脂材料、铜、铜合金、模制材料（尤其是用于eWLP的模制材料），或者非晶硅。
通过将增强晶片16应用于半导体晶片10来形成复合晶片17。复合晶片17可以具有等于或大于半导体晶片10的厚度T1与增强晶片16的厚度T2的和的厚度。因为复合晶片17为复合晶片17增加了稳定性和/或强度，所以可以在后续的方法步骤中处理或操纵复合晶片17而由于半导体晶片10被增强晶片16增强而具有减小的半导体晶片10破碎或破裂的风险。另一方面，如果将后续的方法步骤单单应用于半导体晶片10，则将有半导体晶片10可能由于这里考虑的半导体晶片10的厚度较薄而破碎或破裂的风险。
例如，可以通过粘合或胶合，具体而言通过使用可释放的粘合剂或胶或者使用非可释放的粘合剂或胶，将预先制作的增强晶片16应用于半导体晶片10。如果使用可释放的粘合剂或胶（例如表现出热释放性能的粘合剂或胶），则在将复合晶片17划片为复合芯片之后，增强晶片16的芯片和半导体晶片10的芯片可以例如在后续的步骤中例如通过使用热处理来相互断开。另一方面，增强晶片16的芯片和半导体晶片10的芯片可以例如在所有进一步的制作步骤期间保持相连。作为示例，如果例如使用非可释放的粘合剂或胶，则增强晶片16的芯片和半导体晶片10的芯片可能不可相互分拆。
可以将增强晶片16例如应用于半导体晶片10的正面，参见例如图1-3的示例。可以将增强晶片16例如应用于半导体晶片10的背面，参见例如图1、图4和图5的示例。
可以在将增强晶片16应用于半导体晶片10之前或之后减薄半导体晶片10。在后者的情况下，减薄半导体晶片10的、不面向增强晶片16的第二主面14。此外，增强晶片16可以例如用作用于减薄过程的载体或者用于用于生成半导体晶片10的其它制造步骤的载体。
图1C示出分割，具体而言为将复合晶片17划片。将复合晶片17划片生成多个复合芯片23，每个符合芯片都包括半导体芯片24和增强芯片26和例如在半导体芯片24与增强芯片26之间的粘合剂（未示出）的。可以通过任何适当的技术（例如通过刀片分割（锯）、激光划片、蚀刻、切割等）来分割复合晶片17。尤其是可以例如应用隐形划片，其为使用激光划片的特定技术。可以例如沿在增强晶片16的第一主面18与半导体晶片10的第二主面14之间的截面线分割复合晶片17。截面线可以例如垂直于增强晶片16的第一主面18和半导体晶片10的第二主面14。
增强晶片16可以例如是透明的，这对于在分割期间对准复合晶片10以及/或者后续的芯片放置或安装过程是有利的。此外，可以将对准标记（未示出）应用于增强晶片16上，以协助分割复合晶片17和/或后续的芯片放置或安装过程。也就是说，对准标记可以例如用于将复合晶片17切割、划片、蚀刻等为复合芯片23并且/或者用于放置或安装复合芯片23。
可以沿着可以垂直于增强晶片16的第一主面18和半导体晶片10的第二主面14行进的划片截口（kerf）22来将复合晶片17划片。在图1C中，划片截口22也垂直于增强芯片16的第二主面20和半导体晶片10的第一主面12。每个划片截口22的宽度可以是T3，并且可以依赖于（例如对应于刀片宽度的）所使用的划片技术和设备。作为示例T3的量可以达到几十微米。
作为示例，可以通过将复合晶片17应用到胶带（tape）（尤其是划片胶带）上来将复合晶片17划片；例如根据一个或多个上述技术来将划片图案（特别是矩形图案）应用到复合晶片17；并且例如在胶带平面中沿正交方向拉胶带。通过拉胶带，复合晶片17被分割为多个复合芯片23。
复合芯片23的横向尺寸可以对应于相邻划片截口22之间的距离并且用T4表示。T4可以对应于半导体芯片的通常的长度或宽度尺寸，并且可以例如小于10mm、5mm或1mm。相邻复合芯片23的横向尺寸可以例如相同或不同。
增强芯片26为半导体芯片24增加稳定性和/或刚度和/或强度。这样，可以在后续步骤中处理或操纵复合芯片23并且因此半导体芯片24而有显著减小的、半导体芯片24破碎或破裂的风险。另一方面，如果将任何后续处理或操纵单单应用到半导体芯片24，则将有显著或高的、半导体芯片24由于半导体芯片24的厚度T1较薄而破碎或破裂的风险。
图2A-2C示出根据一个实施例的制造半导体器件100的一种方法。该方法是继续图1A-1C中示出的方法的各种可能性中的一个示例。这意味着，可以在图1C所示的步骤之后执行图2A中示出的方法步骤。然而，还有可能不同地处理复合芯片23，或者复合芯片23不再进一步进行处理或封装并且作为“裸片（bare dies）”向顾客装运。
图2A示出将复合芯片23附接（尤其是接合）到基板28。基板28可以具有第一主面30和第二主面32。基板28可以具有厚度T5。厚度T5是第一主面30与第二主面32之间的距离。T5可以依赖于基板的类型并且依赖于应用（例如低功率或高功率应用）。T5可以例如大于100微米或1mm。T5可以小于5mm或3mm。基板28例如可以是引线框架、诸如例如DCB（直接铜接合）陶瓷基板之类的陶瓷基板、印刷电路板（PCB）等。基板28可以例如形成用于半导体封装的（永久性的）器件载体。
在图2A中用复合芯片23的、面向基板28的半导体芯片24来将复合芯片23接合到基板28。这意味着，半导体芯片24的第二主面14被接合到基板28的第一主面30。接合可以例如通过胶合或焊接（尤其是扩散焊接）来完成。
图2B示出使复合芯片23的增强芯片26与复合芯片23的半导体芯片24分离。在使增强芯片26与半导体芯片24分离之后，所得的半导体芯片100包括基板28，该基板28具有被附接到基板28上面的半导体芯片24。使增强芯片26与半导体芯片24分离的步骤可以在将复合芯片23接合到衬底28期间或之后完成。在第一种情况下，这意味着在复合芯片正在被附接或接合到基板28的同时使增强芯片26与半导体芯片24分离。在后者的情况下，这意味着在复合芯片23已经被附接或接合到基板28之后使增强芯片26与半导体芯片24分离。
更具体而言，可以在单个过程（尤其是诸如例如热胶合处理或热焊接处理之类的单个热处理）内执行将复合芯片23接合到基板28并且使增强芯片26与半导体芯片24分离。在该单个过程中，复合芯片23与基板28机械地和光地、电地连接在一起，并且增强芯片26与半导体芯片24是断开的。
此外，可以通过第一处理（例如作为非热处理执行的胶合）将复合芯片23接合到基板28；并且可以例如通过例如可以是热处理的第二处理来执行使增强芯片26与半导体芯片24分离。在两种情况下，用于将增强晶片16固定到半导体晶片10的粘合剂或胶可以表现出热释放性质。
半导体器件100可以是包含一个或多个半导体芯片24的半导体封装。例如，半导体芯片24可以是功率半导体芯片，并且/或者基板28可以是包括充当器件载体的芯片焊盘和从当外部封装端子的引线的引线框架。功率半导体芯片（例如功率MOSFET）的源极电极24a和栅极电极24b可以位于第一主面12上，而功率半导体芯片24的漏极电极24c可以被布置在第二主面14上。此外，基板28（例如引线框架）和半导体芯片24可以被密封在由可以是电绝缘的密封材料制成的封装体（未示出）中。密封材料（未示出）可以是如上所述的任意材料，并且可以例如通过压缩模制、注塑模制、粉末模制、液态模制或层压来应用。
图3A-3H示出根据一个实施例的制造半导体器件200的示例性方法。该方法与在图1A-1C和图2A-2B中所述的方法相似，并且参照上文描述以避免重复。然而，一个差异可以是，其以批处理方式使用附接面板以便将多个复合芯片23附接到基板28。
图3A示出具有第一主面12和第二主面14的半导体晶片10。在图3A中描绘的半导体晶片10具有与图1A的半导体晶片10相同的特征。具体而言这适用于半导体晶片10的尺寸，以及例如减薄半导体晶片10。
图3B示出将增强晶片16应用于半导体晶片10，由此形成复合晶片17。应用在图3B中描述的增强晶片16和复合晶片17的过程可以具有与在结合图1B所描述的相同的特征。具体而言这可以适用于尺寸，例如适用于增强晶片16和半导体晶片10的尺寸、将增强晶片16应用到半导体晶片10的方法、增强晶片16相对于半导体晶片10的定向，以及增强晶片16的材料。
图3C示出将复合晶片17划片。在图3C中示出的方法步骤可以具有与在图1C中示出的方法步骤相似的特征，并且参照上文描述以避免重复。
在图3D中，将复合芯片23可释放地固定到附接面板34。附接面板34可以例如用于分批裸片附接过程。在图3D中粘合胶带40可以例如用于将复合芯片23固定到附接面板34。附接面板34可以具有第一主面36和第二主面38。粘合胶带40可以具有第一主面42和第二主面44。在图3D中附接面板34的第一主面36面向粘合胶带40的第二主面44。
作为示例，用面向附接面板34的增强芯片26来将复合芯片23附接到附接面板34。可以例如用永久性胶涂覆粘合胶带40的第一主面42。可以例如用可释放胶涂覆粘合胶带40的第二主面44。这就意味着粘合胶带40的第一主面42与复合芯片23之间的连接可能例如不容易被释放，并且粘合胶带40的第二主面44与附接面板34之间的连接可以例如被释放。
因此可以将粘合胶带40的第二主面44可释放地胶合在附接面板34的第一主面36的上面。将复合芯片23附接到附接面板34可以例如通过将复合芯片23放置在粘合胶带40的第一主面42上、其中增强芯片26面向粘合胶带40来完成。复合芯片23可以被放置在附接面板34上，分别地具有相对距离T6和T7。可以选择复合芯片23在附接面板34上的位置以对应于半导体芯片24在半导体器件200中的希望的位置。因此根据器件设计参数，T6和T7例如可以是不同的或者例如可以是相同的。
图3E示出将复合芯片23附接（尤其是接合）到基板28。这可以例如以批处理方式完成，这就意味着同时将多个复合芯片23附接（尤其是接合）到基板28。基板28的厚度可以例如对应于T5。如在图2A中，可以将复合芯片23接合到基板28的第一主面30。
图3E的基板28例如可以是前述类型中的一种。基板28可以包括多个部分28a、28b。部分28a、28b例如可以是岛部（insular）即不彼此互连的。作为示例，部分28a、28b可以表示被间隙29分离的引线框架28的芯片焊盘。
将复合芯片23附接（尤其是接合）到基板28的过程可以例如通过胶合或焊接（尤其是扩散焊接）来完成。参照上文描述以避免重复。在图3E中示出的过程可以例如在单个裸片附接过程步骤中完成。
图3F示出使复合芯片23的增强芯片26与复合芯片23的半导体芯片24分离。这可以例如在将复合芯片23附接（尤其是接合）到基板28期间或之后完成。在第一种情况下，如在图3E中示出的将复合芯片23附接到基板28并且如在图3F中示出的将增强芯片26从复合芯片23去除，可以在例如如上所述的单个热处理中完成。也就是说，应用热量可以一方面导致增强芯片26与半导体芯片24之间的连接断开，并且另一方面导致同时建立复合芯片23的半导体芯片24与基板28之间的连接。在第二种情况下，从复合芯片23去除增强芯片26可以在将复合芯片23附接（尤其是接合）到基板28之后的分离过程步骤中完成。在两种情况下，在裸片附接过程期间都由增强芯片26保护半导体芯片24。
从复合芯片23释放增强芯片26后，可以将粘合胶带40和固定到粘合胶带40的增强芯片26从附接面板34释放。然后可以重复使用附接面板34以用于如图3A至图3F所例示的其他过程。
作为示例，可以针对两种不同类型的半导体芯片，例如功率芯片和逻辑芯片来执行图3A-3E的方法步骤。然后可以将功率芯片和逻辑芯片如在图3D中所示地、互相紧邻地放置。也有可能将多个功率芯片和控制多个功率芯片的逻辑芯片互相紧邻地放置。作为示例而不失一般性地，用“P”标记的半导体芯片24可以是（一个或多个）功率芯片，并且用“L”标记的（一个或多个）半导体芯片24可以是（一个或多个）逻辑芯片。
虽然可以使用例如焊接来将功率芯片P附接到基板28，但是例如在单个步骤中通过胶合来将逻辑芯片L附接到基板28。虽然功率芯片P可能已经具有应用到其背面的焊料层，但是可以事先将胶合逻辑芯片L所必需的胶在相应位置应用在基板28上。如将在下文中更详细描述的，可以将如在图3F中所示的布置用于DC-DC转换器器件200。
作为优化的手段，图3G示出向基板28（例如引线框架）上沉积（尤其是电流（galvanically）沉积）金属（例如铜），以将半导体芯片24嵌入在沉积的金属中。通过向基板28上，具体而言在其如在图3G中描述的第一主面30上电流沉积金属而在基板28上生长金属层48。沉积的金属层48的厚度被称作T8。因为在半导体芯片24上没有生长金属，所以半导体芯片24的第二主面14与沉积的金属层48的外表面之间的距离将减小。
如在图3H中示出的，向基板28上生长（例如电流沉积）金属层48的过程可以例如持续直到半导体芯片24的、背离基板28的主表面与沉积的金属48的外表面彼此处于同一水平面上而例如在小于5μm、2μm、1μm或0.5μm的容差TOL之内。此外，半导体芯片24的、背离基板28的主表面与沉积的金属48的外表面可以例如是平齐的，即之间没有间隙。
如果将基板28加上电流沉积的金属层48考虑为新的基板，则可以说图3G的过程步骤可以减小半导体芯片24的、背离新基板的主表面与新基板的外表面之间的拓扑（topographic）差异，以形成用于进一步处理的共同的平面或平台。进一步处理可以包括薄膜处理，例如薄膜金属层生成或薄膜聚合物层生成、构造、过孔生成、层压、模制、或在封装技术中使用的其它处理步骤。
作为示例，根据图3I，基板28还可以包括部分28c和28d（未在前图中描述）。部分28c和28d可以是岛部，并且可以例如是基板28（例如引线框架）的端子部分。
作为示例，可以用绝缘材料填充在部分28a、28b、28c、28d之间的间隙。此外，所构造的绝缘层60（例如聚合物层）可以适用于有小拓扑差异的共同的平面，其凭借图3H的金属沉积步骤而可以被用作用于后续的处理步骤的建造平台。
作为示例，后续的处理可以包括生成电互连。在图3J中例示通过应用导电层70来生成电互连，其根据希望的信号和电流通路来构造。
作为示例，可以将部分28c连接到在左手边描述的第一功率芯片的源极，可以将部分28a连接到第一功率芯片的漏极并且连接到第二功率芯片的源极。可以将部分28b连接到第二功率芯片的漏极。定位于右方的逻辑芯片L可以具有电极24d，该电极24d被连接到功率芯片的栅极电极的并且被连接到部分28d。正如对于本领域技术人员显而易见的，如在图3I中示出的器件200可以表示DC-DC转换器。
此外，后续的处理可以包括应用密封材料80以保护器件200免受环境影响和例如建立绝缘外壳（envelope）。例如，可以使用层压或模制技术。
图4A-4G示出根据一个实施例的用于制造半导体器件300的方法。
图4A示出具有第一主面12和第二主面14的半导体晶片10。在图4A中描述的半导体晶片10可以具有与图1A或图3A的半导体晶片10相同的特征。参照对应的描述以避免重复。
图4B示出将增强晶片16应用在半导体晶片10上，由此形成复合晶片17。如在图4B中描述的复合晶片17具有与在图1B和图3B中描绘的复合晶片17相同的特征。参照对应的描述以避免重复。
图4C示出分割复合晶片17。在图4C中示出的方法步骤具有与在图1C或图3C中示出的方法步骤相同或相似的特征。参照对应的描述以避免重复。
图4D示出使用例如粘合胶带40来将经划片的复合芯片23可释放地附接到临时载体52。图4D的粘合胶带40可以具有与在图3D中示出的粘合胶带40相似的特征。然而，与图3D的粘合胶带40相比而言，可以用可释放的胶涂覆图4D的粘合胶带40的两侧。
临时载体52可以具有第一主面54和第二主面56。可以将粘合胶带40的第二主面放置到临时载体52的第一主面54上，以用于将粘合胶带40固定在临时载体52处。
可以例如通过使用抓放（pick and place）过程，来将经划片的复合芯片23放置在粘合胶带40的第一主面42的上面。可以将复合芯片23以间隔开的关系放置在粘合胶带40上，其中在相邻复合芯片23之间的横向距离例如可以是T9。图4D仅描绘放置在临时载体上的两个复合芯片23，然而可以有多于两个复合芯片23被附接到临时载体52。更具体而言，可以将例如数百个复合芯片23放置在临时载体52上，临时载体52例如可以是具有圆形轮廓的盘形，并且临时载体52的横向尺寸（例如直径）可以例如等于或大于200或300mm。
图4E示出将密封材料50应用于复合芯片23和临时载体52。通过将密封材料50应用到复合芯片23和临时载体52来生成人工晶片51。人工晶片51包括其中例如以正常图案嵌入有复合芯片23的密封体。人工晶片51例如可以是具有圆形轮廓的盘形，并且横向尺寸（例如人工晶片51的直径）可以例如等于或大于200或300mm。可以例如如上所述通过模制技术或者通过层压来制作嵌入有复合芯片23的密封体。
密封材料50例如可以是与上述密封材料80相同的材料。此外，增强晶片16的材料例如可以是与密封材料50相同的材料。还有可能为密封材料50和增强晶片16的材料选择不同的材料。然而，有利的是为密封材料50选择具有与增强芯片26的材料相似的CTE（热膨胀系数）的材料。
图4F示出从临时载体52释放人工晶片51。粘合胶带40可以例如表现出热释放的性质。在这一情况和其它情况下，可以使用热处理以便从粘合胶带40去除人工晶片51，并且例如从临时载体52去除粘合胶带40。
人工晶片51可以包括多个复合芯片23，每个符合芯片包括半导体芯片24和增强芯片26，其中将多个复合芯片23嵌入在形成密封体的密封材料50中。在人工晶片51的下面暴露复合芯片23的半导体芯片24。更具体而言，密封体的下表面和半导体芯片24的暴露面可以例如平齐并且可以例如彼此成水平。半导体芯片，无论是功率芯片、逻辑芯片或其它芯片都可以具有布置在暴露的芯片面的电极（未示出）。
然后人工晶片51可以经受进一步的eWLP步骤以在人工晶片51的下面形成例如电再分布结构（RDL）或者电互连（未示出）。具体而言，可以执行eWLB（嵌入式晶片级球栅阵列）封装过程，以生产BGA（球栅阵列）封装。
然后可以通过沿线C分割人工晶片51来将人工晶片51单片化为多个单个半导体器件300。半导体器件300可以是扇出型封装。
图5A-5G示出根据一个实施例的制造半导体器件400的示例性方法。该方法与在图4A-4F中所述的方法相似。然而，作为一个不同点，在将密封材料50应用于半导体芯片24和临时载体52之前去除增强芯片26。
图5A-5C示出与图4A-4C相同的制造方法的第一步骤，并且参照上文描述以便避免重复。然而，因为并非意在将增强芯片26集成到半导体器件400中，所以增强晶片16的材料的CTE可以与密封材料50的CTE不同，并且例如可以使用不同的材料。
然后，将复合芯片23可释放地固定到临时载体52。参照结合图4D的描述以避免重复。
图5D示出将增强芯片26从半导体芯片24去除。可以通过将能量（例如热量）应用于复合芯片23来协助去除增强芯片26的处理。在将增强芯片26从半导体芯片24去除的过程期间，不将半导体芯片24从临时载体52去除。
图5E和图5F示出在临时载体52上生成人工芯片51，以及相应地从临时载体52释放人工晶片51。图5E和图5F的方法步骤可以分别地具有与在图4E和4F中示出的方法步骤相同的性质。
然后人工晶片51可以经受进一步的如参照图4F描述的eWLP步骤，参照该描述。这样，例如可以在人工晶片51的下面形成电再分配结构、电互连（未示出）和/或焊料凸点。
图6A-6D示出通过向基板上电流沉积金属层来将半导体芯片24嵌入到在基板上沉积的金属内。
图6A示出提供可以具有第一主面30和第二主面32的基板28。图6A的基板可以具有与如前所述的基板28相同的特征。为了避免重复而参照上文描述。
图6B示出被附接到基板28的第一主面30的半导体芯片24。半导体芯片24可以包括第一主面12和第二主面14并且可以例如具有如上所述的厚度T1。当被放置在基板28上时，半导体芯片24可以例如包括在其主面14上的、背离基板28的增强芯片26。也就是说，可以将如上所述的复合芯片23放置在基板28上，并且可以在半导体芯片24已经附接（例如接合）到基板28后，将增强芯片26从半导体芯片24去除。同样参照上文描述以避免重复。
还有可能，可以利用除了使用增强芯片26之外的其它技术来操纵半导体芯片24并且将其放置在基板28上。具体而言，有可能在不使用增强芯片26的情况下将半导体芯片24放置并且接合在基板28上，并且因此没有将这样的增强芯片26从半导体芯片24释放的步骤。
图6C示出通过向基板28的第一主面30上沉积金属层来嵌入半导体芯片24。通过对基板28的第一主面30应用金属沉积过程可以向基板28的第一主面30上生长金属层48。沉积的金属层48的厚度可以是T8。因为该过程是没有金属在半导体芯片24上生长，因此半导体芯片24的第二主面14与沉积的金属层48的外表面之间的距离将减小。
可以向基板28的第一主面30上电流沉积金属层48。如在图6D中示出的，通过例如向基板28上电流沉积金属来生长金属层的过程可以例如持续，直到半导体芯片24的、背离基板28的主表面与沉积的金属48的外表面49彼此处于同一水平面上而例如在小于5μm、2μm、1μm或0.5μm的容差TOL之内（其中TOL=|T10-T8|，其中T10是基板28的第一主面30与沉积的金属层48的外表面49之间的距离）。此外，半导体芯片24的、背离基板28的主面14与沉积的金属48的外表面可以例如是平齐的，即之间没有间隙。因此，可以将半导体芯片24例如在其横向侧完全地嵌入到金属中。
如果将基板28加上电流沉积的金属层48考虑为新的基板，则可以说图6的过程步骤可以减小半导体芯片24的、背离新基板的主面与新基板的外表面之间的拓扑差异，以形成用于进一步处理的共同的平面或平台。对图6D所示的结构的进一步处理可以包括薄膜处理，例如薄膜金属层生成或薄膜聚合物层生成、构造、过孔生成、层压、模制、或在封装技术中使用的其它过程步骤。参照图3H-3J的描述以避免重复。
应理解任何术语如“形成”或“应用”意味着在语义上涵盖各种应用层及其技术。具体而言，它们意味着涵盖其中层被整体一次应用的技术，例如层压技术、以及其中以顺序方式沉积层的技术，例如溅射、电镀、模制、CVD（化学汽相沉积）、PVD（物理汽相沉积）、蒸发、混合物理化学汽相沉积（HPCVD）等。
尽管特定的实施例已经在本文中得以图示和描述，本领域技术人员应理解，可以在不背离本发明的范围的情况下，各种可替换和/或等效的实施例可以替代示出和描述的具体实施例。本申请意在涵盖本文所描述的具体实施例的任何修改或变化。因此，旨在于本发明仅由权利要求及其等同物进行限制。

Claims (25)

1.一种方法，包括：
将增强晶片应用于半导体晶片，由此形成复合晶片；以及
分割所述复合晶片，由此生成多个复合芯片，每个复合芯片包括半导体芯片和增强芯片。
2.根据权利要求1所述的方法，其中将所述增强晶片应用于所述半导体晶片包括胶合。
3.根据权利要求1所述的方法，其中所述半导体晶片具有小于40μm的厚度。
4.根据权利要求1所述的方法，其中将所述增强晶片应用于所述半导体晶片包括将所述增强晶片应用于所述半导体晶片的正面。
5.根据权利要求1所述的方法，其中将所述增强晶片应用于所述半导体晶片包括将所述增强晶片应用于所述半导体晶片的背面。
6.根据权利要求1所述的方法，还包括在将所述增强晶片应用于所述半导体晶片之前减薄所述半导体晶片。
7.根据权利要求1所述的方法，还包括在将所述增强晶片应用于所述半导体晶片之后减薄所述半导体晶片。
8.根据权利要求1所述的方法，其中所述增强晶片包括从包括如下各项的组中选择的材料：玻璃、树脂材料、铜、铜合金、模制材料和非晶硅。
9.根据权利要求1所述的方法，还包括将所述多个复合芯片附接到临时载体。
10.根据权利要求9所述的方法，还包括将密封材料应用于所述多个复合芯片和所述临时载体，由此生成人工晶片。
11.根据权利要求10所述的方法，还包括从所述临时载体释放所述人工晶片。
12.根据权利要求1所述的方法，还包括将所述多个复合芯片中的至少一个复合芯片接合到基板。
13.根据权利要求12所述的方法，其中将所述多个复合芯片中的所述至少一个复合芯片接合到所述基板，其中所述半导体芯片面向所述基板。
14.根据权利要求12所述的方法，还包括：
将所述多个复合芯片可释放地附接到附接面板；以及
以批处理方式将所述多个复合芯片接合到所述基板。
15.根据权利要求12所述的方法，还包括在接合所述多个复合芯片中的所述至少一个复合芯片期间或者之后，使所述增强芯片与所述半导体芯片分离。
16.根据权利要求15所述的方法，其中在单个热处理内执行将所述多个复合芯片中的所述至少一个复合芯片接合到所述基板并且使所述增强芯片与所述半导体芯片分离。
17.根据权利要求12所述的方法，还包括向所述基板上沉积金属以将所述半导体芯片嵌入在沉积的所述金属中。
18.根据权利要求17所述的方法，其中所述半导体芯片中的所述至少一个半导体芯片的、背离所述基板的主表面与沉积的所述金属的外表面彼此处于同一水平面上而在小于2μm的容差之内。
19.一种复合晶片，包括：
半导体晶片，包括第一主面和第二主面；以及
增强晶片，被附接到所述半导体晶片的所述第一主面，其中所述半导体晶片具有小于40μm的厚度。
20.一种复合芯片，包括：
半导体芯片，包括第一主面和第二主面；以及
增强芯片，被附接到所述半导体芯片的所述第一主面，其中所述半导体芯片具有小于40μm的厚度。
21.一种方法，包括：
提供具有第一主面和第二主面的基板；
将半导体芯片附接到所述基板的所述第一主面；以及
通过向所述基板的所述第一主面上沉积金属层来嵌入所述半导体芯片。
22.根据权利要求21所述的方法，其中向所述基板的所述第一主面上沉积所述金属层，直到沉积的所述金属层的表面与所述半导体芯片的、背离所述基板的表面基本上成水平而在小于1μm的容差之内。
23.根据权利要求21所述的方法，其中沉积所述金属层包括向所述基板的所述第一主面上电流沉积所述金属层。
24.一种半导体器件，包括：
基板，具有第一主面和第二主面；
半导体芯片，被附接到所述基板的所述第一主面；以及
金属层，被沉积到所述基板的所述第一主面上，由此嵌入所述半导体芯片。
25.根据权利要求24所述的半导体器件，其中所述金属层的表面与所述半导体芯片的、背离所述基板的表面彼此处于同一水平面上而在小于1μm的容差之内。
CN201410043965.9A 2013-01-30 2014-01-29 半导体器件及其生产方法 Active CN103972170B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/754,382 US9202753B2 (en) 2013-01-30 2013-01-30 Semiconductor devices and methods of producing these
US13/754,382 2013-01-30

Publications (2)

Publication Number Publication Date
CN103972170A true CN103972170A (zh) 2014-08-06
CN103972170B CN103972170B (zh) 2017-09-08

Family

ID=51163688

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410043965.9A Active CN103972170B (zh) 2013-01-30 2014-01-29 半导体器件及其生产方法

Country Status (3)

Country Link
US (1) US9202753B2 (zh)
CN (1) CN103972170B (zh)
DE (1) DE102014101076B4 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110444480A (zh) * 2019-07-24 2019-11-12 浙江荷清柔性电子技术有限公司 制作柔性芯片的方法、柔性芯片

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9368436B2 (en) 2014-08-04 2016-06-14 Infineon Technologies Ag Source down semiconductor devices and methods of formation thereof
US9640419B2 (en) * 2014-08-04 2017-05-02 Infineon Technologies Ag Carrier system for processing semiconductor substrates, and methods thereof
CN106328572B (zh) * 2015-07-02 2020-03-10 无锡华润华晶微电子有限公司 一种将已完成表面工艺的晶圆从硅片上进行卸片的方法
CN106486572B (zh) 2015-09-02 2020-04-28 新世纪光电股份有限公司 发光二极管芯片
CN107768487A (zh) * 2016-08-18 2018-03-06 新世纪光电股份有限公司 巨量转移电子元件的方法
TWI723207B (zh) 2016-08-18 2021-04-01 新世紀光電股份有限公司 微型發光二極體及其製造方法
US10090199B2 (en) 2017-03-01 2018-10-02 Semiconductor Components Industries, Llc Semiconductor device and method for supporting ultra-thin semiconductor die
US11043420B2 (en) * 2018-09-28 2021-06-22 Semiconductor Components Industries, Llc Fan-out wafer level packaging of semiconductor devices
TWI682513B (zh) * 2019-02-27 2020-01-11 恆勁科技股份有限公司 半導體封裝結構及其製造方法
US11367657B2 (en) 2019-08-01 2022-06-21 Semiconductor Components Industries, Llc Process of forming an electronic device including a polymer support layer
US11742381B2 (en) 2020-07-14 2023-08-29 Semiconductor Components Industries, Llc Monolithic semiconductor device assemblies

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004253628A (ja) * 2003-02-20 2004-09-09 Seiko Epson Corp 半導体装置の製造方法
US20060199353A1 (en) * 2002-07-12 2006-09-07 The Government Of The Usa, As Represented By The Secretary Of The Navy Naval Research Laboratory Wafer bonding of thinned electronic materials and circuits to high performance substrate
US20120068336A1 (en) * 2010-09-17 2012-03-22 Irvine Sensors Corporation Method for Fabricating a Neo-Layer Using Stud Bumped Bare Die

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100222299B1 (ko) * 1996-12-16 1999-10-01 윤종용 웨이퍼 레벨 칩 스케일 패키지 및 그의 제조 방법
US6350664B1 (en) * 1999-09-02 2002-02-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
JP4100936B2 (ja) * 2002-03-01 2008-06-11 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
JP3831287B2 (ja) * 2002-04-08 2006-10-11 株式会社日立製作所 半導体装置の製造方法
JP3961537B2 (ja) * 2004-07-07 2007-08-22 日本電気株式会社 半導体搭載用配線基板の製造方法、及び半導体パッケージの製造方法
JP4776188B2 (ja) * 2004-08-03 2011-09-21 古河電気工業株式会社 半導体装置製造方法およびウエハ加工用テープ
DE102007007142B4 (de) * 2007-02-09 2008-11-13 Infineon Technologies Ag Nutzen, Halbleiterbauteil sowie Verfahren zu deren Herstellung
JP5368957B2 (ja) * 2009-12-04 2013-12-18 シャープ株式会社 半導体レーザチップの製造方法
US8461017B2 (en) * 2010-07-19 2013-06-11 Soitec Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region
CN102413641A (zh) * 2010-07-22 2012-04-11 日本特殊陶业株式会社 多层型线路板及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060199353A1 (en) * 2002-07-12 2006-09-07 The Government Of The Usa, As Represented By The Secretary Of The Navy Naval Research Laboratory Wafer bonding of thinned electronic materials and circuits to high performance substrate
JP2004253628A (ja) * 2003-02-20 2004-09-09 Seiko Epson Corp 半導体装置の製造方法
US20120068336A1 (en) * 2010-09-17 2012-03-22 Irvine Sensors Corporation Method for Fabricating a Neo-Layer Using Stud Bumped Bare Die

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110444480A (zh) * 2019-07-24 2019-11-12 浙江荷清柔性电子技术有限公司 制作柔性芯片的方法、柔性芯片

Also Published As

Publication number Publication date
DE102014101076A1 (de) 2014-07-31
US9202753B2 (en) 2015-12-01
US20140210054A1 (en) 2014-07-31
CN103972170B (zh) 2017-09-08
DE102014101076B4 (de) 2019-11-21

Similar Documents

Publication Publication Date Title
CN103972170A (zh) 半导体器件及其生产方法
CN107134438B (zh) 半导体器件和在半导体管芯周围形成绝缘层的方法
CN104217997B (zh) 3d封装件及其形成方法
CN103915414B (zh) 倒装芯片晶片级封装及其方法
CN105428265B (zh) 半导体装置的制造方法
CN104051337B (zh) 立体堆叠集成电路系统芯片封装的制造方法与测试方法
CN103633075B (zh) 叠层封装半导体器件
CN103383919B (zh) 用于制造芯片封装件的方法
TW201539590A (zh) 半導體裝置及形成微機電系統封裝的方法
TW201133769A (en) Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US20130256857A1 (en) Semiconductor Packages and Methods of Formation Thereof
US20160155680A1 (en) Semiconductor Package and Method of Fabrication Thereof
US9000589B2 (en) Semiconductor device with redistributed contacts
CN103367245A (zh) 形成半导体器件的方法
SG189742A1 (en) Semiconductor device and method of forming protective material between semiconductor die stacked on semiconductor wafer to reduce defects during singulation
CN104465412A (zh) 芯片封装及其制造方法和芯片组件及其制造方法
EP2111636A1 (en) High thermal performance packaging for circuit dies
US10707158B2 (en) Package with vertical interconnect between carrier and clip
CN106486458A (zh) 多功率芯片的功率封装模块及功率芯片单元的制造方法
CN103426837A (zh) 半导体封装及形成半导体封装的方法
JP2021535608A (ja) ウェハレベルパッケージ方法及びパッケージ構造
JP2021535613A (ja) ウェハレベルパッケージ方法及びパッケージ構造
CN103515346A (zh) 半导体模块及其形成方法
CN110745773B (zh) 用于气密密封的薄膜结构
CN112005338A (zh) 在具有翘曲控制增强件的大载体上同时制造多晶圆的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant