CN103928526A - 一种横向功率mos高压器件 - Google Patents

一种横向功率mos高压器件 Download PDF

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CN103928526A
CN103928526A CN201410174519.1A CN201410174519A CN103928526A CN 103928526 A CN103928526 A CN 103928526A CN 201410174519 A CN201410174519 A CN 201410174519A CN 103928526 A CN103928526 A CN 103928526A
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power mos
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胡盛东
金晶晶
陈银晖
朱志
武星河
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Chongqing University
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure

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Abstract

本发明公开了一种横向功率MOS高压器件，包括P型衬底、设置在P型衬底上的N型有源层、设置在N型有源层上的场氧化硅层和位于MOS器件顶端两侧的源电极区、漏电极区，其特征在于：所述P型衬底包括第1层P型硅层至第n层P型硅层，所述n层P型硅层与(n-1)层P型硅层之间设置有若干不连续的N+区，所述N+区与P硅层底形成NP结；其中，n大于等于2。本发明以优化漂移区横向电场达到提高器件耐压的目的，通过在多层P型衬底界面注入不连续的N+区，使得衬底电势钉扎，一方面在衬底中引入新的电场峰值，降低漏端下方主结电场达到辅助衬底耗尽的目的，使得漂移区与衬底形成的NP结的纵向电场值降低从而在保证器件不击穿的条件下优化器件横向电场的目的。

Description

一种横向功率MOS高压器件
技术领域
本发明涉及一种半导体功率器件，特别涉及一种横向功率MOS高压器件。
背景技术
横向功率LDMOS(Lateral Double-diffused Metal-Oxide-Semiconductor即横向双扩散金属-氧化物-半导体)器件广泛应用于功率集成领域，而如何提高器件的击穿电压是人们长期关注的焦点问题之一，并由此提出众多缓解该矛盾的方案。RESURF(Reduced SURface Field,降低表面电场)技术和结终端技术如横向变掺杂技术、表面降场层技术是较为常用的技术。图1为典型的RESURF技术LDMOS器件结构，其中1为第1层P型衬底，4为N型有源层，7为衬底电极，8为漏N+区，9为漏电极，10为源P+区，11为源N+区，12多晶硅栅，13为栅氧化硅层，14为P-Body区，16为场氧化硅层，17为源电极。关态时，衬底电极和源电极接地，漏电极接高压，该结构当外延层全部耗尽时，外延层耗尽区电场与衬底耗尽区电场相互抵消，降低了表面电场，使击穿点由横向PN结表面转移到体内，达到提高击穿电压和降低比导通电阻的效果。相关内容可见参考文献：J.A.Appels and H.M.J.Vaes,High-voltage thinlayer devices,IEDM Tech.Dig.,1979,pp.238-241；S.Y.Han,H.W.Kim,and S.K.Chung,Surface field distribution and breakdown voltage of RESURF LDMOSFETs,MicroelectronicsJournal,2001,31(8),pp.685-688。在RESURF结构基础上，双RESURF(Double-RESURF)结构被提出，见图2，其中1为第1层P型衬底，4为N型有源层，7为衬底电极，8为漏N+区，9为漏电极，10为源P+区，11为源N+区，12多晶硅栅，13为栅氧化硅层，14为P-Body区，16为场氧化硅层，17为源电极，18为P-top降场层。与单RESURF相比，双RESURF是在漂移区表面加一个P-top降场层，该P-top层辅助耗尽N-漂移区，在满足RESURF条件时使得N漂移区掺杂浓度进一步提高，从而获得更小的导通电阻，同时降场层的存在可优化器件横向电场，获得高的击穿电压。相关内容可见参考文献：Souza M.M.D.,Narayanan E.M.S.,Double RESURF technology for HVIC,Electronics Letters,1996,Vol.32,No.12,pp.1092-1093；Hardikar S.,Souza M.M.D.,Xu Y.Z.,et al.,A novel double RESURF LDMOS forHVIC’s,Microelectronics Journal,2004,Vol.35,No.3,pp.305-310。基于横向变掺杂技术的LDMOS结构见图3，1为第1层P型衬底，7为衬底电极，8为漏N+区，9为漏电极，10为源P+区，11为源N+区，12多晶硅栅，13为栅氧化硅层，14为P-Body区，16为场氧化硅层，17为源电极，19为横向变掺杂的N型有源层。其概念N型有源层由源自漏逐渐增厚，在反向偏置电压可获得均匀的横向电场分布，获得高的击穿电压。详见文献Hardikar,S.,Tadikonda,R.,Green,D.W.,Vershinin,K.V.,and Narayanan,E.M.S..Realizing high-voltagejunction isolated LDMOS transistors with variation in lateral doping,IEEE Trans.Electron Devices,2004,51,(12),pp.2223–2228。目前典型的常规LDMOS器件在阻断状态时，衬底电势过于集中，从而影响器件击穿电压的进一步提高，如何通过新器件结构的设计以获得高的击穿电压仍然是LDMOS领域内世界范围内的研究热点。
发明内容
有鉴于此，为了进一步获得具有高击穿电压的功率MOS器件，缓解该类器件的高耐压瓶颈问题，本发明提出一种新型的功率MOS器件结构，较常规器件结构大大提高击穿电压。
本发明的目的是通过这样的技术方案实现的，一种横向功率MOS高压器件，包括P型衬底、设置在P型衬底上的N型有源层、设置在N型有源层上的场氧化硅层和位于MOS器件顶端两侧的源电极区、漏电极区，所述P型衬底包括第1层P型硅层至第n层P型硅层，所述n层P型硅层与(n-1)层P型硅层之间设置有若干不连续的N+区，所述N+区与P硅层底形成NP结；其中，n大于等于2。
进一步，所述N型有源层与第n层P型硅层之间设置有P型区，所述N型有源层和第n层P型硅层部分接触于P型区。
进一步，所述源电极区包括设置在场氧化硅层16中的源电极17、设置在N型有源层中的且与源电极下表面接触的源P+区10和源N+区11，所述源P+区和源N+区从左往右依次排列；所述漏电极区包括设置在场氧化硅层中的漏电极和设置在N型有源层中的且与漏电极下表面接触的漏N+区；所述场氧化硅层内还设置有多晶硅栅12，所述多晶硅栅设置在源电极与漏电极之间且多晶硅栅的下表面与N型有源层分离；所述N型有源层中还设置有P-Body区，所述P-Body区同时与源P+区、源N+区、场氧化硅层接触，所述P-Body区的下表面与P型区接触。
进一步，所述若干不连续的N+区之间的距离相等，每个N+区的宽度相等。
进一步，所述n层P型硅层的厚度相等，其掺杂浓度相同。
进一步，所述N型有源层为Si、SiC、GaN半导体材料中的一种或多种。
由于采用了上述技术方案，本发明具有如下的优点：
本发明在常规的基于RESURF器件基础上，以优化漂移区横向电场达到提高器件耐压的目的，通过在多层P型衬底界面注入不连续的N+区，使得衬底电势钉扎，引入不连续N+区一方面在衬底中引入新的电场峰值，降低漏端下方主结电场达到辅助衬底耗尽的目的，另一方面使得漂移区与衬底形成的NP结的纵向电场值降低从而在保证器件不击穿的条件下优化器件横向电场的目的。这两种效果同时达到增加器件耐压的效果。
附图说明
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步的详细描述，其中：
图1为常规单RESURF LDMOS器件结构示意图；
图2为具有P型降场层的双RESURF LDMOS器件结构示意图；
图3为横向变掺杂LDMOS器件结构示意图；
图4为本发明提出的一种横向功率MOS器件结构；
图5为本发明提出的一种横向功率MOS器件当P型衬底层数为2时的结构示意图；
图6为本发明提出的一种横向功率MOS器件击穿时的等势线分布图；
图7为与本发明尺寸相同的常规器件结构击穿进的等势线分布图；
图8为n等于3时本发明所提出的新器件击穿时的等势线分布图；
其中，1为第1层P型硅层；3为第n层P型硅层；4为N型有源层；5为第1层不连续的N+区；6为第(n-1)层不连续的N+区；7为衬底电极；8为漏N+区；9为漏电极；10为源P+区；11为源N+区；12为多晶硅栅；13为栅氧化硅层；14为P-Body区；15为P型区；16为场氧化硅层；17为源电极；18为P-top层。
具体实施方式
以下将结合附图，对本发明的优选实施例进行详细的描述；应当理解，优选实施例仅为了说明本发明，而不是为了限制本发明的保护范围。
如图4所示，一种横向功率MOS高压器件，包括P型衬底、设置在P型衬底上的N型有源层4、设置在N型有源层上的场氧化硅层16和位于MOS器件顶端两侧的源电极区、漏电极区，所述P型衬底包括第1层P型硅层1至第n层P型硅层3，所述n层P型硅层与(n-1)层P型硅层之间设置有若干不连续的N+区5、6，所述N+区与P硅层底形成NP结；其中，n大于等于2。
所述N型有源层与第n层P型衬底之间设置有P型区15，所述N型有源层和第n层P型衬底部分接触于P型区。
所述源电极区包括设置在场氧化硅层16中的源电极17、设置在N型有源层中的且与源电极下表面接触的源P+区10和源N+区11，所述源P+区和源N+区从左往右依次排列；所述漏电极区包括设置在场氧化硅层中的漏电极9和设置在N型有源层中的且与漏电极9下表面接触的漏N+区8；所述场氧化硅层16内还设置有多晶硅栅12，所述多晶硅栅设置在源电极与漏电极之间且多晶硅栅的下表面与N型有源层分离，所述多晶硅栅的下表面设置有一栅氧化硅层13；所述N型有源层中还设置有P-Body区14，所述P-Body区同时与源P+区、源N+区、栅氧化硅层接触，所述P-Body区的下表面与P型区接触。
所述的若干不连续的N+区可以是等宽或者不等宽的，每个N+区为等距或者不等距的。
所述多层P型衬底中的n层P型硅层可以是等厚度或者不等厚度的，掺杂浓度可以是相等或者不相等的。
所述N型有源层为Si、SiC、GaN半导体材料中的一种或多种。
本发明的工作原理：下面以图5提出的当P型衬底层数n为2时的一种横向功率MOS器件，对所提出的新器件结构的工作机理进行详细说明。当其漏电极9端外加一个高电压Vd，而源电极17、栅电极12及衬底电极7接地，N+区5一方面可以看成是在器件衬底形成一系列新的NP结，其带来衬底的辅助耗尽作用，衬底耗尽区边界向下扩展，器件纵向耐压增加。另一方面，漏端纵向高电势被引向源端，增加源端下方纵向耐压，避免器件在漏端提前击穿。另外，N+区5在衬底内形成一系列横向耐压结构，实现衬底电势钉扎，抬高器件漂移区中间电场。因此本发明所提出的新器件结构可有效提高常规LDMOS器件的击穿电压。图6和图7分别为相同尺寸的本发明所提出新器件结构和常规器件结构击穿时的等势线分布。可见，本发明所提出新器件结构等势线分布明显更加均匀，衬底耗尽区也更深，因而击穿电压较高，达到701V，而常规器件结构仅有378V。图8为n为3时本发明所提出的新器件击穿时的等势线，可以看出衬底电势进一步被调制。
本发明在常规的基于RESURF器件基础上，以优化漂移区横向电场达到提高器件耐压的目的，通过在多层P型衬底界面注入不连续的N+区，使得衬底电势钉扎，引入不连续N+区一方面在衬底中引入新的电场峰值，降低漏端下方主结电场达到辅助衬底耗尽的目的，另一方面使得漂移区与衬底形成的NP结的纵向电场值降低从而在保证器件不击穿的条件下优化器件横向电场的目的。这两种效果同时达到增加器件耐压的效果。
以上所述仅为本发明的优选实施例，并不用于限制本发明，显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (6)

1.一种横向功率MOS高压器件，包括P型衬底、设置在P型衬底上的N型有源层、设置在N型有源层上的场氧化硅层和位于MOS器件顶端两侧的源电极区、漏电极区，其特征在于：所述P型衬底包括第1层P型硅层至第n层P型硅层，所述n层P型硅层与(n-1)层P型硅层之间设置有若干不连续的N+区，所述N+区与P硅层底形成NP结；其中，n大于等于2。
2.根据权利要求1所述横向功率MOS高压器件，其特征在于：所述N型有源层与第n层P型硅层之间设置有P型区，所述N型有源层和第n层P型硅层部分接触于P型区。
3.根据权利要求2所述的横向功率MOS高压器件，其特征在于：所述源电极区包括设置在场氧化硅层(16)中的源电极(17)、设置在N型有源层中的且与源电极下表面接触的源P+区(10)和源N+区(11)，所述源P+区和源N+区从左往右依次排列；所述漏电极区包括设置在场氧化硅层中的漏电极和设置在N型有源层中的且与漏电极下表面接触的漏N+区；所述场氧化硅层内还设置有多晶硅栅(12)，所述多晶硅栅设置在源电极与漏电极之间且多晶硅栅的下表面与N型有源层分离；所述N型有源层中还设置有P-Body区，所述P-Body区同时与源P+区、源N+区、场氧化硅层接触，所述P-Body区的下表面与P型区接触。
4.根据权利要求1所述的横向功率MOS高压器件，其特征在于：所述若干不连续的N+区之间的距离相等，每个N+区的宽度相等。
5.根据权利要求1所述的横向功率MOS高压器件，其特征在于：所述n层P型硅层的厚度相等，其掺杂浓度相同。
6.根据权利要求1所述的横向功率MOS高压器件，其特征在于：所述N型有源层为Si、SiC、GaN半导体材料中的一种或多种。
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