CN103887169A - 一种具有提高抗浪涌电流能力的半导体装置的制备方法 - Google Patents
一种具有提高抗浪涌电流能力的半导体装置的制备方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title claims abstract description 6
- 238000002347 injection Methods 0.000 claims abstract description 23
- 239000007924 injection Substances 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 19
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000005036 potential barrier Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000001039 wet etching Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 3
- 101100207343 Antirrhinum majus 1e20 gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
Abstract
本发明公开了一种具有提高抗浪涌电流能力的半导体装置的制备方法；本发明的半导体装置，为一种改进的TMBS二极管；本发明的半导体装置，利用金属Cr作为刻蚀掩膜，在SiC漂移层表面形成深槽结构，湿法腐蚀使Cr掩膜线宽变窄，露出未刻蚀台面的两边，以此为注入掩膜对SiC漂移层表面进行Al离子注入，从而在台面两边形成P型注入区，该注入区与N型漂移区形成PN结，在大电流条件下该PN结参与导通，利用少子注入形成电导调制效应，使得该半导体装置具备抗浪涌电流能力。除此之外，该方法能够在沟槽底部同时形成P注入区，在器件的反向阻断状态下该P区能够保护沟槽底部，防止不理想的刻蚀表面形成电场集中，防止发生提前击穿，从而提高器件的可靠性。
Description
技术领域
本发明涉及一种具有提高抗浪涌电流能力的半导体装置的制备方法，本发明的半导体装置主要应用于功率电路。
背景技术
碳化硅半导体器件是下一代功率半导体器件的优秀代表。碳化硅半导体材料具有相对第一代硅功率半导体材料更优秀的电流导通和电压阻断能力，可以实现非常低的导通电阻和快速切换时间。因此适合在半导体功率器件方向的应用。
传统的碳化硅半导体器件TMBS二极管(Trench Metal-Oxide-Semiconductor Barrier Schottky Diode)的阳极为纯肖特基结，不存在PN结。由于肖特基结基本没有少子注入现象，在恶劣的工况如浪涌电流条件下，传统型的TMBS二极管的导通压降急剧增加，器件的导通损耗随之迅速增加，从而导致器件损坏。因此需要在原有的器件结构中设计P注入区形成PN结。
本发明中提出的一种具有抗浪涌电流能力的TMBS二极管，可以有效解决传统TMBS二极管的问题。通过在阳极下面引入P注入区形成PN结，该PN结与肖特基结平行，在浪涌电流条件下参与导通，通过少子注入进行电导调制，从而降低导通压降，使器件 具备抗浪涌电流能力。该结构不仅可以使器件具备抗浪涌电流能力，而且同时在沟槽底部形成的P注入区还能起到保护沟槽底部的作用，防止不理想的刻蚀表面形成电场集中，防止发生提前击穿，从而提高器件的可靠性。
发明内容
本发明提出一种具有提高抗浪涌电流能力的半导体装置的制备方法，其特征在于，利用金属铬(Cr)作为掩膜，通过RIE(Reactive Ion Etching)方法对碳化硅漂移层表面进行深槽刻蚀，然后以光刻胶作为保护，将Cr掩膜进行短暂的湿法腐蚀，利用横向腐蚀作用使Cr掩膜线宽变窄，露出台面的两边，并以此Cr金属作为离子注入掩膜，对碳化硅漂移层表面进行垂直方向上的Al离子注入，从而在台面两边形成P型注入区。该注入区与N型漂移层形成PN结，在大电流工作条件下该PN结参与导通，通过少子注入形成电导调制效应，使得该半导体装置具备抗浪涌电流能力。
本发明提出一种具有提高抗浪涌电流能力的半导体装置，其特征在于，在台面形成P型注入区的同时，在沟槽底部形成P型注入区，在器件的反向阻断状态下该P区能够保护沟槽底部，防止不理想的刻蚀表面形成电场集中，防止沟槽底部发生提前击穿，从而提高器件可靠性。
附图说明
图1为实施本发明的一种半导体装置的第一步工艺截面图
图2为实施本发明的一种半导体装置的第二步工艺截面图
图3为实施本发明的一种半导体装置的第三步工艺截面图
图4为实施本发明的一种半导体装置的第四步工艺截面图
图5为实施本发明的一种半导体装置的第五步工艺截面图
图6为本发明的一种半导体装置的截面图
符号说明
1 SiC衬底层
2 SiC漂移层
3 金属Cr掩膜
4 光刻胶
5 沟槽P注入区
6 台面P注入区
7 氧化层
8 阴极
9 阳极
具体实施方式
图6为为本发明的一种具有提高抗浪涌电流能力的半导体装置截面图，下面结合图6详细说明本发明的半导体装置。
一种具有抗浪涌电流能力的半导体装置，包括：衬底层1，为N导电类型碳化硅半导体材料，N型材料的掺杂浓度范围为[1e15／cm3，1e20／cm3]；在衬底层1上表面为漂移层2，为N导电类型碳化硅半导体材料，其掺杂浓度低于衬底层1，N型材料的掺杂浓度范围为[1e13／cm3，1e19／cm3]，在该层表面用RIE方法刻蚀形成深槽； 在沟槽底部和台面两边离子注入形成P型注入区5和6，台面P注入区6与漂移层2形成PN结；而沟槽P注入区5位于沟槽底部起到保护作用；在沟槽的侧壁和底部覆盖一层氧化层7；阳极9与SiC漂移层2表面形成肖特基接触，并且延伸到沟槽中覆盖在氧化层7的表面，与氧化层7、SiC漂移层2一起形成MOS势垒；阴极8与SiC衬底1背面形成欧姆接触。
其制作工艺包括如下步骤：
第一步，如图1所示，在具有层1，2的外延上淀积一层金属Cr3，涂上光刻胶4进行光刻，对Cr进行干法刻蚀形成掩膜图形；
第二步，如图2所示，以金属Cr3作为掩膜，用RIE(Reactive Ion Etching)方法刻蚀SiC漂移层2形成深槽结构；
第三步，如图3所示，以光刻胶4作为保护，对金属Cr3进行湿法腐蚀，利用横向腐蚀使线宽变窄；
第四步，如图4所示，去掉光刻胶4，以变窄的金属Cr3作为掩膜，对SiC漂移层进行Al离子注入，从而形成沟槽底部P注入区5和台面P注入区6；
第四步，如图5所示，去掉金属Cr3，用回刻法在沟槽底部和侧壁覆盖一层氧化层7，在SiC衬底背面1覆盖阴极金属8，形成欧姆接触；
第五步，如图6所示，在SiC漂移层2的表面覆盖阳极金属9形成肖特基接触，阳极金属9延伸到沟槽中，覆盖在氧化层7的表面形成MOS势垒。
Claims (11)
1.一种具有提高抗浪涌电流能力的半导体装置的制备方法，其特征：
阳极和阴极；碳化硅半导体与所述阳极形成肖特基接触，阴极形成欧姆接触。
2.如权利要求1所述的器件，其中，所述器件的第一层半导体为SiC衬底。
3.如权利要求1所述的器件，其中，所述器件的第二层半导体为SiC漂移层。
4.如权利要求3所述的器件，其中，所述SiC漂移层的表面用RIE(ReactiveIonEtching)方法刻蚀形成深槽结构。
5.如权利要求4所述的器件，其中，所述沟槽与沟槽之间未刻蚀区域为台面结构。
6.如权利要求5所述的器件，其中，所述台面结构的两边注入Al离子形成P型注入区。
7.如权利要求4所述的器件，其中，所述沟槽底部注入Al离子形成P型注入区保护沟槽底部。
8.如权利要求4所述的器件，其中，所述沟槽底部和侧壁覆盖一层氧化层。
9.如权利要求5所述的器件，其中，所述台面结构上覆盖阳极金属形成肖特基接触。
10.如权利要求9所述的器件，其中，所述阳极金属延伸到沟槽中，覆盖在氧化层上面形成MOS势垒。
11.如权利要求1所述的器件，其中，所述阴极为Ni金属与碳化硅衬底背面形成欧姆接触。
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107293601A (zh) * | 2016-04-12 | 2017-10-24 | 朱江 | 一种肖特基半导体装置及其制备方法 |
| CN110571282A (zh) * | 2019-08-01 | 2019-12-13 | 山东天岳电子科技有限公司 | 一种肖特基二极管及其制造方法 |
| WO2021128435A1 (zh) * | 2019-12-28 | 2021-07-01 | 汪克明 | 新半导体电子原理技术与器件 |
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| CN107293601A (zh) * | 2016-04-12 | 2017-10-24 | 朱江 | 一种肖特基半导体装置及其制备方法 |
| CN107293601B (zh) * | 2016-04-12 | 2021-10-22 | 朱江 | 一种肖特基半导体装置及其制备方法 |
| CN110571282A (zh) * | 2019-08-01 | 2019-12-13 | 山东天岳电子科技有限公司 | 一种肖特基二极管及其制造方法 |
| WO2021128435A1 (zh) * | 2019-12-28 | 2021-07-01 | 汪克明 | 新半导体电子原理技术与器件 |
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