CN1037881C - 形成半导体器件接触孔的方法 - Google Patents

形成半导体器件接触孔的方法 Download PDF

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CN1037881C
CN1037881C CN95108120A CN95108120A CN1037881C CN 1037881 C CN1037881 C CN 1037881C CN 95108120 A CN95108120 A CN 95108120A CN 95108120 A CN95108120 A CN 95108120A CN 1037881 C CN1037881 C CN 1037881C
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film
forming
photoresist film
oxide
insulating film
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CN1116362A (zh
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金载甲
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/111—Narrow masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Abstract

一种形成半导体器件接触孔的方法，包括以下各步骤，在一给定的基础结构上形成一绝缘膜；在该绝缘膜上形成一些导电布线；在所得结构上形成均厚层间绝缘膜；再在其上形成第一光刻胶膜图形；在第一光刻胶膜图形的侧壁形成氧化膜调距层；在氧化膜调距层之间的层间绝缘膜上形成第二光刻胶膜图形；依次去掉氧化膜调距层，及所露出的层间绝缘膜的区域，形成接触孔，露出导电布线。其结果，改善了半导体器件的工作可靠性、生产率以及器件的高度集成化。

Description

本发明一般涉及形成半导体器件接触孔的方法，特别涉及通过牺牲膜(sacrificial film)的调距层技术形成尺寸不大于分辨率极限的接触孔的方法，除导致器件高集成化外，还改善了半导体器件的工作稳定性和生产率。
半导体器件的高集成化迫使内连电容器上、下布线的接触孔减少尺寸。接触孔与周围布线间的距离也要缩小。而接触孔的宽度比，径深比反而要增加。因此，在待形成多层导电布线的半导体器件内应精细严格设计接触孔的布局。减小接触孔的尺寸要求半导体器件的制造设备要更精密。使用现行的设备，很难做成尺寸在例如0.4μm以下的精细图形。
为使接触孔相互间隔开，根据接触孔掩模间的某一设计标准，应考虑以下因素来形成接触孔：第一，掩模结构的对不准容差；第二，曝光工艺中的透镜失真；第三，掩模制造和光刻中的关键尺寸变化；以及第四，掩模间的套准。
由于上面考虑的因素，极有可能迫使接触孔本身及其之间的距离增加超过光刻胶膜图形的分辨极限。
此外，因为还应考虑与接触孔的重叠、导电布线的宽度以及距离的增加来形成导电布线之间的距离，所以成为一种使器件难以高集成化的因素。
所以，本发明的主要目的在于提供形成半导体器件的其尺寸不超过光刻胶膜图形分辨极限的接触孔的方法。
本发明的另一目的在于提供能高度集成器件的方法。
根据本发明人的创造性的深入研究，通过提供形成半导体器件接触孔的方法能实现上述目的，该法包括以下各步骤：在半导体器件的基础结构(infrastructure)上形成绝缘膜；在绝缘膜上形成导电布线；在所得结构的表面形成均厚层间绝缘膜；在层间绝缘膜上形成第一光刻胶膜，所说的第一光刻胶膜图形的侧壁位于导电布线之上；在第一光刻胶膜图形的侧壁形成氧化膜调距层；在氧化膜调距层之间的层间绝缘膜上形成第二光刻胶膜；以及依次去掉氧化膜调距层，然后以第一和第二光刻胶膜图形作为掩膜去掉层间绝缘膜的裸露区域，形成接触孔。
通过参照附图详细说明本发明优选实施例会更加明了本发明的上述目的和其它优点。
图1A～1C是表示根据本发明形成半导体器件接触孔的方法的示意剖面图。
参照附图会更好地了解本发明优选实施例的应用。图中相同的标号分别用于相同与相应的部件。
参照图1A，图中一在给定的基础结构，即形成了元件隔离膜、栅电极、源电极的半导体衬底上所形成的绝缘膜1上，用均厚层间绝缘膜3覆盖导电布线2。然后，在层间绝缘膜3上形成第一光刻胶膜图形4，各与下面的相邻的两个导电布线2相重叠。为了平坦化，层间绝缘膜3最好由硼磷硅玻璃(下文称BPSG)，即一种流动性优异的材料形成。
参照图1B，在所得结构上形成氧化膜，经各向异性腐蚀，在第一光刻胶膜图形4的侧壁形成氧化膜调距层。然后在所得结构的表面覆盖一光刻胶膜，经深腐蚀，直至露出氧化膜调距层5的上部，以此形成第二光刻胶膜6。该氧化膜由氧化膜在150～300℃形成，其厚度不超过光刻胶膜图形的分辨极限。
参照图1C，去掉氧化膜调距层5，同时以第一和第二光刻胶膜图形4和6作为掩模，经腐蚀工艺，形成接触孔7，通过接触孔露出导电布线2的区域。然后，去掉第一和第二光刻胶膜图形4和6。
如前所述，本发明之特征在于有特色的方法，该方法包括以下各步骤：在构成基础结构的半导体衬底上形成绝缘膜；在所得结构上形成均厚层间绝缘膜；在层间绝缘膜上形成第一光刻胶膜图形，所说的图形侧壁各位于导电布线上方；在第一光刻胶膜图形侧壁形成氧化膜调距层；在氧化膜调距层之间的层间绝缘膜上形成第二光刻胶膜图形；依次去掉氧化膜调距层及因而所裸露的层间绝缘膜区域，形成接触孔。露出导电布线区域。根据该方法，考虑到与接触孔的重叠，基本上不可能形成导电布线宽度及其间的距离，但可能以接近光刻胶膜图形分辨极限的尺寸形成。此外，根据该方法，接触孔虽然以不超过光刻胶膜图形分辨极限的尺寸形成，但仍可保持与导电布线的重叠，因而使器件高度集成。
在阅读前面说明后，对本领域熟练的普通技术人员应容易了解本文公开的发明的其它特性、优点及实施例。就此而言，虽然非常详细地说明了本发明的具体实施例，但在不脱离所说明的和请求保护的本发明的精神和范畴前提下，对这些实施例可做出各种变化和改型。

Claims (3)

1.一种形成半导体器件接触孔的方法，该法包括以下各步骤：
在半导体器件的基础结构上形成绝缘膜；
在该绝缘膜上形成导电布线；
在所得结构表面上形成均厚层间绝缘膜；
在该层间绝缘膜上形成第一光刻胶膜图形，所说的第一光刻胶膜图形的侧壁各位于导电布线的上方；
在第一光刻胶膜图形的侧壁形成一层氧化膜调距层；
在氧化膜调距层之间的层间绝缘膜上形成第二光刻胶膜图形；以及
然后以第一和第二光刻胶膜图形作为掩模依次去掉氧化膜，去掉所露出的层间绝缘膜的区域，形成接触孔。
2.一种根据权利要求1的方法，其中所说的氧化膜调距层是在约150～300℃的温度形成的。
3.一种根据权利要求1的方法，其中所说的氧化膜调距层的厚度约0.05～0.3mm。
CN95108120A 1994-07-14 1995-07-12 形成半导体器件接触孔的方法 Expired - Fee Related CN1037881C (zh)

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AU2002366913A1 (en) * 2001-12-20 2003-07-09 Koninklijke Philips Electronics N.V. Fabrication of non-volatile memory cell
ITMI20022785A1 (it) * 2002-12-30 2004-06-30 St Microelectronics Srl Processo per la fabbricazione di celle di memoria
ITMI20022784A1 (it) * 2002-12-30 2004-06-30 St Microelectronics Srl Processo per la fabbricazione di celle di memoria
US8084347B2 (en) * 2008-12-31 2011-12-27 Sandisk 3D Llc Resist feature and removable spacer pitch doubling patterning method for pillar structures
US8114765B2 (en) 2008-12-31 2012-02-14 Sandisk 3D Llc Methods for increased array feature density
CN101847576B (zh) * 2010-04-23 2012-01-25 北京大学 一种制备超窄槽的方法
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KR960005789A (ko) 1996-02-23
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