CN103779218B - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN103779218B
CN103779218B CN201210406039.4A CN201210406039A CN103779218B CN 103779218 B CN103779218 B CN 103779218B CN 201210406039 A CN201210406039 A CN 201210406039A CN 103779218 B CN103779218 B CN 103779218B
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卜伟海
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

本发明公开了一种半导体器件及其制造方法，涉及半导体技术领域。该方法中在衬底源/漏处形成凹槽，在凹槽侧壁形成可去除侧墙，然后对凹槽进行刻蚀以形成Sigma形凹陷；在Sigma形凹陷内进行基本不掺杂的硅锗选择性外延生长时由可去除侧墙保护Sigma形凹陷靠近衬底表面不被外延，去除可去除侧墙再在Sigma形凹陷内进行掺杂P型杂质的硅锗外延生长。这样，在充分增加应力的情况下保证源漏结之间有充分的距离，以免加剧短沟道效应，并且无掺杂的SiGe外延生长不给导电通道引入高阻层，避免了器件性能退化，提高了器件性能。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体技术，特别涉及一种半导体器件及其制造方法。
背景技术
在先进技术中，提出嵌入式硅锗（Embedded SiGe，eSiGe）工艺，以增大MOS（MetalOxide Semiconductor，金属氧化物半导体）器件沟道区的应力（Stress），增强其载流子迁移率；其中使用嵌入式硅锗来形成源区或漏区，从而对沟道区施加应力。为达到更好的应力效果，一般在源/漏外延SiGe（硅锗）前需要先进行凹陷（Recess）刻蚀，刻蚀后形成Sigma（“∑”）形凹陷，然后在Sigma形凹陷内外延生长硅锗，以增强施加应力的效果，提高半导体器件性能。
SiGe外延生长需充分靠近沟道以增加应力，但是如果外延一开始就原位掺杂很高浓度的P型杂质，将加剧器件的短沟效应。
为了解决上面这个问题，目前通常先外延生长基本无掺杂的SiGe层，然后再外延高浓度P型掺杂的SiGe。但是，基本无掺杂的SiGe层位于侧墙下方，无法被后续的源漏注入充分掺杂，将增加源漏串联电阻。
发明内容
本发明的发明人发现上述现有技术中存在问题，并因此针对所述问题中的至少一个问题提出了一种新的技术方案。
本发明的一个目的是提供一种半导体器件及其制造方法，能够降低源漏串联电阻。
根据本发明的第一方面，提供了一种半导体器件制造方法，包括：提供衬底，衬底上形成有栅结构；刻蚀衬底以在衬底源/漏处形成凹槽；在凹槽侧壁形成可去除侧墙；对凹槽进行刻蚀以形成Sigma形凹陷；在Sigma形凹陷内进行基本不掺杂的硅锗选择性外延生长；去除可去除侧墙；在Sigma形凹陷内进行掺杂P型杂质的硅锗外延生长。
可选地，凹槽为U型凹陷；通过刻蚀衬底在衬底源/漏处形成凹槽包括：通过自对准刻蚀衬底在衬底源/漏处形成U型凹陷。
可选地，在凹槽侧壁形成可去除侧墙包括：通过化学气相淀积和各向异性刻蚀在在凹槽侧壁形成可去除侧墙；或去除可去除侧墙包括：通过湿法腐蚀或者各向同性的干法刻蚀去除可去除侧墙。
可选地，凹槽的深度为5nm~20nm。
可选地，在形成凹槽前还包括：形成栅结构的偏移间隔物（offset spacer）;进行LDD注入和退火；在Sigma形凹陷内进行掺杂P型杂质的硅锗外延生长后还包括：进行源/漏离子注入。
可选地，该方法还包括：在LDD注入后形成凹槽前形成侧墙；或者在Sigma形凹陷内进行掺杂P型杂质的硅锗外延生长后进行源/漏离子注入前形成侧墙。
可选地，基本不掺杂的硅锗选择性外延生长包括与沟道类型相同掺杂的硅锗选择性外延生长。
根据本发明的另一方面，提供一种半导体器件，半导体器件的衬底上形成有栅结构，在衬底中栅结构侧方形成有Sigma形凹陷；在Sigma形凹陷的内表面外延生长有基本不掺杂的硅锗层，基本不掺杂的硅锗层上外延生长有掺杂P型杂质的硅锗体；其中，基本不掺杂的硅锗层位于Sigma形凹陷内衬底表面预定深度下。
可选地，预定深度为5nm~20nm。
可选地，栅结构两侧形成有偏移间隔物，偏移间隔物两侧形成有侧墙。
本发明的一个优点在于，在无掺杂SiGe外延时通过可去除侧墙保护衬底表面层使它不被外延，然后外延原位掺杂的SiGe，原位掺杂的SiGe会降低源漏串联电阻，提高器件性能。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本发明，其中：
图1A至图1G示意性地示出根据本发明的半导体器件制造方法的一个实施例中各个阶段的截面图。
图2A至图2J示意性地示出根据本发明的半导体器件制造方法的另一个实施例中各个阶段的截面图。
图3A至图3J示意性地示出根据本发明的半导体器件制造方法的又一个实施例中各个阶段的截面图。
图4示出根据本发明的一个实施例的半导体器件的结构示意图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
图1A至图1G示意性地示出根据本发明的半导体器件制造方法的一个实施例中各个阶段的截面图。
如图1A所示，提供衬底100，衬底100上形成有栅结构102。栅结构102的形成可以采用现有的多种方式，具体栅结构也可以根据情况进行选择。可选地，栅结构102两侧还形成有偏移间隔物（Offset Spacer）103，偏移间隔物103的主要成份可以是二氧化硅或氮化硅。
如图1B所示，刻蚀衬底100以在衬底100的源/漏处形成凹槽104。在衬底100中例如通过干法刻蚀在栅结构两侧的源/漏处形成凹槽104。在一个实施例中，该凹槽104的深度大约为沟道深度的1/4~1/3。例如，凹槽104的深度为5nm（纳米）~20nm。
如图1C所示，在凹槽104侧壁形成可去除侧墙105。可以过通过CVD（ChemicalVapor Deposition，化学气相淀积）和各向异性刻蚀在在凹槽104的侧壁形成可去除侧墙105。可去除侧墙105的主要成份可以是氮化硅或二氧化硅，并且与偏移间隔物103具有刻蚀选择比。
如图1D所示，对凹槽104进行刻蚀以形成Sigma形凹陷106。例如，采用具有晶向选择性的湿法蚀刻剂，例如包含四甲基氢氧化铵（TMAH）的蚀刻剂，通过凹槽104对衬底进行蚀刻以形成Sigma形凹陷106。
如图1E所示，在Sigma形凹陷106内进行基本不掺杂的硅锗选择性外延生长（SEG，Selective Epitaxial Growth）生成基本不掺杂的硅锗层107；该基本不掺杂的硅锗选择性外延生长也可以包括与沟道类型相同掺杂的硅锗选择性外延生长。
如图1F所示，去除可去除侧墙105。例如，通过用湿法腐蚀或者各向同性的干法刻蚀去除可去除侧墙105。
如图1G所示，在Sigma形凹陷106内进行掺杂P型杂质的硅锗外延生长获得掺杂P型杂质的硅锗体。例如，进行原位掺杂硼的硅锗选择性外延生长。
上述实施例中，在外延无掺杂SiGe时通过可去除侧墙保护衬底表面层使它不被外延，然后去掉可去除侧墙的保护层，外延原位掺杂的SiGe，从而在充分增加应力的情况下保证源漏结之间有充分的距离，以免加剧短沟道效应，而且，无掺杂SiGe不给导电通道引入高阻层，避免了器件性能退化，提高了器件性能。
图2A至图2J示意性地示出根据本发明的半导体器件制造方法的另一个实施例中各个阶段的截面图。
如图2A所示，提供衬底200，在衬底200上形成STI（Shallow Trench Isolation，浅槽隔离）201，生长栅介质，淀积栅材料和硬掩膜层，然后进行栅极光刻，在衬底200上形成栅介质层202a，栅极202，栅极202上的硬掩膜202b层。淀积和刻蚀介质层，在栅结构202两侧形成有偏移间隔物（Offset Spacer）203。
如图2B所示，进行LDD（Lightly Doped Drain，轻掺杂漏）注入和退火。
如图2C所示，通过自对准刻蚀硅衬底200在衬底200的源/漏处形成凹槽204。该凹槽104可以为Ｕ型凹槽。
如图2D所示，在凹槽204侧壁形成可去除侧墙205。
如图2E所示，对凹槽204进行刻蚀以形成Sigma形凹陷206。
如图2F所示，在Sigma形凹陷206内进行基本不掺杂的硅锗选择性外延生长生成硅锗种子层207；
如图2G所示，去除可去除侧墙205。
如图2H所示，在Sigma形凹陷206内选择性外延源/漏并同时进行原位掺杂，获得掺杂P型杂质的硅锗体208。
如图2I所示，去掉硬掩膜202b，在偏移间隔物203的外侧形成侧墙209。
如图2J所示，进行源漏注入。后续可与HKMG（High-K and Metal Gate，高介电常数介质和金属栅）工艺兼容。
上述实施例中，LDD注入后形成凹槽，在凹槽侧壁形成可去除侧墙，然后形成Sigma形凹陷，在硅锗种子外延生长时由可去除侧墙保护凹陷靠近衬底表面的内壁不生长硅锗，并在原位掺杂的硅锗生长前去除可去除侧墙，从而使得原位掺杂的硅锗体生长于Sigma形凹陷靠近衬底表面的部分，避免了在此处生成高阻区域，提高了器件性能。硬掩膜可以保护栅极在工艺过程中不被污染或者破坏。
图3A至图3J示意性地示出根据本发明的半导体器件制造方法的又一个实施例中各个阶段的截面图。
如图3A所示，提供衬底300，在衬底300中形成STI隔离301，衬底300上形成有栅结构302。栅结构302两侧还形成有偏移间隔物303。
如图3B所示，进行LDD注入形成轻掺杂注入区304，然后进行退火。
如图3C所示，在偏移间隔物303的外侧形成侧墙305。
如图3D所示，通过刻蚀衬底300在衬底300的源/漏处形成凹槽306。
如图3E所示，在凹槽306侧壁形成可去除侧墙307。
如图3F所示，对凹槽306进行刻蚀以形成Sigma形凹陷308。
如图3G所示，在Sigma形凹陷308内进行基本不掺杂的硅锗选择性外延生长生成硅锗种子层309；
如图3H所示，去除可去除侧墙307。
如图3I所示，在Sigma形凹陷306内进行掺杂P型杂质的硅锗外延生长获得掺杂P型杂质的硅锗体308。
如图3J所示，进行源漏注入。
上述实施例中，在形成Sigma形凹陷前形成侧墙，也可以应用可去除侧墙来保护Sigma形凹陷靠近衬底表面的内壁不生长基本不掺杂的硅锗种子层，提高了器件的性能。
图4示出根据本发明的一个实施例的半导体器件的结构示意图。如图4所示，半导体器件的衬底200上形成有栅结构202，在衬底200中栅结构202侧方形成有Sigma形凹陷；在Sigma形凹陷的内表面外延生长有基本不掺杂的硅锗层207，基本不掺杂的硅锗层207上外延生长有掺杂P型杂质的硅锗体208；其中，基本不掺杂的硅锗层207位于Sigma形凹陷内衬底表面预定深度下，即图4中标号41指示的部分没有基本不掺杂的硅锗层207。此外，在栅结构202侧面形成有偏移间隔物203，偏移间隔物203侧面形成有侧墙209。
至此，已经详细描述了根据本发明的制造半导体器件的方法和所形成的半导体器件。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (10)

1.一种半导体器件制造方法，其特征在于，包括：
提供衬底，所述衬底上形成有栅结构；
刻蚀所述衬底以在所述衬底源/漏处形成凹槽；
在所述凹槽侧壁形成可去除侧墙；
对所述凹槽进行刻蚀以形成Sigma形凹陷；
在所述Sigma形凹陷内进行基本不掺杂的硅锗选择性外延生长；
去除所述可去除侧墙；
在所述Sigma形凹陷内进行掺杂P型杂质的硅锗外延生长。
2.根据权利要求1所述的方法，其特征在于，所述凹槽为U型凹陷；
所述刻蚀所述衬底以在所述衬底源/漏处形成凹槽包括：
通过自对准刻蚀所述衬底在所述衬底源/漏处形成U型凹陷。
3.根据权利要求1或2所述的方法，其特征在于，
所述在所述凹槽侧壁形成可去除侧墙包括：
通过化学气相淀积和各向异性刻蚀在所述凹槽侧壁形成可去除侧墙；
或
所述去除所述可去除侧墙包括：
通过湿法腐蚀或者各向同性的干法刻蚀去除所述可去除侧墙。
4.根据权利要求1所述的方法，其特征在于，所述凹槽的深度为5nm～20nm。
5.根据权利要求1所述的方法，其特征在于，在形成所述凹槽前还包括：
形成所述栅结构的偏移间隔物(offset spacer)；
进行轻掺杂漏注入和退火；
在所述Sigma形凹陷内进行掺杂P型杂质的硅锗外延生长后还包括：
进行源/漏离子注入。
6.根据权利要求5所述的方法，其特征在于，还包括：
在轻掺杂漏注入后形成所述凹槽前形成侧墙；
或者
在所述Sigma形凹陷内进行掺杂P型杂质的硅锗外延生长后进行源/漏离子注入前形成侧墙。
7.根据权利要求1所述的方法，其特征在于，所述在所述Sigma形凹陷内进行基本不掺杂的硅锗选择性外延生长包括：
在所述Sigma形凹陷内进行掺杂与沟道类型相同杂质的硅锗选择性外延生长。
8.一种根据权利要求1至7中任意一项所述的半导体器件制造方法所形成的半导体器件，其中，所述半导体器件的衬底上形成有栅结构，在所述衬底中所述栅结构侧方形成有Sigma形凹陷；在所述Sigma形凹陷的内表面外延生长有基本不掺杂的硅锗层，所述基本不掺杂的硅锗层上外延生长有掺杂P型杂质的硅锗体；
其中，所述基本不掺杂的硅锗层位于所述Sigma形凹陷内所述衬底表面预定深度下。
9.根据权利要求8所述的半导体器件，其特征在于，所述预定深度为5nm～20nm。
10.根据权利要求8所述的半导体器件，其特征在于，所述栅结构两侧形成有偏移间隔物，所述偏移间隔物两侧形成有侧墙。
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