CN102640270B - Ω形状的纳米线场效应晶体管 - Google Patents

Ω形状的纳米线场效应晶体管 Download PDF

Info

Publication number
CN102640270B
CN102640270B CN201080054741.8A CN201080054741A CN102640270B CN 102640270 B CN102640270 B CN 102640270B CN 201080054741 A CN201080054741 A CN 201080054741A CN 102640270 B CN102640270 B CN 102640270B
Authority
CN
China
Prior art keywords
nano wire
doping
silicon
grid structure
sept
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201080054741.8A
Other languages
English (en)
Other versions
CN102640270A (zh
Inventor
J·斯莱特
S·邦萨伦蒂普
G·科亨
J·常
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN102640270A publication Critical patent/CN102640270A/zh
Application granted granted Critical
Publication of CN102640270B publication Critical patent/CN102640270B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种用于形成纳米线场效应晶体管(FET)器件的方法，包括在半导体衬底(100)上形成纳米线(110)；在纳米线的第一部分上形成栅极结构；形成与第一栅极结构的侧壁相邻并且在纳米线的从第一栅极结构延伸的部分之上的第一保护性间隔物(604)；移除纳米线的未受第一间隔物保护的露出部分；以及在纳米线的露出截面上外延生长掺杂的半导体材料(902)以形成第一源极区域和第一漏极区域。

Description

Ω形状的纳米线场效应晶体管
技术领域
本发明涉及半导体纳米线场效应晶体管。
背景技术
纳米线场效应晶体管(FET)包括纳米线的掺杂的部分，该部分接触沟道区域并且充当器件的源极区域和漏极区域。使用离子注入以掺杂小直径纳米线的之前制造方法可能导致纳米线的不期望的非晶化或不期望的结掺杂分布。
发明内容
在本发明的一个方面中，提供了一种用于形成纳米线场效应晶体管(FET)器件的方法，包括：在半导体衬底上形成纳米线；在纳米线的第一部分上形成第一栅极结构；形成与第一栅极结构的侧壁相邻并且在纳米线的从第一栅极结构延伸的部分之上的第一保护性间隔物；移除纳米线的未受第一间隔物保护的露出部分；以及在纳米线的露出截面上外延生长掺杂的半导体材料以形成第一源极区域和第一漏极区域。
在本发明的另一方面中，一种用于纳米线场效应晶体管(FET)器件的方法，包括：在半导体衬底上形成纳米线；在纳米线的一部分上形成栅极结构；形成与栅极结构的侧壁相邻并且在纳米线的从栅极结构延伸的部分之上的保护性间隔物；移除纳米线的露出部分以形成由被栅极结构包围的纳米线、半导体衬底以及间隔物限定的腔；以及在腔中从纳米线的露出截面外延生长掺杂的半导体材料。
在本发明的又一方面中，纳米线场效应晶体管(FET)器件包括：沟道区域，包括布置在半导体衬底上的、具有从沟道区域延伸的第一远端和从沟道区域延伸的第二远端的硅部分，该硅部分由圆周地布置在该硅部分上的栅极结构部分地包围；源极区域，包括接触硅部分的第一远端的第一掺杂的外延硅纳米线延伸；以及漏极区域，包括接触硅部分的第二远端的第二掺杂的外延硅纳米线延伸。
在本发明的又一方面中，纳米线场效应晶体管(FET)器件包括：布置在半导体衬底上的沟道区域，包括具有第一远端和第二远端的硅部分，该硅部分由圆周地布置在该硅部分上的栅极结构包围；第一腔，由硅部分的第一远端、半导体衬底和栅极结构的内径限定；第二腔，由硅部分的第二远端、半导体衬底和栅极结构的内径限定；源极区域，包括从第一腔中硅部分的第一远端外延延伸的第一掺杂的外延硅纳米线延伸；以及漏极区域，包括从第二腔中硅部分的第二远端外延延伸的第二掺杂的外延硅纳米线延伸。
通过本发明的技术实现附加的特征和优势。在此详细描述本发明的其他一些实施例和方面，并且这些实施例和方面被认为是要求保护的本发明的一部分。为了更好地理解具有优势和特征的本发明，参见说明书和附图。
附图说明
在说明书末尾的权利要求书中具体指出和清楚限定被视为本发明的主题。通过下面结合所附附图的具体描述，本发明的前述和其他特征以及优势将变得明显，在附图中：
图1至图12B示出了用于形成场效应晶体管(FET)器件的示例性方法。
图13A至图14B示出了用于形成场效应晶体管(FET)器件的备选示例性方法。
具体实施方式
现在参见图1，在布置在硅衬底100上的掩埋氧化物(BOX)层104上限定绝缘体上硅(SOI)部分102。SOI部分102包括SOI衬垫区域106、SOI衬垫区域108和纳米线部分109。可以通过使用光刻并且之后通过诸如例如反应离子蚀刻(RIE)之类的蚀刻工艺来图案化SOI部分102。
图2示出了在减小纳米线110的直径的氧化工艺之后布置在BOX层104上的纳米线110。例如可以通过纳米线110的氧化之后对生长的氧化物的蚀刻来执行纳米线110的直径的减小。可以重复氧化和蚀刻工艺以实现期望的纳米线110的直径。一旦纳米线110的直径已减小，则在纳米线110的沟道区域之上形成栅极(下文描述)。
如下文进一步详细描述的那样，图3A示出了在纳米线110上形成并且由多晶硅层(覆盖层)404覆盖的栅极402。在多晶硅层404之上沉积诸如例如氮化硅(Si3N4)之类的硬掩模层406。可以通过以下步骤来形成多晶硅层404和硬掩模层406：在BOX层104和SOI部分102之上沉积多晶硅材料、在多晶硅材料之上沉积硬掩模材料并且通过RIE刻蚀来形成如图3A所示的多晶硅层404和硬掩模层406。可以通过产生栅极402的直立侧壁的定向蚀刻来执行栅极402的蚀刻。
图3B示出了示例性备选布置的立体图，其包括形成在SOI衬垫区域106和108之间的纳米线110上的多个栅极402。可以使用与上述用于制造单行栅极402线的方法类似的方法来执行图3B中所示的布置的制造，并且示出了可以如何使用本文所述的方法在SOI衬垫区域106和108之间的纳米线上形成任何数量的器件。
图4示出了沿(图3A的)线A-A的栅极402的截面图。通过在纳米线110的沟道部分上沉积诸如氧化硅(SiO2)之类的第一栅极电介质层502形成栅极402。在第一栅极电介质层502上形成诸如例如氧化铪(HfO2)之类的第二栅极电介质504。在第二栅极电介质层504上形成诸如例如氮化钛(TaN)之类的金属层506。金属层506由(图3A的)多晶硅层404包围。使用诸如硼(p型)或磷(n型)之类的杂质掺杂多晶硅层404使得多晶硅层404导电。
图5A和图5B示出了沿多晶硅层404的相对侧形成的间隔物部分604。通过沉积诸如氮化硅之类的毯式电介质膜并且使用RIE从所有的水平表面处蚀刻电介质膜来形成间隔物。环绕纳米线110的从多晶硅层404延伸的部分形成间隔物壁604，并且间隔物壁604包围纳米线110的一部分。图5A和图5B包括在纳米线110之下以及在(图2的)底切区域202中形成的间隔物部分602。
图6A示出了(图5A的)截面图。图6B示出了图5B的示例性备选布置的类似截面图。
图7A和图7B示出了在移除(图6A中所示的)纳米线110的露出部分与SOI衬垫区域106和108的选择性RIE工艺之后所得结构的截面图。选择性RIE工艺的示例包括基于HBr化学反应的RIE，该RIE在蚀刻硅的同时选择性地减少对诸如氧化硅和氮化硅之类的电介质的蚀刻。纳米线110的由间隔物壁604包围的部分未被蚀刻，并且具有由间隔物壁604限定的露出的截面。
图8A和图8B示出了在选择性外延硅生长以形成外延纳米线延伸902(纳米线延伸)之后所得结构的截面图。从纳米线110的由间隔物壁604包围的露出的截面部分外延生长纳米线延伸902。通过外延生长例如可以为n型或p型掺杂的原位掺杂的硅(Si)或锗硅(SiGe)来形成纳米线延伸902。原位掺杂的外延工艺形成纳米线FET的源极区域和漏极区域。例如，可以使用化学气相沉积(CVD)反应器来执行外延生长。用于硅外延的前驱物包括SiCl4、与HCl结合的SiH4。使用氯允许仅在露出的硅表面上选择性沉积硅。用于SiGe的前驱物可以是GeH4，其可以在没有HCl的情形下获得沉积选择性。用于掺杂剂的前驱物可以包括用于n型掺杂的PH3或AsH3和用于p型掺杂的B2H6。针对纯硅沉积，沉积温度范围可以从550℃到1000℃，而针对纯Ge沉积可以低至300℃。
图9A至图10B示出了用于制造在同一芯片上制造有N-FET和P-FET的互补型金属氧化物半导体(CMOS)的示例方法。由于N-FET和P-FET具有不同掺杂剂类型的纳米线延伸，因此单独地生长N-FET器件和P-FET器件。参见图9A，示出了N-FET器件和P-FET器件。N-FET由外延阻挡掩模1001覆盖，该掩模1001阻挡从纳米线110的露出的截面部分的生长。外延阻挡掩模1001例如可以是被图案化以覆盖N-FET器件的沉积的氧化膜。使纳米线110的P-FET截面部分露出，从而允许使用与上述的工艺类似的选择性外延生长硅沉积工艺形成p+掺杂的纳米线延伸902P。图9B示出了针对多个N-FET器件和P-FET器件的与图9A中描述的类似工艺。
参见图10A和图10B，在生长(图9A和图9B中的)p+掺杂的纳米线延伸902P之后，移除外延阻挡掩模1001，并且沉积且图案化第二外延阻挡掩模1101以覆盖P-FET和p+掺杂的纳米线延伸902P。使用利用n型原位掺杂的选择性外延来形成n+掺杂的纳米线延伸902N。一旦形成了n+掺杂的纳米线延伸902N，则可以移除第二外延阻挡掩模1101。可以选择形成P-FET和N-FET纳米线延伸902的顺序以最小化在生长第二纳米线延伸期间在第一生长的延伸中的掺杂剂的扩散。因此，可以在形成p+掺杂的纳米线延伸902P之前形成n+掺杂的纳米线延伸902N的外延。由于可以在单独的处理步骤中执行纳米线延伸902的形成，因此延伸的组成可以不同。例如，针对P-FET器件可以形成SiGe纳米线延伸，而针对N-FET器件可以形成纯硅纳米线延伸。
图11A和图11B示出了在(在上述的纳米线延伸902生长之后执行的)热工艺之后所得结构的示例，该热工艺将掺杂的离子从纳米线延伸902扩散进入纳米线110的由间隔物壁604和栅极404包围以与器件重叠的区域1202中。纳米线延伸902在生长时均匀地掺杂，从而在离子从纳米线延伸902扩散进入区域1202中之后在纳米线110的区域1202中形成均匀掺杂的分布。对于(在上面的图9A至图10B中描述的)CMOS器件而言，可以执行类似的热工艺。当n型掺杂剂和p型掺杂剂扩散特性类似时，针对PFET器件和NFET器件两者将得到纳米线110的类似掺杂区域。当n型掺杂剂和p型掺杂剂扩散特性不相类似时，n型掺杂剂和p型掺杂剂的渗透将在纳米线110中形成不相类似的区域1202。可以在快速热退火(RTA)室中执行热工艺。例如可以在如下条件下执行热工艺：退火温度在900℃至1100℃之间、在N2气体环境中维持0至10秒。退火温度速率的范围例如可以在50℃/秒至300℃/秒之间。
图12A和图12B示出了在纳米线延伸902上和在多晶硅层404之上形成硅化物1302的硅化之后的所得结构。硅化物形成金属的示例包括Ni、Pt、Co以及诸如NiPt之类的合金。当使用Ni时，因其低阻率而形成NiSi相。例如，形成温度包括400℃至600℃。一旦执行了硅化工艺，则可以形成覆盖层和用于连接性的过孔(未示出)。
图13A至图14B示出了用于形成纳米线FET的备选示例性方法。该备选示例性方法类似于上面在图1至图12B中描述的方法。然而，当蚀刻纳米线110以移除纳米线110的露出部分时，蚀刻工艺移除了纳米线110的由间隔物壁604和栅极404包围的一部分，以使纳米线110凹陷到栅极402中，并且形成由栅极402、纳米线110和间隔物壁604限定的腔1402。图13A和图13B示出了所得结构的截面图。
形成腔1402的侧向蚀刻工艺可以基于时间。间隔物604的宽度变化可以导致凹陷的纳米线110的边缘的位置变化。在腔1402中的蚀刻速率取决于腔的尺寸，其中较窄孔对应于较慢的蚀刻速率。因此，纳米线尺寸的变化将导致腔1402的深度变化。
可以通过在形成(图5A和图5B中的)间隔物604之前使用离子(例如硅离子、锗离子和甚至不导致非晶化的诸如硼之类的掺杂剂)轰击纳米线110的露出端部来减小上述变化。纳米线110的被轰击部分的蚀刻速率比纳米线110的由栅极材料402保护的未露出部分的蚀刻速率快若干倍。因此，当蚀刻时，腔1402变成与栅极402的侧壁自对准。
如果在提升的温度下执行间隔物604的沉积，则沉积工艺可以使露出的纳米线110部分(已被离子轰击的部分)退火并且增加露出的纳米线110部分的抗蚀刻性。对于硅纳米线110而言，可以在较低温度(例如低于500℃)下形成间隔物604以避免使纳米线110的经轰击的部分退火。如果使用其他材料形成所用的纳米线110，则间隔物604的形成温度可以较高。适合间隔物604的高温沉积的备选包括：在沉积间隔物604之后，使用损害纳米线110的由间隔物604包封的部分的离子能以倾斜的角度向衬底100执行离子注入。
参见图14A和图14B，其示出了具有通过与上面在图8A和图8B中描述的工艺类似的原位掺杂的外延硅生长工艺形成的纳米线延伸1502的所得结构的截面图。外延硅生长在(图13A和图13B的)腔1402中从栅极402中露出的纳米线110开始以形成纳米线延伸1502。一旦形成了纳米线延伸1502，可以通过例如激光或闪速退火工艺活化掺杂。激光或闪速退火可以降低离子向栅极402的沟道区域1501中的扩散，并且导致在纳米线延伸1502中的高均匀浓度掺杂以及在纳米线110中的突变结。一旦离子被活化，则可以执行与上面在图12A和图12B中描述的工艺类似的硅化，并且可以形成覆盖层和用于连接性的过孔(未示出)。
本文所使用的术语仅出于描述特定实施例的目的，并且并非旨在限制本发明。如本文所用，除非上下文另有清楚指示，否则单数形式“一”、“一个”和“一种”旨在还包括复数形式。还将理解，术语“包括”和/或“包含”在说明书中使用时指定所陈述的特征、整体、步骤、操作、元件和/或部件的存在，但是不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在和添加。
下面权利要求书中的所有功能元素加装置或步骤的对应结构、材料、动作和等同物旨在包括用于与在权利要求书中具体限定的其他元素组合地执行功能的任何结构、材料或动作。已出于说明和描述的目的展示了本发明的说明书，但是其并非旨在穷尽本发明或将本发明限制为所公开的形式。在不偏离本发明的范围和精神的情形下，许多修改和变化对于本领域技术人员将是显而易见的。为了最好地说明本发明的原理和实际应用以及使得本领域技术人员能够理解本发明具有适配于所构思的特定用途的各种修改的各种实施例而选择和描述了实施例。
本文描绘的图仅是一个示例。可以存在对本文描述的这些图或步骤(或操作)的许多变化，而不偏离本发明。例如，可以以不同顺序执行步骤或可以添加、删除或修改步骤。所有这些变化被视为是要求保护的本发明的一部分。
虽然已经描述了本发明的一些优选实施例，但是将理解，当前和未来本领域技术人员可以做出落入下文权利要求书范围的各种改进和增强。这些权利要求应该被解释为维持首先描述的本发明的适当保护。

Claims (25)

1.一种用于形成纳米线场效应晶体管(FET)器件的方法，所述方法包括：
在半导体衬底上形成纳米线；
在所述纳米线的第一部分上形成第一栅极结构；
形成与所述第一栅极结构的侧壁相邻并且在所述纳米线的从所述第一栅极结构延伸的部分之上的第一保护性间隔物；
移除所述纳米线的未受所述第一间隔物保护的露出部分；以及
在所述纳米线的露出的截面上外延生长掺杂的半导体材料以形成第一源极区域和第一漏极区域，其中所述外延生长的掺杂的半导体材料被均匀掺杂；
加热所述器件以将掺杂剂从所述掺杂的半导体材料向所述纳米线的部分中扩散。
2.根据权利要求1所述的方法，其中所述方法还包括：
在所述纳米线的第二部分上形成第二栅极结构；
形成与所述第二栅极结构的侧壁相邻并且在所述纳米线的从所述第二栅极结构延伸的部分之上的第二保护性间隔物；
移除所述纳米线的未受所述第二间隔物保护的露出部分；
在所述纳米线的露出截面上外延生长掺杂的半导体材料以形成所述第一源极区域和所述第一漏极区域之前，在所述第二栅极结构和所述第二保护性间隔物之上沉积第一保护性掩模；
移除所述第一保护性掩模；
在所述第一栅极结构、所述第一保护性间隔物、所述第一源极区域和所述第一漏极区域之上沉积第二保护性掩模；以及
在所述第二栅极结构的所述纳米线的露出截面上外延生长掺杂的半导体材料以形成第二源极区域和第二漏极区域。
3.根据权利要求2所述的方法，其中所述第一源极区域和所述第一漏极区域的外延生长的掺杂的半导体材料是p型掺杂的材料。
4.根据权利要求2所述的方法，其中所述第二源极区域和所述第二漏极区域的所述外延生长的掺杂的半导体材料是n型掺杂的材料。
5.根据权利要求1所述的方法，其中所述第一栅极结构包括布置在所述纳米线的沟道部分上的氧化硅层、布置在所述氧化硅层上的电介质层以及布置在所述电介质层上的金属层。
6.根据权利要求1所述的方法，其中所述第一栅极结构被形成在所述纳米线的栅极部分之上的圆周层中。
7.根据权利要求1所述的方法，其中所述第一保护性间隔物包括氮化物材料。
8.一种用于纳米线场效应晶体管(FET)器件的方法，所述方法包括：
在半导体衬底上形成纳米线；
在所述纳米线的一部分上形成栅极结构；
形成与所述栅极结构的侧壁相邻并且在所述纳米线的从所述栅极结构延伸的部分之上的保护性间隔物；
移除所述纳米线的露出部分以形成由被所述栅极结构包围的所述纳米线、所述半导体衬底和所述间隔物限定的腔；以及
在所述腔中从所述纳米线的露出截面外延生长掺杂的半导体材料，其中所述外延生长的掺杂的半导体材料被均匀掺杂；
加热所述器件以将掺杂剂从所述掺杂的半导体材料向所述纳米线的部分中扩散。
9.根据权利要求8所述的方法，其中所述方法还包括：
在形成与所述栅极的侧壁相邻并且在所述纳米线的从所述栅极延伸的部分之上的保护性间隔物之前，使用离子对所述纳米线的露出部分进行注入。
10.根据权利要求8所述的方法，其中所述方法还包括：
在形成与所述栅极的侧壁相邻并且在所述纳米线的从所述栅极延伸的部分之上的保护性间隔物之前，使用离子对所述纳米线的露出部分进行注入以增加所述纳米线的所述露出部分的蚀刻速率性质。
11.根据权利要求8所述的方法，其中在低于500℃的温度下形成与所述栅极侧壁相邻并且在纳米线的从所述栅极延伸的部分之上的所述保护性间隔物。
12.根据权利要求8或权利要求1所述的方法，其中所述外延生长的掺杂的半导体材料是n型掺杂的材料。
13.根据权利要求8或权利要求1所述的方法，其中所述外延生长的掺杂的半导体材料是p型掺杂的材料。
14.根据权利要求8所述的方法，其中所述外延生长的掺杂的半导体材料是硅。
15.根据权利要求8或权利要求1所述的方法，其中所述外延生长的掺杂的半导体材料是SiGe合金。
16.根据权利要求8所述的方法，其中所述栅极结构包括布置在所述纳米线的沟道部分上的氧化硅层、布置在所述氧化硅层上的电介质层和布置在所述电介质层上的金属层。
17.根据权利要求8所述的方法，其中所述栅极结构被形成在所述纳米线的栅极部分上的圆周层中。
18.根据权利要求8所述的方法，其中所述保护性间隔物包括氮化物材料。
19.根据权利要求8或权利要求1所述的方法，其中所述外延生长的掺杂的半导体材料是原位掺杂的材料。
20.一种纳米线场效应晶体管(FET)器件，包括：
沟道区域，包括布置在半导体衬底上的具有从所述沟道区域延伸的第一远端和从所述沟道区域延伸的第二远端的硅部分，所述硅部分由圆周地布置在所述硅部分上的栅极结构部分地包围；
源极区域，包括接触所述硅部分的所述第一远端的第一掺杂的外延硅纳米线延伸；以及
漏极区域，包括接触所述硅部分的所述第二远端的第二掺杂的外延硅纳米线延伸，
其中使用离子均匀地掺杂所述第一外延硅纳米线延伸和所述第二外延硅纳米线延伸，并且通过加热所述器件以将离子从所述掺杂的外延硅纳米线向所述硅部分中扩散。
21.根据权利要求20的器件，其中使用从所述第一外延硅纳米线延伸扩散的离子掺杂所述硅部分的第一远端的部分，并且使用从所述第二外延硅纳米线延伸扩散的离子掺杂所述硅部分的第二远端的部分。
22.根据权利要求20的器件，其中所述硅部分为椭圆形形状。
23.根据权利要求20的器件，其中所述硅部分为圆柱形形状。
24.一种纳米线场效应晶体管(FET)器件，包括：
布置在半导体衬底上的沟道区域，包括具有第一远端和第二远端的硅部分，所述硅部分由圆周地布置在所述硅部分上的栅极结构包围；
第一腔，由所述硅部分的第一远端、所述半导体衬底和所述栅极结构的内径限定；
第二腔，由所述硅部分的第二远端、所述半导体衬底和所述栅极结构的内径限定；
源极区域，包括从所述第一腔中所述硅部分的第一远端外延延伸的第一掺杂的外延硅纳米线延伸；以及
漏极区域，包括从所述第二腔中所述硅部分的第二远端外延延伸的第二掺杂外延硅纳米线延伸，
其中所述第一外延硅纳米线和所述第二外延硅纳米线被均匀掺杂，并且通过加热所述器件以将掺杂剂从所述外延硅纳米线向所述硅部分中扩散。
25.根据权利要求24所述的器件，其中所述第一外延硅纳米线延伸填充所述第一腔，而所述第二外延硅纳米线填充所述第二腔。
CN201080054741.8A 2009-12-04 2010-11-08 Ω形状的纳米线场效应晶体管 Active CN102640270B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/631,205 US8129247B2 (en) 2009-12-04 2009-12-04 Omega shaped nanowire field effect transistors
US12/631,205 2009-12-04
PCT/EP2010/066961 WO2011067069A1 (en) 2009-12-04 2010-11-08 Omega shaped nanowire field effect transistors

Publications (2)

Publication Number Publication Date
CN102640270A CN102640270A (zh) 2012-08-15
CN102640270B true CN102640270B (zh) 2015-08-12

Family

ID=43127115

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201080054741.8A Active CN102640270B (zh) 2009-12-04 2010-11-08 Ω形状的纳米线场效应晶体管

Country Status (3)

Country Link
US (2) US8129247B2 (zh)
CN (1) CN102640270B (zh)
WO (1) WO2011067069A1 (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7884004B2 (en) * 2009-02-04 2011-02-08 International Business Machines Corporation Maskless process for suspending and thinning nanowires
US8455334B2 (en) 2009-12-04 2013-06-04 International Business Machines Corporation Planar and nanowire field effect transistors
US8143113B2 (en) * 2009-12-04 2012-03-27 International Business Machines Corporation Omega shaped nanowire tunnel field effect transistors fabrication
US8129247B2 (en) 2009-12-04 2012-03-06 International Business Machines Corporation Omega shaped nanowire field effect transistors
US8722492B2 (en) 2010-01-08 2014-05-13 International Business Machines Corporation Nanowire pin tunnel field effect devices
US8324940B2 (en) 2010-04-13 2012-12-04 International Business Machines Corporation Nanowire circuits in matched devices
US8361907B2 (en) 2010-05-10 2013-01-29 International Business Machines Corporation Directionally etched nanowire field effect transistors
US8324030B2 (en) 2010-05-12 2012-12-04 International Business Machines Corporation Nanowire tunnel field effect transistors
US8394710B2 (en) * 2010-06-21 2013-03-12 International Business Machines Corporation Semiconductor devices fabricated by doped material layer as dopant source
US8835231B2 (en) 2010-08-16 2014-09-16 International Business Machines Corporation Methods of forming contacts for nanowire field effect transistors
US8536563B2 (en) 2010-09-17 2013-09-17 International Business Machines Corporation Nanowire field effect transistors
US20130026575A1 (en) * 2011-07-28 2013-01-31 Synopsys, Inc. Threshold adjustment of transistors by controlled s/d underlap
US8648330B2 (en) * 2012-01-05 2014-02-11 International Business Machines Corporation Nanowire field effect transistors
US8900959B2 (en) 2013-03-12 2014-12-02 International Business Machines Corporation Non-replacement gate nanomesh field effect transistor with pad regions
US10304956B2 (en) 2013-12-27 2019-05-28 Intel Corporation Diffused tip extension transistor
US9263260B1 (en) * 2014-12-16 2016-02-16 International Business Machines Corporation Nanowire field effect transistor with inner and outer gates
CN105810730B (zh) * 2014-12-29 2018-12-07 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US10374086B2 (en) * 2015-12-04 2019-08-06 The Regents Of The University Of California 3D transistor having a gate stack including a ferroelectric film
US10734511B2 (en) * 2016-03-31 2020-08-04 Intel Corporation High mobility asymmetric field effect transistors with a band-offset semiconductor drain spacer
CN108695382B (zh) * 2017-04-07 2021-07-06 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
US10651291B2 (en) 2017-08-18 2020-05-12 Globalfoundries Inc. Inner spacer formation in a nanosheet field-effect transistor
US10896956B2 (en) * 2017-12-22 2021-01-19 Commissariat A L'energie Atomique Et Aux Energies Alternatives Field effect transistor with reduced contact resistance
US10686050B2 (en) * 2018-09-26 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US11217694B2 (en) * 2019-03-18 2022-01-04 Shanghai Industrial Μtechnology Research Institute Field-effect transistor and method for manufacturing the same
US10923348B2 (en) * 2019-05-29 2021-02-16 International Business Machines Corporation Gate-all-around field effect transistor using template-assisted-slective-epitaxy

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7608489B2 (en) * 2006-04-28 2009-10-27 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture

Family Cites Families (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4638769A (en) 1985-03-18 1987-01-27 Caterpillar Inc. Engine having a multipiece cylinder block
US4995001A (en) * 1988-10-31 1991-02-19 International Business Machines Corporation Memory cell and read circuit
JPH04299569A (ja) * 1991-03-27 1992-10-22 Nec Corp Ｓｏｉｓの製造方法及びトランジスタとその製造方法
US5308445A (en) * 1991-10-23 1994-05-03 Rohm Co., Ltd. Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate
JPH0637302A (ja) * 1992-07-14 1994-02-10 Mitsuteru Kimura トンネルトランジスタ
JP3319472B2 (ja) * 1992-12-07 2002-09-03 富士通株式会社 半導体装置とその製造方法
US6365465B1 (en) * 1999-03-19 2002-04-02 International Business Machines Corporation Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques
US6653209B1 (en) * 1999-09-30 2003-11-25 Canon Kabushiki Kaisha Method of producing silicon thin film, method of constructing SOI substrate and semiconductor device
US6642115B1 (en) * 2000-05-15 2003-11-04 International Business Machines Corporation Double-gate FET with planarized surfaces and self-aligned silicides
US6982460B1 (en) * 2000-07-07 2006-01-03 International Business Machines Corporation Self-aligned gate MOSFET with separate gates
US20060175601A1 (en) * 2000-08-22 2006-08-10 President And Fellows Of Harvard College Nanoscale wires and related devices
CA2442985C (en) * 2001-03-30 2016-05-31 The Regents Of The University Of California Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
DE10118405A1 (de) 2001-04-12 2002-10-24 Infineon Technologies Ag Heterostruktur-Bauelement
WO2003010837A1 (en) 2001-07-26 2003-02-06 Technische Universiteit Delft Electronic device using carbon nanotubes
US6891227B2 (en) * 2002-03-20 2005-05-10 International Business Machines Corporation Self-aligned nanotube field effect transistor and method of fabricating same
US6872645B2 (en) * 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
US6815750B1 (en) * 2002-05-22 2004-11-09 Hewlett-Packard Development Company, L.P. Field effect transistor with channel extending through layers on a substrate
US6919740B2 (en) * 2003-01-31 2005-07-19 Hewlett-Packard Development Company, Lp. Molecular-junction-nanowire-crossbar-based inverter, latch, and flip-flop circuits, and more complex circuits composed, in part, from molecular-junction-nanowire-crossbar-based inverter, latch, and flip-flop circuits
US6855606B2 (en) * 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US6903013B2 (en) * 2003-05-16 2005-06-07 Chartered Semiconductor Manufacturing Ltd. Method to fill a trench and tunnel by using ALD seed layer and electroless plating
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US6835618B1 (en) * 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US7060576B2 (en) 2003-10-24 2006-06-13 Intel Corporation Epitaxially deposited source/drain
US7311776B2 (en) * 2003-12-30 2007-12-25 The Regents Of The University Of California Localized synthesis and self-assembly of nanostructures
KR100625177B1 (ko) * 2004-05-25 2006-09-20 삼성전자주식회사 멀티-브리지 채널형 모오스 트랜지스터의 제조 방법
US7180107B2 (en) * 2004-05-25 2007-02-20 International Business Machines Corporation Method of fabricating a tunneling nanotube field effect transistor
US7443025B2 (en) * 2004-06-07 2008-10-28 Broadcom Corporation Thermally improved placement of power-dissipating components onto a circuit board
KR100618831B1 (ko) * 2004-06-08 2006-09-08 삼성전자주식회사 게이트 올 어라운드형 반도체소자 및 그 제조방법
US7452778B2 (en) * 2004-06-10 2008-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-wire devices and methods of fabrication
US8288813B2 (en) * 2004-08-13 2012-10-16 Infineon Technologies Ag Integrated memory device having columns having multiple bit lines
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US7473943B2 (en) 2004-10-15 2009-01-06 Nanosys, Inc. Gate configuration for nanowire electronic devices
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7402872B2 (en) * 2004-11-18 2008-07-22 Intel Corporation Method for forming an integrated circuit
US7598516B2 (en) * 2005-01-07 2009-10-06 International Business Machines Corporation Self-aligned process for nanotube/nanowire FETs
US20080121932A1 (en) * 2006-09-18 2008-05-29 Pushkar Ranade Active regions with compatible dielectric layers
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
KR100594327B1 (ko) 2005-03-24 2006-06-30 삼성전자주식회사 라운드 형태의 단면을 가지는 나노와이어를 구비한 반도체소자 및 그 제조 방법
KR101127132B1 (ko) * 2005-05-13 2012-03-21 삼성전자주식회사 실리콘 나노와이어 기판 및 그 제조방법, 그리고 이를이용한 박막 트랜지스터의 제조방법
US7230286B2 (en) * 2005-05-23 2007-06-12 International Business Machines Corporation Vertical FET with nanowire channels and a silicided bottom contact
WO2006132659A2 (en) * 2005-06-06 2006-12-14 President And Fellows Of Harvard College Nanowire heterostructures
US7387946B2 (en) * 2005-06-07 2008-06-17 Freescale Semiconductor, Inc. Method of fabricating a substrate for a planar, double-gated, transistor process
KR100618900B1 (ko) 2005-06-13 2006-09-01 삼성전자주식회사 다중 채널을 갖는 모스 전계효과 트랜지스터의 제조방법 및그에 따라 제조된 다중 채널을 갖는 모스 전계효과트랜지스터
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7190050B2 (en) * 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
US7354831B2 (en) * 2005-08-08 2008-04-08 Freescale Semiconductor, Inc. Multi-channel transistor structure and method of making thereof
US7452759B2 (en) * 2005-11-29 2008-11-18 Micron Technology, Inc. Carbon nanotube field effect transistor and methods for making same
US7871912B2 (en) * 2005-12-13 2011-01-18 Versatilis Llc Methods of making semiconductor-based electronic devices by forming freestanding semiconductor structures
US7498211B2 (en) * 2005-12-28 2009-03-03 Intel Corporation Independently controlled, double gate nanowire memory cell with self-aligned contacts
US7449373B2 (en) * 2006-03-31 2008-11-11 Intel Corporation Method of ion implanting for tri-gate devices
US7772071B2 (en) * 2006-05-17 2010-08-10 Chartered Semiconductor Manufacturing Ltd. Strained channel transistor and method of fabrication thereof
US7880160B2 (en) * 2006-05-22 2011-02-01 Qimonda Ag Memory using tunneling field effect transistors
US7456068B2 (en) * 2006-06-08 2008-11-25 Intel Corporation Forming ultra-shallow junctions
US7629603B2 (en) * 2006-06-09 2009-12-08 Intel Corporation Strain-inducing semiconductor regions
US20080014689A1 (en) * 2006-07-07 2008-01-17 Texas Instruments Incorporated Method for making planar nanowire surround gate mosfet
US7999251B2 (en) * 2006-09-11 2011-08-16 International Business Machines Corporation Nanowire MOSFET with doped epitaxial contacts for source and drain
KR100745769B1 (ko) 2006-09-11 2007-08-02 삼성전자주식회사 나노와이어 전기기계 스위칭 소자 및 그 제조방법, 상기나노와이어 전기기계 소자를 이용한 전기기계 메모리 소자
US7893476B2 (en) * 2006-09-15 2011-02-22 Imec Tunnel effect transistors based on silicon nanowires
EP1900681B1 (en) * 2006-09-15 2017-03-15 Imec Tunnel Field-Effect Transistors based on silicon nanowires
KR100801063B1 (ko) * 2006-10-02 2008-02-04 삼성전자주식회사 게이트 올 어라운드형 반도체 장치 및 그 제조 방법
US7498265B2 (en) 2006-10-04 2009-03-03 Micron Technology, Inc. Epitaxial silicon growth
KR100757328B1 (ko) * 2006-10-04 2007-09-11 삼성전자주식회사 단전자 트랜지스터 및 그 제조 방법
US20080128760A1 (en) 2006-12-04 2008-06-05 Electronics And Telecommunications Research Institute Schottky barrier nanowire field effect transistor and method for fabricating the same
US20080135949A1 (en) 2006-12-08 2008-06-12 Agency For Science, Technology And Research Stacked silicon-germanium nanowire structure and method of forming the same
KR100881185B1 (ko) * 2006-12-20 2009-02-05 삼성전자주식회사 비휘발성 메모리 소자 및 그 동작 방법
US8049203B2 (en) * 2006-12-22 2011-11-01 Qunano Ab Nanoelectronic structure and method of producing such
JP5100137B2 (ja) * 2007-01-26 2012-12-19 株式会社東芝 半導体装置の製造方法および半導体装置
US20090217216A1 (en) 2007-02-28 2009-08-27 Motorola, Inc. Carbon nanotube circuits design methodology
JP2008252086A (ja) * 2007-03-12 2008-10-16 Interuniv Micro Electronica Centrum Vzw ゲートトンネル障壁を持つトンネル電界効果トランジスタ
US7859036B2 (en) * 2007-04-05 2010-12-28 Micron Technology, Inc. Memory devices having electrodes comprising nanowires, systems including same and methods of forming same
US7871851B2 (en) 2007-05-25 2011-01-18 RF Nano Method for integrating nanotube devices with CMOS for RF/analog SoC applications
US7812370B2 (en) * 2007-07-25 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling
US8154127B1 (en) 2007-07-30 2012-04-10 Hewlett-Packard Development Company, L.P. Optical device and method of making the same
US7534675B2 (en) * 2007-09-05 2009-05-19 International Business Machiens Corporation Techniques for fabricating nanowire field-effect transistors
US7795677B2 (en) * 2007-09-05 2010-09-14 International Business Machines Corporation Nanowire field-effect transistors
JP4966153B2 (ja) * 2007-10-05 2012-07-04 株式会社東芝 電界効果トランジスタおよびその製造方法
KR20090044799A (ko) 2007-11-01 2009-05-07 삼성전자주식회사 액티브 핀의 제조 방법 및 이를 포함하는 트랜지스터
JP2009130167A (ja) * 2007-11-26 2009-06-11 Renesas Technology Corp 半導体装置およびその製造方法
KR101014926B1 (ko) * 2008-05-20 2011-02-15 주식회사 하이닉스반도체 불휘발성 메모리 장치의 프로그램 검증 방법
US7834345B2 (en) * 2008-09-05 2010-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Tunnel field-effect transistors with superlattice channels
US8362604B2 (en) 2008-12-04 2013-01-29 Ecole Polytechnique Federale De Lausanne (Epfl) Ferroelectric tunnel FET switch and memory
US7884004B2 (en) 2009-02-04 2011-02-08 International Business Machines Corporation Maskless process for suspending and thinning nanowires
KR20100094192A (ko) 2009-02-18 2010-08-26 삼성전자주식회사 탄소나노튜브 박막을 이용한 에스램
US8129247B2 (en) 2009-12-04 2012-03-06 International Business Machines Corporation Omega shaped nanowire field effect transistors
US8097515B2 (en) 2009-12-04 2012-01-17 International Business Machines Corporation Self-aligned contacts for nanowire field effect transistors
US8173993B2 (en) 2009-12-04 2012-05-08 International Business Machines Corporation Gate-all-around nanowire tunnel field effect transistors
US20110147840A1 (en) 2009-12-23 2011-06-23 Cea Stephen M Wrap-around contacts for finfet and tri-gate devices
US8420455B2 (en) 2010-05-12 2013-04-16 International Business Machines Corporation Generation of multiple diameter nanowire field effect transistors
US8338280B2 (en) 2010-07-08 2012-12-25 Globalfoundries Singapore Pte. Ltd. Method for fabricating nano devices
US8716072B2 (en) 2011-07-25 2014-05-06 International Business Machines Corporation Hybrid CMOS technology with nanowire devices and double gated planar devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7608489B2 (en) * 2006-04-28 2009-10-27 International Business Machines Corporation High performance stress-enhance MOSFET and method of manufacture

Also Published As

Publication number Publication date
US20120146000A1 (en) 2012-06-14
CN102640270A (zh) 2012-08-15
US8680589B2 (en) 2014-03-25
US20110133164A1 (en) 2011-06-09
WO2011067069A1 (en) 2011-06-09
US8129247B2 (en) 2012-03-06

Similar Documents

Publication Publication Date Title
CN102640270B (zh) Ω形状的纳米线场效应晶体管
CN102640271B (zh) 全环栅纳米线场效应晶体管
US8097515B2 (en) Self-aligned contacts for nanowire field effect transistors
US8173993B2 (en) Gate-all-around nanowire tunnel field effect transistors
US8507892B2 (en) Omega shaped nanowire tunnel field effect transistors
US8455334B2 (en) Planar and nanowire field effect transistors
CN101281926B (zh) 半导体结构
CN102983165B (zh) 控制沟道厚度的FinFET设计
US8324030B2 (en) Nanowire tunnel field effect transistors
US8674342B2 (en) Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers
US9105482B2 (en) Nanowire PIN tunnel field effect devices
US8558219B2 (en) Nanowire field effect transistors
US20150041897A1 (en) Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet
US20070281411A1 (en) Formation of strain-inducing films
US20170025509A1 (en) Strained silicon germanium fin with controlled junction for finfet devices
TWI739152B (zh) 具有增強局部等向性之磊晶半導體材料生長
WO2008034113A1 (en) Formation of strain-inducing films using hydrogenated amorphous silicon
US8563385B2 (en) Field effect transistor device with raised active regions
CN103779218B (zh) 半导体器件及其制造方法
JP2003243532A (ja) 相補型半導体装置および相補型半導体装置の製造方法
US10290738B2 (en) Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device
CN106960792A (zh) Nmos晶体管及其形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20171113

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171113

Address after: American New York

Patentee after: Core USA second LLC

Address before: New York grams of Armand

Patentee before: International Business Machines Corp.

TR01 Transfer of patent right