CN103715150A - 芯片帽及戴有芯片帽的倒装芯片封装 - Google Patents

芯片帽及戴有芯片帽的倒装芯片封装 Download PDF

Info

Publication number
CN103715150A
CN103715150A CN201310456311.4A CN201310456311A CN103715150A CN 103715150 A CN103715150 A CN 103715150A CN 201310456311 A CN201310456311 A CN 201310456311A CN 103715150 A CN103715150 A CN 103715150A
Authority
CN
China
Prior art keywords
chip
cap
flip
chip cap
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310456311.4A
Other languages
English (en)
Other versions
CN103715150B (zh
Inventor
申宇慈
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CN103715150A publication Critical patent/CN103715150A/zh
Application granted granted Critical
Publication of CN103715150B publication Critical patent/CN103715150B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H01L2924/16153—Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

在本发明中，用于倒装芯片封装的芯片帽和盖有芯片帽的倒装芯片封装被提供。芯片帽的作用是通过紧紧地包住倒装芯片的顶部和侧边来约束芯片在温度变化过程中的热变形。在倒装芯片封装中，倒装芯片和基板之间的CTE（热膨胀系数）不匹配是引起倒装芯片封装的翘曲和可靠性方面的问题的根本原因。当前的发明构思是通过使用芯片帽来约束倒装芯片的热变形，以减少热膨胀系数的不匹配。当使用具有高的热膨胀系数和高模量的芯片帽，盖有芯片帽的倒装芯片具有相对高的整体的热膨胀系数，降低了与基板之间的热膨胀系数的不匹配。其结果是，倒装芯片封装的翘曲和可靠性同时得到根本改善。

Description

芯片帽及戴有芯片帽的倒装芯片封装
技术领域
本发明总体上涉及集成电路的半导体封装。本发明特别涉及用于减少倒装芯片半导体封装的翘曲和提高其可靠性的芯片帽及其应用。
背景技术
由于倒装芯片互连技术能够容纳非常高的单位面积引脚数，其被广泛用于半导体器件封装。倒装芯片封装是最常见的采用倒装芯片互连技术的半导体封装。倒装芯片封装基本上包括一个芯片和一个基板。其中的芯片通过安装在其一侧的导电焊球或铜柱焊球被焊接在基板的一侧。一种用来保护这些焊球的底部填充材料通常被通过毛细管力注入到倒装芯片和基板之间的间隙。根据基板底侧上不同的电触点，倒装芯片封装包括倒装芯片球栅阵列封装（FCBGA），倒装芯片栅格阵列封装（FCLGA）和倒装芯片引脚网格阵列封装（FCPGA）。翘曲是倒装芯片封装使用有机基板时的一个大问题，特别是对于大的基板尺寸和大的芯片尺寸的倒装芯片封装。为了控制倒装芯片封装的翘曲，各种金属加强环或金属盖子被安装在基板上以控制其变形。使用传统的金属加强环或金属盖子可以减少翘曲，但同时也增加了倒装芯片封装内的应力水平，从而导致了一些应力引起的失效问题。
对于使用有机材料基板的倒装芯片封装，基板的热膨胀系数大约是15ppm，而芯片的热膨胀系数大约是为3ppm。如此大的芯片和基板之间的热膨胀系数的不匹配是下列这些问题的根本原因：倒装芯片封装的过量翘曲，在倒装芯片封装的制造过程，可靠性试验或应用中的芯片介电层开裂，焊球桥连或焊球开裂等。
人们一直在尝试各种方法去减少倒装芯片封装的翘曲和提高其可靠性。例如，在现有的发明中，当注入和固化底部填充材料时，人们通过各种类型的夹子去夹紧基板或把倒装芯片和基板保持在一起来减少翘曲。此外，人们也设计了各种类型的加强环或盖子以减少倒装芯片封装基板的翘曲。
图1A和图1B显示了在现有的发明中用于控制倒装芯片封装翘曲的传统类型的盖子。图1A所示的盖子也被称作帽子类型的盖子，其由顶片10，侧壁12和脚边沿14组成。这种帽子类型的盖子可以廉价地通过冲压金属片制造。图1B所示的盖子由顶片20和宽侧壁22组成。图2A，2B和2C显示了使用传统类型盖子的倒装芯片封装。
图2A和图2B所示的倒装芯片封装的盖子的大小和基板相同，并粘附在基板的边缘上。图2C所示的倒装芯片封装的盖子小于基板，并附着在基板的内侧部分。这些传统的倒装芯片封装包括一个芯片32，一个基板36和一个盖子。芯片32和基板36通过焊点38和底部填充材料40获得在电性能和机械上的连接。盖子通过粘接材料34和热界面材料30被粘附在基板36和芯片32上。盖子的主要目的是限制基板36的热变形，以减少其翘曲。在这些传统的倒装芯片封装中，盖子不限制芯片的侧边，而是在芯片和盖子之间有一个空腔。
图3所示的是一个在现有的发明中用于倒装芯片封装的芯片夹，其中倒装芯片52通过焊点54和底部填充材料56连接在基板58上，并且在注入底部填充材料前，为了把芯片固定在基板上，一个芯片夹50被首先粘接在基板上。
图4显示了一个在现有的发明中用于倒装芯片封装的多片散热片70和76。在这个使用多片散热片的倒装芯片封装设计中，芯片72和基板80通过焊点74和底部填充材料78获得在电性能和机械上的连接，多片散热片70和76的其中一片76在注入底部填充材料前被粘附在基板80上，然后在注入底部填充材料后，另一片70再被粘附。
在倒装芯片封装中使用盖子的主要目的是减少基板的翘曲。然而，在现有的发明中，图1A和图1B所示的传统的盖子主要限制图2A，2B和2C所示的倒装芯片封装基板36的变形或翘曲。这种传统盖子的缺点之一是盖子和芯片之间有一个空腔，其结果是由于芯片的侧面32没有被有效地约束，这种用来减小倒装芯片封装翘曲的传统方法的效率不能令人满意。
图3和图4中所示的现有的发明中的基本概念是先在基板上粘附一个芯片夹或多片散热片的一片以防止倒装芯片在底部填充材料注入和固化期间的移动。图3所示的现有的发明中的散热片被称为芯片夹50，它包括一个顶部和一个侧部，为了让底部填充材料流入，其侧部具有至少一个开口。图4所示的现有的发明使用了多片散热片，其特征在于，为了让底部填充材料流入，其第一片76具有至少一个开口，并在注入底部填充材料前被粘附在基板上，而这个多片散热片的第二片在底部填充材料注入芯片和基板的间隙后再被粘附在基板上以封住这个多片散热片的第一片的开口。图3和图4图中所示的现有发明的一个缺点是芯片夹或多片散热片的第一片要在注底部填充材料流入芯片和基板之间的间隙前被粘附在基板上。其结果是，为了让底部填充材料流入，芯片夹或多片散热片的第一片的侧部需要一个或多个开口，从而导致一个复杂的倒装芯片封装装配过程。
本发明介绍一个具有一些本发明性元素的芯片帽及其在倒装芯片半导体封装中的应用。在本发明的戴有芯片帽的倒装芯片封装中，芯片帽不是被粘附在基板上，而是在注底部填充材料进入芯片和基板之间的间隙后被粘附在芯片上，以控制热芯片的热变形。值得注意的是，本发明的芯片帽不仅与芯片的顶部粘接而且也与芯片的侧部粘接，并且在本发明的倒装芯片封装中使用的芯片帽不必留有侧面开口。可以选用高热膨胀系数和高模量的材料，如铜或铜合金来制作芯片帽。这样，戴有芯片帽的芯片（这里简称作戴帽子的芯片）具有相对高的整体热膨胀系数，从而降低了倒装芯片半导体封装中的芯片和基板之间的热膨胀系数的不匹配。其结果是，倒装芯片封装的翘曲被减少或消除，同时倒装芯片封装的可靠性也被提高，而且效率高，成本低。此外，热膨胀系数的不匹配也是引起倒装芯片封装和印刷电路板之间的焊锡球的可靠性问题的根源，所以戴有芯片帽的倒装芯片封装同时提高倒装芯片封装和印刷电路板之间的焊锡球的可靠性。
发明内容
本发明描述了一个具有一些特定元素的芯片帽，戴有芯片帽的倒装芯片封装及其制造方法。
在本发明的一个实施例中，芯片帽由顶片和侧壁组成，其中在侧壁的底部可以有脚边沿，也可以没有脚边沿，并且芯片帽具有这样一些特定元素，包括：1）在芯片帽顶片的内表面和靠近其边缘上开有凹口，（这里简称作边缘凹口），2）在芯片帽顶片的内表面和中间部分有一些凸点（这里简称作中凸点），3）从芯片帽顶片向外延伸的顶部边沿（这里简称作顶边沿），4）从顶部边缘向下延伸的侧支撑壁或侧支撑柱（这里简称作侧支撑壁或侧面支柱）。涉及在本发明中的边缘凹口，中凸点，顶边沿和侧支撑壁及在传统盖子涉中的脚边沿这些术语将在下面结合图片被进一步解释。除了控制倒装芯片封装的翘曲这个主要目的外，在本发明中的芯片帽具有的这些特定元素还可以提高热性能，并减少芯片帽从芯片剥离的风险。
在本发明的另一个实施例中，倒装芯片封装由芯片，基板及芯片帽组成，其特征在于，芯片和芯片帽形成一个戴帽子的芯片，底部填充材料通过毛细管力注入芯片和基板之间的间隙以保护焊点。芯片帽通过粘合剂材料或相同的底部填充材料与芯片粘在一起，从而紧紧地包住芯片的顶部和侧边。
在本发明的另一个实施例中，使用芯片帽的倒装芯片封装的制造方法被描述，其特征在于，组装过程中的主要步骤包括：在基板上附加芯片，在芯片和基板之间的间隙注入底部填充材料，在芯片的上表面或芯片帽的里侧分配一些粘接材料或相同的底部填充材料，把芯片帽通过一定的压力覆盖在芯片上，然后同时固化封装组件。
在现有的发明中，用于减少倒装芯片封装翘曲的传统方法是通过在基板上粘附加强环或盖子来约束倒装芯片封装基板的热变形。本发明的概念是通过给倒装芯片戴一个芯片帽来直接约束芯片的热变形，从而减少倒装芯片封装的翘曲。本发明的精神，可以很容易地扩展为减少其他的半导体封装的翘曲和改善其可靠性。例如，芯片帽可以盖在一个多芯片的组合上，从而形成一个戴帽子的多芯片组件来减少其封装的翘曲。本发明更多的特征和优点将在下面参考实施例被详细描述。
附图说明
图1A和1B是在现有技术中倒装芯片封装使用的传统盖子的示意性横截面视图，其中，图1A所示的盖子具有脚边沿14。
图2A，图2B和图2C所示的是在现有技术中使用传统盖子的倒装芯片封装的示意性横截面视图。
图3所示的是在现有技术中使用一个芯片夹的倒装芯片封装的示意性横截面视图。
图4所示的是在现有技术中使用多片散热片的倒装芯片封装的示意性横截面视图。
图5A-5D所示的是本发明的一个实施例中的芯片帽，其具有边缘凹口140或中凸点180，而图5E-5F所示的是芯片帽的侧壁120可以是一个整片或具有梳齿状结构。
图6A-6C所示的是本发明的一个实施例的芯片帽的的示意性剖视图，其顶部边沿200从芯片帽的顶部100向外延伸，而在图6D和6E所示的芯片帽的顶部边沿200可以是一个整片或几个分开的部分。
图7A-7E所示的是本发明的另一个实施例的芯片帽的的剖视图，其侧支承壁300或侧支承柱300从顶部边沿200向下延伸，而图7F-7G所示的是侧支撑壁300和侧支撑柱300的示意性侧视图。
图8A-8C所示的是在本发明的一个实施例中的戴有芯片帽的倒装芯片封装横的示意性横截面视图。
图9A-9C所示的是在本发明的一个实施例中的戴有芯片帽的倒装芯片封装的示意性横截面视图，其中的芯片帽具有一些本发明的特定元素。
图10所示的是在本发明的一个实施例中的戴有芯片帽的塑料注封倒装芯片封装的示意性横截面视图。
图11所示的是在本发明的一个实施例中的戴有芯片帽的多芯片倒装芯片封装的示意性横截面视图。
图12所示的是在本发明的一个实施例中的戴有芯片帽的倒装芯片封装的组装过程的示意性横截面视图。
图13A所示的是在本发明的一个实施例中的戴有芯片帽的倒装芯片封装的另一个组装过程的示意性横剖视图，而图13B所示的是基于这个组装过程的倒装芯片封装的横截面视图，其中在芯片帽1000周围的底部填充材料具有一个大底部填充圆角900。
具体实施方式
图5A所示的是芯片帽的示意性横截面视图1000，其包括顶部100，侧壁120和在芯片帽顶片的内表面和靠近其边缘的边缘凹口140。使用边缘凹口140的目的是使芯片和芯片帽之间的粘合层的厚度在芯片的边缘部位厚，而在芯片的中间部位薄，这样既减小了芯片帽从芯片边缘开裂的风险，又不显著地影响从芯片到芯片帽的散热性能。图5B所示的是芯片帽的示意性横截面视图1200，其包括顶部100，侧壁120，边缘凹口140和脚边沿160。图5A和5B所示的芯片帽中的边缘凹口140是本发明的一个实施例中的芯片帽的第一个特点。图5C和5D所示的芯片帽1400和1600在芯片帽顶部100的中间部位有一些凸点180，其是本发明的一个实施例中的芯片帽的第二个特点。使用中凸点180的目的类似于使用边缘凹口140的目的，也是为了减小芯片帽从芯片边缘开裂的风险，又不显著地影响从芯片到芯片帽的散热性能。图5E-5F所示的是芯片帽的侧壁120，其可以是一个整片或具有梳齿状结构的多个部分。当芯片帽和芯片粘接在一起，整片形式的侧壁可以更好地约束芯片的热变形，而具有梳齿状结构的侧壁可以更好地减少芯片帽和芯片之间剥离的风险。
图6A，6AB和6C所示的芯片帽1700，1800和1900有一个从芯片帽顶部100向外延伸的顶部边沿200，这是本发明的一个实施例中的第三个特点。顶部边沿200的设计是为了更好的散热。顶部边沿200可以具有任何形状，从它的顶视图看，其可以是一个整片或一些分开的部分。图6D和6E所示的是顶部边沿200的两个例子。图6E所示的由一些分开的部分组成的顶部边沿200可以通过折叠一片材料，如一片金属片廉价地制造。
图7A至7E所示的芯片帽2000，2200，2400，2600和2800有一个从芯片帽顶部100的顶部边沿2300向下延伸的侧面支撑壁或支撑柱300，这是本发明的一个实施例中的第四个特点。当芯片帽由薄的金属片制成时，顶部边沿200可能太柔软，因此使用这个向下延伸的侧面支撑壁或支撑柱300的目的是为了支持顶部边沿200。侧支持壁或支撑柱300只接触基板而不与其粘接。图7F-7G是侧支撑壁或支撑柱300的侧视图，其特征在于，侧支撑壁或支撑柱300的个数（这里所示的是三个）可以是任意的。
对于戴有芯片帽的倒装芯片封装，芯片帽与芯片通过粘接材料粘接在一起以约束芯片在温度变化过程中的热变形。制造芯片帽的材料可以是金属，并具有较高的CTE（热膨胀系数），高模量和高导热性。特别地，制造芯片帽的材料可以是铜，铜合金，铝，铝合金，铁，钢或不锈钢。芯片帽的厚度大约在0.01毫米到1.0毫米。特别地，芯片帽的厚大约为0.015毫米至0.5毫米。芯片帽与芯片侧边之间被粘接材料填充的间隙的厚度可以大约为0.001毫米至2毫米。特别地，芯片帽与芯片侧边之间被粘接材料填充的间隙的厚度大约为0.05毫米至0.5毫米。芯片帽与芯片顶部之间被粘接材料填充的间隙大约为0.001毫米到0.25毫米。特别地，芯片帽与芯片顶部之间的间隙间隙大约为0.01毫米到0.1毫米。对于具有梳齿状结构侧壁的芯片帽，其与芯片侧边之间被粘接材料填充的间隙的厚度可以相对小些。
图8A，8B和8C所示的是戴有芯片帽的倒装芯片封装3000，3200和3400，其由芯片540，芯片帽500，1000或1200，基板520，焊球580，粘接材料560和底部填充材料565组成，其特征在于芯片540和芯片帽500通过粘接材料560粘接在一起，并且这个粘接材料560也可以与底部填充材料565相同。用相同的底部填充材料作为粘接芯片540和芯片帽500的粘接材料的一个优点是粘接材料560和底部填充胶材料565可以更好地在芯片帽侧壁的底部结合在一起，而其另一个优点是戴芯片帽的倒装芯片封装的组装过程可以更简单。
戴在倒装芯片封装的芯片上的芯片帽可以具有图5，图6和图7所示的本发明的芯片帽的四个特点中的一个或多个。图9A-9C描述的戴有芯片帽的倒装芯片封装4000，4200和4400中的芯片帽具有边缘凹口140，顶部边沿200和侧支撑壁300这些特点。戴在倒装芯片封装的芯片上的芯片帽也可以具有中凸点180。这里没有图示芯片帽具有中凸点180的倒装芯片封装。
从成本，可靠性和控制翘曲等各方面综合考虑，图5B所示的芯片帽和图8C所示的戴有这样的芯片帽的倒装芯片封装是优先的选择。基于倒装芯片封装的尺寸，其中的脚边沿160的长度约为0.1毫米至2毫米，并且0.2毫米至1.0毫米是优先的选择。
本发明的基本概念是用一个芯片帽去约束倒装芯片封装中芯片的热变形。本发明的基本概念可以容易地与一些传统的概念相结合以形成新的封装结构。例如，图10所示的戴有芯片帽500的倒装芯片封装5000，其特征在于，所述的芯片帽500塑封在塑封料620中。这种塑封体倒装芯片封装件5000可用于叠层封装组件（PoP），其中顶层焊球600是用于与顶层封装相连接。对于叠层封装组件来说，为了顶层和底层封装的可靠连接，对底层封装翘曲的有效控制是至关重要。戴有芯片帽500的倒装芯片封装5000可以显着地减少底层封装的翘曲。
本发明的基本概念也可以很容易地扩展到多个芯片或叠层芯片的半导体封装。图11所示的是一个戴有芯片帽的倒装芯片封装6000，其中的叠层多芯片组件包括一个中间芯片层740和两个芯片700，它们通过焊球720和底部填充材料560获得电的和机械的连接，而芯片帽500与叠层多芯片组件通过粘合材料560粘接在一起。
图12所示的是一个戴有芯片帽500的倒装芯片封装的组装工序7000，其特征在于，倒装芯片附着在基板上后，底部填充材料565首先被填充到芯片540与基板520之间的间隙，然后粘接剂或底部填充胶材料820被分配在芯片的顶部或芯片帽内，再通过压力800把芯片帽戴在芯片120上。当使用相同的底部填充材料作为芯片和芯片帽的粘接材料时，这个组装工序可以通过控制底部填充材料820的量来获得各种尺寸的底部填充圆角820。一个恰当的压力800可以使粘接剂或底部填充材料820从芯片顶部向下流动，从而填充芯片和芯片帽之间的间隙并与底部填充材料565相结合。为了散热的目的，用于粘接芯片和芯片帽的底部填充材料820可以具有高导热性。
图13A所示的是一个戴有芯片帽的倒装芯片封装的组装工序8000，其特征在于，倒装芯片附着在基板上后，首先把芯片帽1000盖在芯片上，然后再把芯片帽和芯片看作一个整体，在其与基板之间的间隙注入底部填充材料820。因为底部填充材料820是从芯片帽1000的外侧被填充进入芯片和基板之间的间隙，如图13B所示的这个组装工序8000生产的戴有芯片帽的倒装芯片封装将具有较大的底部填充圆角900。
对于制造戴盖子的倒装芯片封装的传统方法，底部填充材料是在安装盖子之前先被固化，在底部填充材料的固化过程中，倒装芯片封装将产生严重的翘曲。之后，通过在基板上附着盖子来纠正这个严重的翘曲，这样做的结果会在倒装芯片封装中导致非常高的应力水平。图12和图13所示的本发明的用于制造戴有芯片帽的倒装芯片的方法的一个主要特性是芯片帽盖在芯片上之后底部填充材料才被固化，其结果是，在底部填充材料的固化过程中芯片的热变形受到制约，从而减少或消除了在固化过程中产生的倒装芯片封装的翘曲。
与现有技术中的使用盖子的传统倒装芯片封装相比，本发明中的戴有芯片帽的倒装芯片封装具有以下的优点：1）在降低翘曲的同时也降低应力，2底部填充材料的开裂风险较低，3）芯片在测试或应用过程中的开裂风险较低，4）焊球开裂的风险较低，和5）更大的用于安装其它部件的基板上表面。
出于说明性的目的，本发明通过参照一些实施例和一些附图被加以描述。但是，很明显地，基于本发明的精神和基本概念，本发明可以有许多其他的修改和变化。

Claims (17)

1.用于倒装芯片封装的芯片帽，其包括顶片，在底部带脚边缘或不带脚边缘的四个侧壁，以及这四个特定元素中的一个或多个：1）在芯片帽的顶片的内表面上并沿着顶片边缘的边缘凹口，）在芯片帽的顶片的内表面上的中间部分的一些中凸点，3）从芯片帽的顶片向外延伸的顶部边缘，4）从芯片帽的顶片的顶部边缘向下延伸的侧支撑壁或侧支撑柱。
2.权利要求1所述的芯片帽，其特征在于，芯片帽的每个侧壁可以由一个整片组成或由多个形成梳状结构的小片组成。
3.权利要求1所述的芯片帽，其特征在于，芯片帽的顶片的顶部边缘可以是一个整片组成或多个分开的小片。
4.权利要求1所述的芯片帽，其特征在于，制造芯片帽的材料是厚度从0.01毫米到1毫米的金属片，并且具有高的热膨胀系数，高导热性和高杨氏模量，其可以是铜，镀镍的铜，铜合金，铝，阳极化铝，铝合金，铁，或不锈钢。
5.一个戴有芯片帽的倒装芯片封装，其包括芯片，基板和芯片帽，其特征在于，所述的芯片和基板通过导电焊球和底部填充材料在电性能上和结构上连接在一起，所述的芯片帽包括至少一个顶片和四个侧壁，其中每个侧壁的底部可以带有脚边缘，所述的芯片帽和芯片通过粘合材料在它们的顶部和四边相互粘接在一起，从而约束所述的倒装芯片封装中的芯片在温度变化过程中的热变形。
6.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，粘接材料（其用于粘接芯片帽和芯片）和底部填充材料（其用于填充芯片和基板之间的间隙）在芯片帽的侧壁的底部相连接。
7.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，所述的用于粘接芯片帽和芯片的粘接材料可以是相同的用于填充芯片和基板之间的间隙的填充模具和基板之间的间隙底部填充材料，这样，两种材料在芯片帽的侧壁的底部可以更好地结合在一起。
8.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，所述的芯片帽的每个侧壁可以是一整片材料或多片形成梳状结构的材料。
9.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，所述的芯片帽具有这四个特定元素中的一个或多个：1）在芯片帽的顶片的内表面上并沿着顶片边缘的边缘凹口，2）在芯片帽的顶片的内表面上的中间部分的一些中凸点，3）从芯片帽的顶片向外延伸的顶部边缘，4）从芯片帽的顶片的顶部边缘向下延伸的侧支撑壁或侧支撑柱。
10.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，制造芯片帽的材料是厚度从0.01毫米到1毫米的金属片，并且具有高的热膨胀系数，高导热性和高杨氏模量，其可以是铜，镀镍的铜，铜合金，铝，阳极化铝，铝合金，铁，或不锈钢。
11.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，所述的芯片可以是多个芯片的芯片组件。
12.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，这个戴有芯片帽的倒装芯片封装可进一步包括覆盖基板或芯片的塑封料。
13.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，所述的基板在其下表面具有焊球，引脚或焊盘，从而形成戴有芯片帽的倒装芯片球栅阵列封装（FCBGA），戴有芯片帽的倒装芯片引脚网格阵列封装（FCPGA）或戴有芯片帽的倒装芯片焊盘网格阵列封装（FCLGA）。
14.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，所述的芯片帽可以有一些小孔，这样，芯片和芯片帽可以更好地粘接在一起并避免在粘接层中产生孔洞，以免开裂。
15.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，所述的芯片帽的是一个网状的芯片帽，其可以由金属网制造，网状的芯片帽和芯片可以非常牢固地粘接在一起，以免开裂。
16.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，所述的芯片帽的顶片可以有一个非均匀的厚度，比如其中间部分比边缘部分厚是一个网状的芯片帽，这样，边缘处较厚的粘接层可以使芯片和芯片帽更好地粘接在一起，以免开裂。
17.权利要求5所述的戴有芯片帽的倒装芯片封装，其特征在于，用于粘接芯片帽和芯片的粘接材料和用于填充芯片和基板之间间隙的底部填充材料可以是任何的粘接材料，比如通过塑封铸模工艺形成的塑封材料。
CN201310456311.4A 2012-09-30 2013-09-29 芯片帽及戴有芯片帽的倒装芯片封装 Active CN103715150B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/631,991 US20140091461A1 (en) 2012-09-30 2012-09-30 Die cap for use with flip chip package
US13/631,991 2012-09-30

Publications (2)

Publication Number Publication Date
CN103715150A true CN103715150A (zh) 2014-04-09
CN103715150B CN103715150B (zh) 2017-07-25

Family

ID=50384405

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310456311.4A Active CN103715150B (zh) 2012-09-30 2013-09-29 芯片帽及戴有芯片帽的倒装芯片封装

Country Status (2)

Country Link
US (1) US20140091461A1 (zh)
CN (1) CN103715150B (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057750A (zh) * 2016-07-28 2016-10-26 合肥矽迈微电子科技有限公司 具有低翘曲度的封装结构
CN106910723A (zh) * 2015-07-29 2017-06-30 三星半导体(中国)研究开发有限公司 半导体封装件和制造该半导体封装件的方法
CN107403784A (zh) * 2016-05-19 2017-11-28 胡川 线路板制作方法及结构
CN108431946A (zh) * 2016-01-07 2018-08-21 赛灵思公司 具有加强件的堆叠的硅封装组件
CN108987358A (zh) * 2017-05-31 2018-12-11 台湾积体电路制造股份有限公司 封装件中具有不同厚度的热界面材料
CN111446217A (zh) * 2015-02-09 2020-07-24 株式会社吉帝伟士 半导体装置
WO2022061682A1 (zh) * 2020-09-25 2022-03-31 华为技术有限公司 一种封装结构及封装方法、电子装置及其制造方法
CN114823550A (zh) * 2022-06-27 2022-07-29 北京升宇科技有限公司 一种适于批量生产的芯片封装结构及封装方法
TWI832400B (zh) * 2021-08-31 2024-02-11 台灣積體電路製造股份有限公司 封裝結構以及用於形成其的方法

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2947692B1 (en) * 2013-12-20 2020-09-23 Analog Devices, Inc. Integrated device die and package with stress reduction features
US9497570B2 (en) 2014-02-06 2016-11-15 Nimbelink Corp. Embedded wireless modem
USD731491S1 (en) * 2014-02-07 2015-06-09 NimbeLink L.L.C. Embedded cellular modem
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
KR101676916B1 (ko) 2014-08-20 2016-11-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9899238B2 (en) 2014-12-18 2018-02-20 Intel Corporation Low cost package warpage solution
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
US10287161B2 (en) 2015-07-23 2019-05-14 Analog Devices, Inc. Stress isolation features for stacked dies
US9768145B2 (en) * 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
JP6676079B2 (ja) * 2016-02-16 2020-04-08 三菱電機株式会社 半導体装置およびその製造方法
US10236229B2 (en) 2016-06-24 2019-03-19 Xilinx, Inc. Stacked silicon package assembly having conformal lid
US10269669B2 (en) 2016-12-14 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of forming the same
US11302592B2 (en) * 2017-03-08 2022-04-12 Mediatek Inc. Semiconductor package having a stiffener ring
US9947634B1 (en) * 2017-06-13 2018-04-17 Northrop Grumman Systems Corporation Robust mezzanine BGA connector
WO2019005152A1 (en) * 2017-06-30 2019-01-03 Intel Corporation CHIP REAR FRONT STRUCTURES FOR AN ARROW CONTROL
US10636722B2 (en) * 2017-09-26 2020-04-28 Western Digital Technologies, Inc. System and method to enhance solder joint reliability
CN109727957B (zh) * 2017-10-30 2023-11-24 莱尔德电子材料(深圳)有限公司 热管理和电磁干扰减轻组件及其使用方法、包括该组件的装置
US11127716B2 (en) 2018-04-12 2021-09-21 Analog Devices International Unlimited Company Mounting structures for integrated device packages
US11062971B2 (en) * 2019-01-08 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method and equipment for forming the same
US11139253B2 (en) 2019-03-26 2021-10-05 Samsung Electronics Co., Ltd. Semiconductor package
US11710672B2 (en) * 2019-07-08 2023-07-25 Intel Corporation Microelectronic package with underfilled sealant
US20210013155A1 (en) * 2019-07-10 2021-01-14 Flex Ltd. Multi-metal package stiffener
US20210020537A1 (en) * 2019-07-19 2021-01-21 Intel Corporation Integrated heat spreader (ihs) with solder thermal interface material (stim) bleed-out restricting feature
US11430710B2 (en) * 2020-01-27 2022-08-30 International Business Machines Corporation Lid/heat spreader having targeted flexibility
EP3872851A1 (en) * 2020-02-27 2021-09-01 Infineon Technologies Austria AG Protector cap for package with thermal interface material
US11646302B2 (en) 2020-03-31 2023-05-09 Apple Inc. Multiple chip module trenched lid and low coefficient of thermal expansion stiffener ring
US11664340B2 (en) 2020-07-13 2023-05-30 Analog Devices, Inc. Negative fillet for mounting an integrated device die to a carrier
US20230064277A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of chip package with reinforcing structures
CN114582815B (zh) * 2022-05-05 2022-11-01 甬矽电子(宁波)股份有限公司 散热盖、封装结构和封装结构制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW552689B (en) * 2001-12-21 2003-09-11 Siliconware Precision Industries Co Ltd High electrical characteristic and high heat dissipating BGA package and its process
US6686649B1 (en) * 2001-05-14 2004-02-03 Amkor Technology, Inc. Multi-chip semiconductor package with integral shield and antenna
CN1549337A (zh) * 2003-05-09 2004-11-24 华泰电子股份有限公司 防止半导体封装件中散热片溢胶的散热片装置
CN1774804A (zh) * 2003-04-15 2006-05-17 波零公司 用于电子元件封装的emi屏蔽
CN101315919A (zh) * 2007-07-30 2008-12-03 日月光半导体制造股份有限公司 芯片封装结构及其工艺
CN102368494A (zh) * 2011-10-11 2012-03-07 常熟市广大电器有限公司 一种抗电磁干扰的芯片封装结构

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003068806A (ja) * 2001-08-29 2003-03-07 Hitachi Ltd 半導体装置及びその製造方法
US7187077B1 (en) * 2004-03-19 2007-03-06 Xilinx, Inc. Integrated circuit having a lid and method of employing a lid on an integrated circuit
JP2007042719A (ja) * 2005-08-01 2007-02-15 Nec Electronics Corp 半導体装置
US7851893B2 (en) * 2008-06-10 2010-12-14 Stats Chippac, Ltd. Semiconductor device and method of connecting a shielding layer to ground through conductive vias

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686649B1 (en) * 2001-05-14 2004-02-03 Amkor Technology, Inc. Multi-chip semiconductor package with integral shield and antenna
TW552689B (en) * 2001-12-21 2003-09-11 Siliconware Precision Industries Co Ltd High electrical characteristic and high heat dissipating BGA package and its process
CN1774804A (zh) * 2003-04-15 2006-05-17 波零公司 用于电子元件封装的emi屏蔽
CN1549337A (zh) * 2003-05-09 2004-11-24 华泰电子股份有限公司 防止半导体封装件中散热片溢胶的散热片装置
CN101315919A (zh) * 2007-07-30 2008-12-03 日月光半导体制造股份有限公司 芯片封装结构及其工艺
CN102368494A (zh) * 2011-10-11 2012-03-07 常熟市广大电器有限公司 一种抗电磁干扰的芯片封装结构

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111446217B (zh) * 2015-02-09 2024-02-09 安靠科技日本公司 半导体装置
CN111446217A (zh) * 2015-02-09 2020-07-24 株式会社吉帝伟士 半导体装置
CN106910723A (zh) * 2015-07-29 2017-06-30 三星半导体(中国)研究开发有限公司 半导体封装件和制造该半导体封装件的方法
CN106910723B (zh) * 2015-07-29 2019-05-24 三星半导体(中国)研究开发有限公司 半导体封装件和制造该半导体封装件的方法
CN108431946B (zh) * 2016-01-07 2021-12-07 赛灵思公司 具有加强件的堆叠的硅封装组件
CN108431946A (zh) * 2016-01-07 2018-08-21 赛灵思公司 具有加强件的堆叠的硅封装组件
CN107403784A (zh) * 2016-05-19 2017-11-28 胡川 线路板制作方法及结构
CN107403784B (zh) * 2016-05-19 2020-04-24 胡川 线路板制作方法及结构
CN106057750A (zh) * 2016-07-28 2016-10-26 合肥矽迈微电子科技有限公司 具有低翘曲度的封装结构
CN108987358A (zh) * 2017-05-31 2018-12-11 台湾积体电路制造股份有限公司 封装件中具有不同厚度的热界面材料
US10770405B2 (en) 2017-05-31 2020-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal interface material having different thicknesses in packages
US10707177B2 (en) 2017-05-31 2020-07-07 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal interface material having different thicknesses in packages
US11916023B2 (en) 2017-05-31 2024-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal interface material having different thicknesses in packages
WO2022061682A1 (zh) * 2020-09-25 2022-03-31 华为技术有限公司 一种封装结构及封装方法、电子装置及其制造方法
TWI832400B (zh) * 2021-08-31 2024-02-11 台灣積體電路製造股份有限公司 封裝結構以及用於形成其的方法
CN114823550A (zh) * 2022-06-27 2022-07-29 北京升宇科技有限公司 一种适于批量生产的芯片封装结构及封装方法
CN114823550B (zh) * 2022-06-27 2022-11-11 北京升宇科技有限公司 一种适于批量生产的芯片封装结构及封装方法

Also Published As

Publication number Publication date
CN103715150B (zh) 2017-07-25
US20140091461A1 (en) 2014-04-03

Similar Documents

Publication Publication Date Title
CN103715150B (zh) 芯片帽及戴有芯片帽的倒装芯片封装
US9087924B2 (en) Semiconductor device with resin mold
US7074645B2 (en) Fabrication method of semiconductor package with heat sink
US6038136A (en) Chip package with molded underfill
US7348211B2 (en) Method for fabricating semiconductor packages
TWI550741B (zh) 四方扁平無接腳封裝及其製造方法
JP6847266B2 (ja) 半導体パッケージおよびその製造方法
US20070273019A1 (en) Semiconductor package, chip carrier structure thereof, and method for fabricating the chip carrier
US20140167243A1 (en) Semiconductor packages using a chip constraint means
US9899208B2 (en) Molded leadframe substrate semiconductor package
JP2000323623A (ja) 半導体装置
JP2011086705A (ja) 半導体装置及びその製造方法
US7129119B2 (en) Method for fabricating semiconductor packages
US6699731B2 (en) Substrate of semiconductor package
CN103794587A (zh) 一种高散热芯片嵌入式重布线封装结构及其制作方法
JP2002110718A (ja) 半導体装置の製造方法
JP2010050323A (ja) 電子装置およびその製造方法
JP2010263108A (ja) 半導体装置及びその製造方法
JP3857574B2 (ja) 半導体装置及びその製造方法
US6710434B1 (en) Window-type semiconductor package and fabrication method thereof
KR101391108B1 (ko) 반도체 패키지 제조방법
JP3968321B2 (ja) 半導体装置およびその製造方法
JP5958136B2 (ja) 半導体装置及び半導体装置の製造方法
US20080251910A1 (en) Fabricating method of semiconductor package and heat-dissipating structure applicable thereto
JP2011151104A (ja) 半導体装置の製造方法及び半導体装置の中間構造体

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant