CN103594506A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN103594506A
CN103594506A CN201210293234.0A CN201210293234A CN103594506A CN 103594506 A CN103594506 A CN 103594506A CN 201210293234 A CN201210293234 A CN 201210293234A CN 103594506 A CN103594506 A CN 103594506A
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马小龙
殷华湘
许淼
朱慧珑
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Institute of Microelectronics of CAS
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Abstract

本发明公开了一种半导体器件，包括衬底、衬底上的缓冲层、缓冲层上的反型掺杂隔离层、反型掺杂隔离层上的阻挡层、阻挡层上的沟道层、沟道层上的栅极堆叠结构、栅极堆叠结构两侧的源漏区，其特征在于：缓冲层和/或阻挡层和/或反型掺杂隔离层为SiGe合金或者SiGeSn合金，沟道层为GeSn合金。依照本发明的半导体器件，采用SiGe/GeSn/SiGe的量子阱结构，限制载流子的输运，并且通过晶格失配引入应力，大大提高了载流子迁移率，从而提高了器件驱动能力以适应高速高频应用。

Description

半导体器件
技术领域
本发明涉及半导体集成电路制造领域，更具体地，涉及一种具有GeSn量子阱的场效应晶体管。
背景技术
随着集成电路工艺持续发展，特别是器件尺寸不断等比例缩减，器件的各个关键参数例如阈值电压等也随之减小，功耗减小、集成度提高这些优点促进了器件整体性能提高。然而与此同时，器件的驱动能力却受制于传统的硅材料工艺的限制，载流子迁移率较低，面临了器件驱动能力相比而言不足的问题，难以用于高速高频应用领域。因此，高迁移率器件特别是高迁移率晶体管(HEMT)在未来具有重要应用背景。
一种现有的高迁移率场效应晶体管(FET)是AlGaAs/GaAs基的，例如是在GaAs衬底上依次包括本征的GaAs层(用作缓冲层和/或下盖层)、本征的AlxGal-xAs层(用作势阱层、活性层、控制层)、n掺杂的AlxGal-xAs层(用作上盖层)，在上盖层之上再形成栅极堆叠以及栅极堆叠两侧的源漏(接触)区。器件工作时，作为载流子的电子基本上被限制在势阱层中，形成二维电子气，在该层中载流子迁移率得到极大提升，因此提高了器件的驱动能力。
然而，上述各项材料和工艺与现有的Si基CMOS工艺兼容度不高，在制造高迁移率器件时需要大量额外的工艺和设备，因此成本较高。作为替代，另一种现有的高迁移率场效应晶体管则是在Si衬底上依次沉积不同配比的SiGe合金作为量子阱层并且采用Si或SiGe作为缓冲层、阻挡层、盖层。这种SiGe/Si基的高迁移率FET虽然降低了成本，但是由于材料本身限制，导致迁移率提高幅度有限。
因此，需要一种工艺简单、载流子迁移率更高的FET。
发明内容
有鉴于此，本发明的目的在于提供一种具有GeSn量子阱的场效应晶体管，以简化工艺、降低成本的同时还能大幅提高载流子迁移率。
实现本发明的上述目的，是通过提供一种半导体器件，包括衬底、衬底上的缓冲层、缓冲层上的反型掺杂隔离层、反型掺杂隔离层上的阻挡层、阻挡层上的沟道层、沟道层上的栅极堆叠结构、栅极堆叠结构两侧的源漏区，其特征在于：缓冲层和/或阻挡层和/或反型掺杂隔离层为SiGe合金或者SiGeSn合金，沟道层为GeSn合金。
其中，缓冲层和/或阻挡层和/或反型掺杂隔离层中Ge含量大于50％。
其中，缓冲层和/或阻挡层和/或反型掺杂隔离层中Sn含量小于25％。
其中，缓冲层厚度为100nm～2μm。
其中，沟道层中Sn含量大于1％并且小于25％。
其中，沟道层厚度为5nm～200nm。
其中，沟道层与栅极堆叠结构之间还包括SiGe合金的盖层。
其中，源漏区为Si GeSn合金。
其中，源漏区具有第一导电类型，反型掺杂隔离层、阻挡层、沟道区具有与第一导电类型相反的第二导电类型。
其中，阻挡层材料的禁带宽度大于沟道层材料的带隙宽度。
依照本发明的半导体器件，采用SiGe/GeSn/SiGe的量子阱结构，限制载流子的输运，并且通过晶格失配引入应力，大大提高了载流子迁移率，从而提高了器件驱动能力以适应高速高频应用。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1为根据本发明实施例的半导体器件的剖视图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”、“厚”、“薄”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。
参照图1，为根据本发明一个实施例的半导体器件的剖视图。
提供衬底1，其材质可以是(体)Si(例如单晶Si晶片)、SOI、GeOI(绝缘体上Ge)。优选地，衬底1选用体Si或SOI，以便与CMOS工艺兼容。
通过PECVD、MOCVD、MBE、ALD等方法，在衬底1上沉积形成缓冲层2，用于降低衬底1与上层的GeSn沟道层之间的晶格失配。缓冲层2的材质的晶格常数要介于衬底1的Si/Ge与上层的GeSn之间，优选为SiGe合金，具体地可以是Sil-xGex，其中Ge含量(原子数目百分比)x大于50％也即x>0.5。缓冲层2的厚度例如是100nm～2μm。此外，缓冲层2也可以是SiGeSn三元合金例如Sil-u-vGeuSnv，其中Ge含量u大于50％并且优选介于60％～70％之间也即0.6<u<0.7，Sn含量v小于25％并且优选地介于1％～10％之间也即0.01<v<0.1。
通过PECVD、MOCVD、MBE、ALD等方法，在缓冲层2上沉积形成反型掺杂隔离层3，其导电类型缓冲层2和/或稍后的阻挡层4相同，但是与稍后的源漏区8(具有第一导电类型，例如n或者p)不同，例如具有第二导电类型(p或n)，用于通过掺杂而调整控制势垒，调节阈值电压。反型掺杂隔离层3的材质可以是S iGe合金，具体地可以是Si1-yGey，其中Ge含量(原子数目百分比)y介于55％～75％之间，也即0.55<y<0.75。反型掺杂隔离层3的厚度例如是50nm～500nm。反型掺杂隔离层3形成过程中可以原位掺杂，也可以形成反型掺杂隔离层3之后注入掺杂，掺杂剂例如包括B、P、N、Al、Ga等，用于调节导电类型。
同样通过PECVD、MOCVD、MBE、ALD等方法，在反型掺杂隔离层3上沉积形成阻挡层4，用于将作为载流子的二维电子气限制在其上的沟道层中。阻挡层4的材质可以是SiGe合金，具体地可以是Sil-yGey，其中Ge含量(原子数目百分比)y大于50％并且优选介于55％～75％之间，也即0.55<y<0.75。阻挡层4的厚度例如是50nm～500nm。此外，阻挡层4也可以是上述SiGeSn三元合金。阻挡层4具有第二导电类型，并且掺杂浓度较轻，也即为p-或者n-型。特别地，阻挡层4材料的禁带宽度E2大于沟道层5材料的带隙宽度E1。
在阻挡层4上沉积形成量子阱层5，用作器件的沟道层。量子阱层5的材质是GeSn合金，具体地可以是Ge1-zSnz，其中Sn含量(原子数目百分比)z介于1％～25％之间，也即0.01<z<0.25。量子阱层5的厚度例如是5nm～200nm。形成GeSn基量子阱层的方法可以是传统的MBE、MOCVD、ALD等方法，也可以是依次沉积非晶Ge和金属Sn层并且激光快速退火使得两者相互反应而形成。
可选地，在量子阱层5上还通过PECVD、MOCVD、MBE、ALD等方法沉积形成盖层6，用于将作为载流子的二维电子气限制在其下的沟道层5中。盖层6的材质可以是SiGe合金，具体地可以是Si1-wGew，其中Ge含量(原子数目百分比)w大于50％并且优选介于60％～85％之间，也即0.60<w<0.85。盖层6的厚度例如是100nm～500nm。
随后，在量子阱的沟道层5(以及盖层6)上形成栅极堆叠结构7。例如采用LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等常规沉积方法，依次沉积并且随后刻蚀形成栅极绝缘层7A和栅极导电层7B。当栅极堆叠结构采用前栅工艺时：栅极绝缘层7A是高k材料，包括但不限于氮化物(例如SiN、AlN、TiN)、金属氧化物(主要为副族和镧系金属元素氧化物，例如Al2O3、Ta2O5、TiO2、ZnO、ZrO2、HfO2、CeO2、Y2O3、La2O3)、钙钛矿相氧化物(例如PbZrxTi1-xO3(PZT)、BaxSr1-xTiO3(BST))；栅极导电层7B是金属、金属氮化物及其组合，其中金属包括Al、Ti、Cu、Mo、W、Ta以用作栅极填充层，金属氮化物包括TiN、TaN以用作功函数调节层。当栅极堆叠结构采用后栅工艺时，用作假栅极堆叠结构，因此假栅极绝缘层是氧化硅，假栅极导电层是多晶硅、非晶硅，随后工艺中刻蚀去除假栅极堆叠结构形成栅极沟槽，在栅极沟槽中依次填充如前述高k材料的栅极绝缘层7A以及金属材料的栅极导电层7B，因此栅极绝缘层7A包围了栅极导电层7B的底部以及侧面。在栅极绝缘层7A/栅极导电层7B两侧通过沉积后刻蚀形成了氮化硅、氮氧化硅、类金刚石无定形碳(DLC)的材质的栅极侧墙7C，这些构成了栅极堆叠结构6。
在栅极堆叠结构7两侧形成源漏区8。
当不包含盖层6时(未示出)，直接在量子阱的沟道层5上通过MBE、MOCVD、ALD等方法沉积形成了源漏区8，其材质为SiGeSn合金。具体地，源漏区8包括Sil-u-vGeuSnv，其中Ge含量u大于50％并且优选介于60％～70％之间也即0.6<u<0.7，Sn含量v小于25％并且优选介于1％～10％之间也即0.01<v<0.1。源漏区8的厚度可以是500nm～2μm。此外，也可以在GeSn的沟道层5栅极堆叠结构7两侧的位置处注入Si并且退火激活，使得形成S iGeSn三元合金的源漏区8，此时源漏区8将与图1所示不同而深入沟道层5中、但是不接触更下方的阻挡层4，也即深入深度不大于沟道层5厚度(未示出)。优选地，继续采用外延技术，形成抬升的源漏区8，使得源漏区8的上表面高于栅极绝缘层6A的上表面。
如图1所示，当沟道层5上包含了盖层6时，可以先刻蚀形成沟槽，刻蚀可以停止在沟道层5与盖层6的界面上，也可以停止在沟道层5中并且未到达阻挡层4。此后通过MBE、MOCVD、ALD等方法沉积形成了上述SiGeSn三元合金的源漏区8。
优选地，形成源漏区8时或者形成源漏区8之后，可以原位掺杂或者注入掺杂使得源漏区8具有第一导电类型。掺杂剂可以包括B、P、Al、Ga等，用于调节源漏区导电类型和浓度。
最后，可以在源漏区8上形成源漏接触层9，例如是金属硅化物，以降低源漏电阻。在整个器件上形成层间介质层(ILD)10，刻蚀ILD10形成源漏接触孔，在接触孔中填充W、Al、Mo等金属形成源漏接触塞11。
因此，根据本发明第一实施例，半导体器件包括衬底1、衬底1上的缓冲层2、缓冲层2上的SiGe反型掺杂隔离层3、反型掺杂隔离层3上SiGe合金的阻挡层4、阻挡层4上GeSn合金的沟道层5、沟道层5上的栅极堆叠结构7、栅极堆叠结构7两侧的源漏区8。其中，沟道层5与栅极堆叠结构7之间还可以包括S iGe合金的盖层6。其中，缓冲层2、反型掺杂隔离层3、阻挡层4、盖层6除了是SiGe合金之外，还可以是与源漏区8相同或者类似的SiGeSn三元合金，例如前述的Sil-u-vGeuSnv。其余各个部件的材料配比、厚度等参数均描述在上述制造方法中，因此不再赘述。
依照本发明的半导体器件，采用SiGe/GeSn/SiGe的量子阱结构，限制载流子的输运，并且通过晶格失配引入应力，大大提高了载流子迁移率，从而提高了器件驱动能力以适应高速高频应用。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (10)

1.一种半导体器件，包括衬底、衬底上的缓冲层、缓冲层上的反型掺杂隔离层、反型掺杂隔离层上的阻挡层、阻挡层上的沟道层、沟道层上的栅极堆叠结构、栅极堆叠结构两侧的源漏区，其特征在于：缓冲层和/或阻挡层和/或反型掺杂隔离层为SiGe合金或者SiGeSn合金，沟道层为GeSn合金。
2.如权利要求1的半导体器件，其中，缓冲层和/或阻挡层和/或反型掺杂隔离层中Ge含量大于50％。
3.如权利要求1的半导体器件，其中，缓冲层和/或阻挡层和/或反型掺杂隔离层中Sn含量小于25％。
4.如权利要求1的半导体器件，其中，缓冲层厚度为100nm～2μm。
5.如权利要求1的半导体器件，其中，沟道层中Sn含量大于1％并且小于25％。
6.如权利要求1的半导体器件，其中，沟道层厚度为5nm～200nm。
7.如权利要求1的半导体器件，其中，沟道层与栅极堆叠结构之间还包括SiGe合金的盖层。
8.如权利要求1的半导体器件，其中，源漏区为Si GeSn合金。
9.如权利要求1的半导体器件，其中，源漏区具有第一导电类型，反型掺杂隔离层、阻挡层、沟道区具有与第一导电类型相反的第二导电类型。
10.如权利要求1的半导体器件，其中，阻挡层材料的禁带宽度大于沟道层材料的带隙宽度。
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