WO2020062706A1 - 一种硅基锗锡高电子迁移率晶体管 - Google Patents

一种硅基锗锡高电子迁移率晶体管 Download PDF

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WO2020062706A1
WO2020062706A1 PCT/CN2019/070518 CN2019070518W WO2020062706A1 WO 2020062706 A1 WO2020062706 A1 WO 2020062706A1 CN 2019070518 W CN2019070518 W CN 2019070518W WO 2020062706 A1 WO2020062706 A1 WO 2020062706A1
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layer
silicon
gesn
electron mobility
high electron
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PCT/CN2019/070518
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French (fr)
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汪巍
方青
涂芝娟
曾友宏
蔡艳
王庆
王书晓
余明斌
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中国科学院上海微系统与信息技术研究所
上海新微科技服务有限公司
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Publication of WO2020062706A1 publication Critical patent/WO2020062706A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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  • the present application relates to the field of semiconductor technology, and in particular, to a silicon-based germanium tin high electron mobility transistor.
  • High Electron Mobility Transistor (HEMT, High Electron Mobility Transistor) has excellent performance such as high speed, high frequency, and low noise, and is a mainstream microwave device for 5G communication and high frequency satellite communication.
  • III-V high mobility semiconductor materials represented by gallium arsenide and indium phosphide have shown great advantages and can meet the high-speed, high-speed of information processing Frequency requirements.
  • III-V materials are very expensive to manufacture, cause environmental problems, and are difficult to integrate with silicon (Si) -based integrated circuit manufacturing technologies.
  • the embodiments of the present application provide a silicon-based germanium tin (GeSn) high electron mobility transistor and a manufacturing method thereof.
  • a high electron mobility transistor made of a germanium tin (GeSn) material is formed on a silicon-based substrate.
  • the high-speed performance of the transistor, and GeSn is easy to integrate with Si-based integrated circuit manufacturing technology.
  • a silicon-based germanium tin (GeSn) high electron mobility transistor including:
  • a channel layer on the buffer layer the channel layer being a germanium tin (GeSn) material
  • a spacer layer, a barrier layer, and a cap layer on the channel layer, the spacer layer, the barrier layer, and the cap layer are a III-V semiconductor material, wherein an interface between the spacer layer and the channel layer is formed
  • the two-dimensional electron gas has a thickness of more than 500 nm.
  • a material of the silicon-based substrate is silicon or silicon on an insulator, and a material of the buffer layer is germanium or silicon germanium (SiGe).
  • the material of the channel layer is Ge (1-x) Sn x , where 0.06 ⁇ x ⁇ 0.3.
  • the material of the spacer layer, the barrier layer and the capping layer is indium aluminum phosphorus (InAlP), indium aluminum arsenic (InAlAs), indium gallium phosphorus (InGaP) or indium gallium arsenide (InGaAs).
  • the spacer layer is undoped
  • the barrier layer and the capping layer are both doped
  • a doping concentration of the capping layer is higher than the barrier layer The doping concentration of the layer.
  • the barrier layer is connected to a gate electrode, and the capping layer is connected to a source electrode and a drain electrode.
  • a beneficial effect of the present application is that a high electron mobility transistor made of a germanium tin (GeSn) material is formed on a silicon-based substrate, thereby improving the high-speed performance of the transistor, and GeSn is easily integrated with Si-based integrated circuit manufacturing technology .
  • GeSn germanium tin
  • FIG. 1 is a schematic diagram of a silicon-based germanium tin high electron mobility transistor according to Embodiment 1 of the present application;
  • FIG. 2 is a schematic diagram of a method for manufacturing a silicon-based germanium-tin high electron mobility transistor according to Embodiment 2 of the present application;
  • lateral a direction parallel to the main surface of the silicon-based substrate
  • longitudinal a direction perpendicular to the main surface of the silicon-based substrate
  • the embodiments of the present application provide a silicon-based germanium tin (GeSn) high electron mobility transistor.
  • FIG. 1 is a schematic diagram of a silicon-based germanium tin (GeSn) high electron mobility transistor according to this embodiment.
  • the silicon-based germanium tin high electron mobility transistor 1 includes: a silicon-based substrate 11; Buffer layer 12 on base substrate 11; channel layer 13 on buffer layer 12, channel layer 13 made of germanium tin (GeSn) material; spacer layer 14, barrier layer 15 and channel layer 13 on channel layer 13
  • the cap layer 16, wherein the spacer layer 14, the barrier layer 15 and the cap layer 16 are III-V semiconductor materials, and the buffer layer 12 has a thickness greater than 500 nm.
  • the spacer layer 14 and the channel layer 13 form a III-V / GeSn heterojunction, and a conduction band band step is formed in the III-V / GeSn heterojunction, thereby generating a two-dimensional electron gas.
  • the Schottky barrier under the gate electrode 17 controls the two-dimensional electron gas concentration in the III-V / GeSn heterojunction, thereby realizing the control of the current. Since the GeSn material has high electron mobility, and the two-dimensional electron gas is spatially separated from the impurity center in the III-V layer and is not affected by the scattering of ionized impurities, high mobility can be achieved.
  • a high electron mobility transistor made of a germanium tin (GeSn) material is formed on a silicon-based substrate, whereby the high-speed performance of the transistor can be improved, and GeSn is easily integrated with Si-based integrated circuit manufacturing technology.
  • GeSn germanium tin
  • the material of the silicon-based substrate 11 is silicon (Si) or silicon on insulator (SOI).
  • the surface of the silicon-based substrate 11 is, for example, a (111) crystal plane.
  • the material of the buffer layer 12 is germanium (Ge) or silicon germanium (SiGe).
  • the buffer layer 12 can buffer the mismatch between the lattice of the surface of the silicon-based substrate 11 and the lattice of the channel layer 13, thereby improving the quality of the channel layer 13.
  • germanium tin (GeSn) material of the channel layer 13 may be represented as Ge (1-x) Sn x , where 0.06 ⁇ x ⁇ 0.3.
  • germanium tin The band structure of germanium tin (GeSn) is adjusted with the Sn composition.
  • Sn composition is greater than 6%, GeSn will achieve the transition from an indirect bandgap material to a direct bandgap material, and when GeSn becomes a direct bandgap For materials, its electron mobility is much larger than that of Si and Ge materials.
  • the composition of Sn in the germanium tin (GeSn) material of the channel layer 13 is controlled to be 6% to 30%, and the germanium tin (GeSn) material of the channel layer 13 can be made into a direct band gap. Materials, thereby increasing the electron mobility in the channel layer.
  • the III-V materials of the spacer layer 14, the barrier layer 15, and the capping layer 16 may be lattice-matched or approximately matched materials of the germanium tin (GeSn) material of the channel layer 13. Adjusting the composition of each element in the III-V material can make the lattice constant of the III-V material match or approximately match the lattice of the GeSn material.
  • the III-V material may be, for example, indium aluminum phosphorus (InAlP), indium aluminum arsenic (InAlAs), indium gallium phosphorus (InGaP), or indium gallium arsenide (InGaAs). In addition, other III-V materials may be used.
  • the spacer layer 14 is undoped, so that the movement of the two-dimensional electron gas is not affected by the scattering of impurities.
  • the barrier layer 15 is connected to the gate electrode 17, and the capping layer 16 is connected to the source electrode 18 and the drain electrode 19.
  • the barrier layer 15 and the capping layer 16 are both doped, thereby facilitating contact with the gate electrode, the source electrode, and the drain electrode.
  • the doping concentration of the capping layer 16 may be higher than that of the barrier layer 15.
  • a high electron mobility transistor made of a germanium tin (GeSn) material is formed on a silicon-based substrate, whereby the high-speed performance of the transistor can be improved, and GeSn, which is a Group IV material, is easily integrated with a Si-based integrated circuit. Manufacturing technology integration.
  • Embodiment 2 provides a method for manufacturing a silicon-based germanium-tin high electron mobility transistor, which is used for manufacturing the silicon-based germanium-tin high electron mobility transistor described in Embodiment 1.
  • FIG. 2 is a schematic diagram of a method for manufacturing a silicon-based germanium tin high electron mobility transistor according to this embodiment. As shown in FIG. 2, in this embodiment, the method for manufacturing may include:
  • Step 201 forming a buffer layer on a silicon-based substrate
  • Step 202 A channel layer is formed on the buffer layer, and the channel layer is a germanium tin (GeSn) material;
  • Step 203 A spacer layer, a barrier layer, and a cap layer are formed on the channel layer, and the spacer layer, the barrier layer and the cap layer are a III-V semiconductor material, wherein the spacer layer and the channel layer Interface is formed with two-dimensional electron gas,
  • Step 204 Etch the capping layer to expose the barrier layer
  • Step 205 forming a gate electrode on the exposed barrier layer
  • Step 206 Form a source electrode and a drain electrode on the capping layer on both sides of the gate electrode, respectively.
  • the material of the silicon-based substrate is silicon or silicon on an insulator
  • the material of the buffer layer is germanium or silicon germanium (SiGe).
  • the material of the channel layer is Ge (1-x) Snx, where 0.06 ⁇ x ⁇ 0.3.
  • the material of the spacer layer, the barrier layer and the capping layer is indium aluminum phosphorus (InAlP), indium aluminum arsenic (InAlAs), indium gallium phosphorus (InGaP), or indium gallium arsenide (InGaAs).
  • the spacer layer is undoped, the barrier layer and the capping layer are both doped, and the doping concentration of the capping layer is higher than the doping concentration of the barrier layer.
  • FIG. 3 is a cross-sectional view of the device corresponding to each step in this example.
  • a method for manufacturing a silicon-based germanium tin (GeSn) high electron mobility transistor includes the following steps:
  • Step 1 As shown in FIG. 3 (a), a Ge buffer layer 12 and a GeSn channel layer 13 are sequentially epitaxially grown on the surface of the cleaned Si substrate 11 by a two-step chemical vapor deposition method at a low temperature and a high temperature.
  • the thickness of the buffer layer 12 is> 500 nm
  • the Sn composition in the GeSn channel layer 13 is 10%
  • the thickness of the GeSn channel layer 13 is> 300 nm.
  • the GeSn channel layer 13 is not doped.
  • Step 3 As shown in FIG. 3 (c), the source and drain regions 16a are defined in the capping layer 16 using photolithography and reactive ion etching techniques; in the barrier layer 15 exposed between the source and drain regions 16a, photolithography is performed And etching to define the gate region; the gate electrode material is deposited, and the gate electrode 17 is prepared by photolithographic etching.
  • Step 4 As shown in FIG. 3 (d), the source and drain electrode materials are deposited, and the source and drain electrodes 18 and 19 are prepared by photolithographic etching to complete the device preparation.
  • a high electron mobility transistor made of a germanium tin (GeSn) material is formed on a silicon-based substrate, whereby the high-speed performance of the transistor can be improved, and GeSn, which is a Group IV material, is easily integrated with a Si-based integrated circuit. Manufacturing technology integration.

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Abstract

一种硅基锗锡高电子迁移率晶体管（1），该硅基锗锡高电子迁移率晶体管（1）包括：硅基衬底（11）；位于所述硅基衬底（11）上的缓冲层（12）；位于所述缓冲层（12）上的沟道层（13），所述沟道层（13）为锗锡(GeSn)材料；以及位于所述沟道层（13）上的间隔层（14），势垒层（15）和盖层（16），所述间隔层（14），势垒层（15）和盖层（16）为III-V族半导体材料，其中，所述间隔层（14）与沟道层（13）的界面形成二维电子气，所述缓冲层（12）厚度大于500nm。能够提高晶体管的高速性能，并且，GeSn容易与Si基集成电路制造技术集成。

Description

一种硅基锗锡高电子迁移率晶体管 技术领域
本申请涉及半导体技术领域，尤其涉及一种硅基锗锡高电子迁移率晶体管。
背景技术
高电子迁移率晶体管(HEMT，High Electron Mobility Transistor)具有的高速、高频、低噪声等优异性能，是实现5G通信、高频卫星通信的主流微波器件。
随着半导体应用不断向微波(高频)段拓展，以砷化镓、磷化铟为代表的III-V族高迁移率半导体材料显示出巨大的优越性，能满足信息处理的高速化、高频化需求。
应该注意，上面对技术背景的介绍只是为了方便对本申请的技术方案进行清楚、完整的说明，并方便本领域技术人员的理解而阐述的。不能仅仅因为这些方案在本申请的背景技术部分进行了阐述而认为上述技术方案为本领域技术人员所公知。
发明内容
在现有技术中，III-V族材料制造成本都非常高，并且会引起环境问题，而且难以与硅(Si)基集成电路制造技术集成。
本申请实施例提供一种硅基锗锡(GeSn)高电子迁移率晶体管及其制造方法，在硅基衬底上形成由锗锡(GeSn)材料制备高电子迁移率晶体管，由此，能够提高晶体管的高速性能，并且，GeSn容易与Si基集成电路制造技术集成。
根据本申请实施例的一个方面，提供一种硅基锗锡(GeSn)高电子迁移率晶体管，包括：
硅基衬底；
位于所述硅基衬底上的缓冲层；
位于所述缓冲层上的沟道层，所述沟道层为锗锡(GeSn)材料；以及
位于所述沟道层上的间隔层，势垒层和盖层，所述间隔层，势垒层和盖层为III-V族半导体材料，其中，所述间隔层与沟道层的界面形成二维电子气，所述缓冲层厚度 大于500nm。
根据本申请实施例的另一个方面，其中，所述硅基衬底的材料为硅或绝缘体上的硅，所述缓冲层材料为锗或者锗硅(SiGe)。
根据本申请实施例的另一个方面，其中，所述沟道层的材料为Ge (1-x)Sn x，其中，0.06<x<0.3。
根据本申请实施例的另一个方面，其中，所述间隔层，势垒层和盖层的材料为铟铝磷(InAlP)，铟铝砷(InAlAs)，铟镓磷(InGaP)或者铟镓砷(InGaAs)。
根据本申请实施例的另一个方面，其中，所述间隔层未掺杂，所述势垒层和所述盖层均掺杂，并且，所述盖层的掺杂浓度高于所述势垒层的掺杂浓度。
根据本申请实施例的另一个方面，其中，所述势垒层与栅电极连接，所述盖层与源电极和漏电极连接。
本申请的有益效果在于：在硅基衬底上形成由锗锡(GeSn)材料制备高电子迁移率晶体管，由此，能够提高晶体管的高速性能，并且，GeSn容易与Si基集成电路制造技术集成。
参照后文的说明和附图，详细公开了本申请的特定实施方式，指明了本申请的原理可以被采用的方式。应该理解，本申请的实施方式在范围上并不因而受到限制。在所附权利要求的精神和条款的范围内，本申请的实施方式包括许多改变、修改和等同。
针对一种实施方式描述和/或示出的特征可以以相同或类似的方式在一个或更多个其它实施方式中使用，与其它实施方式中的特征相组合，或替代其它实施方式中的特征。
应该强调，术语“包括/包含”在本文使用时指特征、整件、步骤或组件的存在，但并不排除一个或更多个其它特征、整件、步骤或组件的存在或附加。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请实施例1的硅基锗锡高电子迁移率晶体管的一个示意图；
图2是本申请实施例2的硅基锗锡高电子迁移率晶体管的制造方法的一个示意图；
图3(a)-图3(b)是本申请实施例2中各步骤对应的器件截面图。
具体实施方式
参照附图，通过下面的说明书，本申请的前述以及其它特征将变得明显。在说明书和附图中，具体公开了本申请的特定实施方式，其表明了其中可以采用本申请的原则的部分实施方式，应了解的是，本申请不限于所描述的实施方式，相反，本申请包括落入所附权利要求的范围内的全部修改、变型以及等同物。
在本申请各实施例的说明中，为描述方便，将平行于硅基衬底的主表面的方向称为“横向”，将垂直于硅基衬底的主表面的方向称为“纵向”。
实施例1
本申请实施例提供一种硅基锗锡(GeSn)高电子迁移率晶体管。
图1是本实施例的硅基锗锡(GeSn)高电子迁移率晶体管的一个示意图，如图1所示，该硅基锗锡高电子迁移率晶体管1包括：硅基衬底11；位于硅基衬底11上的缓冲层12；位于缓冲层12上的沟道层13，沟道层13为锗锡(GeSn)材料制备；位于沟道层13上的间隔层14，势垒层15和盖层16，其中，间隔层14，势垒层15和盖层16为III-V族半导体材料，缓冲层12厚度大于500nm。
在本实施例中，间隔层14与沟道层13形成III-V/GeSn异质结，并在该III-V/GeSn异质结中形成导带带阶，从而产生二维电子气，通过栅电极17下的肖特基势垒来控制III-V/GeSn异质结中的二维电子气浓度，从而实现电流的控制。由于GeSn材料具有高的电子迁移率，且二维电子气与处在III-V层中的杂质中心在空间上是分离的，且不受电离杂质散射的影响，所以可以实现高的迁移率。
根据本实施例，在硅基衬底上形成由锗锡(GeSn)材料制备高电子迁移率晶体管，由此，能够提高晶体管的高速性能，并且，GeSn容易与Si基集成电路制造技术集成。而在现有技术中，还没有关于GeSn高电子迁移率晶体管的技术方案，更没有硅基GeSn高电子迁移率晶体管的相关报道。
在本实施例中，硅基衬底11的材料为硅(Si)或绝缘体上的硅(SOI)。该硅基 衬底11的表面的例如为(111)晶面。
在本实施例中，缓冲层12的材料为锗(Ge)或者锗硅(SiGe)。该缓冲层12能够缓冲硅基衬底11的表面的晶格与沟道层13的晶格之间的不匹配，从而提高沟道层13的质量。
在本实施例中，沟道层13的锗锡(GeSn)材料可以表示为Ge (1-x)Sn x，其中，0.06<x<0.3。
锗锡(GeSn)的能带结构随Sn组分而被调整，当Sn组分大于6％时，GeSn将实现间接带隙材料到直接带隙材料的转变，并且，当GeSn变为直接带隙材料时，其电子迁移率远大于Si和Ge材料。
因此，在本实施例中，将沟道层13的锗锡(GeSn)材料中Sn的组分控制在6％到30％，能够使沟道层13的锗锡(GeSn)材料成为直接带隙材料，从而提高沟道层中的电子迁移率。
在本实施例中，间隔层14，势垒层15和盖层16的III-V材料可以是与沟道层13的锗锡(GeSn)材料的晶格匹配或近似匹配的材料，其中，通过调整III-V材料中各元素的组分，可以使得III-V族材料晶格常数与GeSn材料晶格匹配的或近似匹配。该III-V材料例如可以是铟铝磷(InAlP)，铟铝砷(InAlAs)，铟镓磷(InGaP)或者铟镓砷(InGaAs)。此外，也可以是其他的III-V组材料。
在本实施例中，间隔层14未掺杂，从而避免二维电子气的运动受到杂质的散射的影响。
在本实施例中，势垒层15与栅电极17连接，盖层16与源电极18和漏电极19连接。
在本实施例中，势垒层15和盖层16均掺杂，从而便于和栅电极、源电极、漏电极形成接触。此外，在本实施例中，盖层16的掺杂浓度可以高于势垒层15的掺杂浓度。
根据本实施例，在硅基衬底上形成由锗锡(GeSn)材料制备高电子迁移率晶体管，由此，能够提高晶体管的高速性能，并且，作为四族材料的GeSn容易与Si基集成电路制造技术集成。
实施例2
实施例2提供一种硅基锗锡高电子迁移率晶体管的制造方法，用于制造实施例1所述的硅基锗锡高电子迁移率晶体管。
图2是本实施例的硅基锗锡高电子迁移率晶体管的制造方法的一个示意图，如图2所示，在本实施例中，该制造方法可以包括：
步骤201、在硅基衬底上形成缓冲层；
步骤202、在所述缓冲层上形成沟道层，所述沟道层为锗锡(GeSn)材料；以及
步骤203、在所述沟道层上形成间隔层，势垒层和盖层，所述间隔层，势垒层和盖层为III-V族半导体材料，其中，所述间隔层与沟道层的界面形成有二维电子气，
步骤204、刻蚀所述盖层，以露出所述势垒层；
步骤205、在露出的所述势垒层上形成栅电极；
步骤206、在所述栅电极两侧的所述盖层上分别形成源电极和漏电极。
在本实施例中，该硅基衬底的材料为硅或绝缘体上的硅，该缓冲层材料为锗或者锗硅(SiGe)。
在本实施例中，沟道层的材料为Ge(1-x)Snx，其中，0.06<x<0.3。
在本实施例中，间隔层，势垒层和盖层的材料为铟铝磷(InAlP)，铟铝砷(InAlAs)，铟镓磷(InGaP)或者铟镓砷(InGaAs)。其中，该间隔层未掺杂，该势垒层和该盖层均掺杂，并且，该盖层的掺杂浓度高于该势垒层的掺杂浓度。
下面，结合一个具体的实例来说明本申请的硅基锗锡高电子迁移率晶体管的制造方法。
图3是该实例中各步骤对应的器件截面图，如图3所示，在该实例中，硅基锗锡(GeSn)高电子迁移率晶体管的制造方法包括如下步骤：
步骤1：如图3(a)所示，在清洗后的Si衬底11表面，采用低温和高温两步化学气相沉积方法，依次外延生长Ge缓冲层12和GeSn沟道层13，其中，Ge缓冲层12厚度>500nm，GeSn沟道层13中Sn组分为10％，GeSn沟道层13厚度>300nm，其中，GeSn沟道层13不掺杂。
步骤2：如图3(b)所示，外延生长本征In 1-yAl yAs间隔层14，y＝0.72，厚度～2nm；外延生长n型In 1-yAl yAs势垒层15，y＝0.72，厚度约30nm，掺杂浓度1*10 18cm -3；外延生长重掺杂n型In 1-yAl yAs盖层16，y＝0.72，厚度约50nm，掺杂浓度1*10 19cm -3。
步骤3：如图3(c)所示，利用光刻及反应离子刻蚀技术在盖层16中定义源漏区域16a；在源漏区域16a之间露出的势垒层15中，通过光刻及刻蚀定义栅极区域；淀积栅电极材料，并通过光刻刻蚀制备栅极电极17。
步骤4：如图3(d)所示，淀积源漏极电极材料，并通过光刻刻蚀制备源漏极电极18、19，完成器件制备。
根据本实施例，在硅基衬底上形成由锗锡(GeSn)材料制备高电子迁移率晶体管，由此，能够提高晶体管的高速性能，并且，作为四族材料的GeSn容易与Si基集成电路制造技术集成。
以上结合具体的实施方式对本申请进行了描述，但本领域技术人员应该清楚，这些描述都是示例性的，并不是对本申请保护范围的限制。本领域技术人员可以根据本申请的精神和原理对本申请做出各种变型和修改，这些变型和修改也在本申请的范围内。

Claims (6)

  1. 一种硅基锗锡(GeSn)高电子迁移率晶体管，包括：
    硅基衬底；
    位于所述硅基衬底上的缓冲层；
    位于所述缓冲层上的沟道层，所述沟道层为锗锡(GeSn)材料；以及
    位于所述沟道层上的间隔层，势垒层和盖层，所述间隔层，势垒层和盖层为III-V族半导体材料，
    其中，
    所述间隔层与沟道层的界面形成二维电子气，
    所述缓冲层厚度大于500nm。
  2. 如权利要求1所述的硅基锗锡(GeSn)高电子迁移率晶体管，其中，
    所述硅基衬底的材料为硅或绝缘体上的硅，
    所述缓冲层材料为锗或者锗硅(SiGe)。
  3. 如权利要求1所述的硅基锗锡(GeSn)高电子迁移率晶体管，其中，
    所述沟道层的材料为Ge (1-x)Sn x，其中，0.06<x<0.3。
  4. 如权利要求1所述的硅基锗锡(GeSn)高电子迁移率晶体管，其中，
    所述间隔层，势垒层和盖层的材料为铟铝磷(InAlP)，铟铝砷(InAlAs)，铟镓磷(InGaP)或者铟镓砷(InGaAs)。
  5. 如权利要求1所述的硅基锗锡(GeSn)高电子迁移率晶体管，其中，
    所述间隔层未掺杂，所述势垒层和所述盖层均掺杂，并且，所述盖层的掺杂浓度高于所述势垒层的掺杂浓度。
  6. 如权利要求1所述的硅基锗锡(GeSn)高电子迁移率晶体管，其中所述势垒层与栅电极连接，
    所述盖层与源电极和漏电极连接。
PCT/CN2019/070518 2018-09-27 2019-01-05 一种硅基锗锡高电子迁移率晶体管 WO2020062706A1 (zh)

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Citations (4)

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Publication number Priority date Publication date Assignee Title
CN101132022A (zh) * 2007-09-29 2008-02-27 西安电子科技大学 基于组份渐变GaN MISFET的GaN器件及制备方法
US20130105863A1 (en) * 2011-10-27 2013-05-02 Samsung Electronics Co., Ltd. Electrode structures, gallium nitride based semiconductor devices including the same and methods of manufacturing the same
CN103311306A (zh) * 2013-06-26 2013-09-18 重庆大学 带有InAlP盖层的GeSn沟道金属氧化物半导体场效应晶体管
CN103594506A (zh) * 2012-08-16 2014-02-19 中国科学院微电子研究所 半导体器件

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Publication number Priority date Publication date Assignee Title
CN101132022A (zh) * 2007-09-29 2008-02-27 西安电子科技大学 基于组份渐变GaN MISFET的GaN器件及制备方法
US20130105863A1 (en) * 2011-10-27 2013-05-02 Samsung Electronics Co., Ltd. Electrode structures, gallium nitride based semiconductor devices including the same and methods of manufacturing the same
CN103594506A (zh) * 2012-08-16 2014-02-19 中国科学院微电子研究所 半导体器件
CN103311306A (zh) * 2013-06-26 2013-09-18 重庆大学 带有InAlP盖层的GeSn沟道金属氧化物半导体场效应晶体管

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