CN103339728B - 具有拥有低于主体区域的带隙的带隙的连接区域的存储器装置 - Google Patents

具有拥有低于主体区域的带隙的带隙的连接区域的存储器装置 Download PDF

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CN103339728B
CN103339728B CN201280007365.6A CN201280007365A CN103339728B CN 103339728 B CN103339728 B CN 103339728B CN 201280007365 A CN201280007365 A CN 201280007365A CN 103339728 B CN103339728 B CN 103339728B
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刘海涛
李健
钱德拉·穆利
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Micron Technology Inc
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Abstract

本发明涉及存储器装置，其展示为包含主体区域及连接区域，所述连接区域由具有低于所述主体区域的带隙的半导体形成。连接区域配置可在擦除操作期间提供增加的栅极诱发的漏极泄漏。所展示的配置可将可靠偏压提供到主体区域以用于例如擦除的存储器操作，且在升压操作期间使电荷容纳在所述主体区域中。

Description

具有拥有低于主体区域的带隙的带隙的连接区域的存储器装置
优先权申请案
本专利申请案主张受益于在2011年2月3日提出申请的第13/020,337号美国申请案的优先权，所述美国申请案的全文以引用的方式并入本文中。
技术领域
背景技术
总是需要较高存储器密度以提供具有较高存储器容量的较小装置。将存储器装置横向地形成于半导体芯片的表面上使用大量芯片有效面积。需要具有新配置的经改进存储器装置以进一步使存储器密度增加超过传统横向形成的存储器装置。
发明内容
附图说明
图1展示根据本发明的实施例的存储器装置。
图2展示根据本发明的实施例的图1的存储器装置的一部分的框图。
图3展示根据本发明的实施例的另一存储器装置。
图4展示根据本发明的实施例的图3的存储器装置的一部分的框图。
图5展示根据本发明的实施例的在擦除操作期间的模拟栅极诱发的漏极泄漏。
图6展示根据本发明的实施例的使用存储器装置的信息处置系统。
具体实施方式
在本发明的以下详细说明中，参考形成本发明的一部分且其中以图解方式展示其中可实践本发明的特定实施例的附图。充分详细地描述这些实施例以使得所属领域的技术人员能够实践本发明。可利用其它实施例且可做出逻辑、电、材料改变等。
此申请案中所使用的术语“水平”定义为平行于衬底(例如晶片或裸片)的常规平面或表面的平面，而不管所述衬底的定向如何。术语“垂直”指代垂直于如上文所定义的水平的方向。例如“在......上(on)”、“侧(side)”(如在“侧壁(sidewall)”中)、“高于(higher)”、“低于(lower)”、“在......上方(over)”及“在......下方(under)”的介词是相对于在衬底的顶表面上的常规平面或表面而定义，而不管所述衬底的定向如何。因此，以下详细说明不应视为具限制性意义，且本发明的范围仅由所附权利要求书连同此些权利要求书在其内受保护的等效内容的全部范围来定义。
图1展示形成于衬底102上的存储器装置100。一(多个)电荷存储层112(例如，穿隧电介质层、多晶硅层及电荷阻挡层的组合；氮化物层、氧化物层及氮化物层的组合；或不管是当前已知还是将来开发的可提供电荷存储功能的其它任何其它层或层的组合)大致环绕经伸长主体区域110以形成对应于多个栅极114中的每一者的相应电荷结构(其还可大致环绕经伸长主体区域110及一(多个)电荷存储层112的相应横截面)。第一选择栅极120及第二选择栅极122展示为将经伸长主体区域110选择性地分别电耦合到漏极区域132及源极区域130。电介质104可填充于组件(例如上文所描述的那些组件)之间的空间中。
图1展示一实施例，其中经伸长主体区域110形成具有一对面向上的端部的“U”形。另一实例性配置(未展示)包含线性垂直经伸长主体区域110，其一端面向上，且另一端面向下。另一实例性配置(未展示)包含在任一侧上具有端部的水平线性经伸长主体区域110。与其中组件较深地形成于结构中的实施例相比，具有两个面向上的端部的实施例(例如大致“U”形配置)可使得一些组件在制造期间更易于形成于经伸长主体区域110的端部处。
在一个实例中，经伸长主体区域110由p型半导体材料形成。源极区域130及漏极区域132展示为分别耦合到经伸长主体区域110的第一端111及第二端113。在一个实例中，源极区域130及漏极区域包含n型半导体材料，例如n+多晶硅。在操作中，源极区域130到经伸长主体区域110、到漏极区域132的路径充当n-p-n晶体管，其中选择栅极120、122及栅极114操作以允许或抑制沿所述通路的信号传输。在所展示的实例中，源极区域130、经伸长主体区域110、漏极区域132、选择栅极120、122及栅极114共同形成存储器单元串101。
源极线126及数据线(例如位线128)展示为分别耦合到源极区域130及漏极区域132。在一个实施例中，插塞124用于将位线128耦合到漏极区域132。因此，在此实施例中漏极区域132可描述为“间接耦合”到位线128。源极线126、位线128及插塞124中的每一者可包括金属、由金属组成或基本上由金属组成，例如铝、铜或钨，或这些或其它导体金属的合金。在本发明中，术语“金属”进一步包含金属氮化物或主要作为导体操作的其它材料。
图2展示图1的存储器单元串101的框图。在一个实施例中，连接区域134位于源极区域130与主体区域110之间，且用于将源极区域130耦合到主体区域110。举例来说，连接区域134可在一端上直接耦合到源极区域130且在另一端上直接耦合到主体区域110。在一个实施例中，连接区域134包括半导体材料、由半导体材料组成或基本上由半导体材料组成，所述半导体材料具有低于用于形成主体区域110的半导体材料的带隙的带隙。在一个实例中，主体区域包括硅、由硅组成或基本上由硅组成。在一个实例中，主体区域由p型硅形成。硅具有约1.11eV的带隙。
用于具有低于硅的带隙的连接区域134的若干实例性材料包含锗(约0.67eV)、锑化镓(约0.7eV)、氮化铟(约0.7eV)、砷化铟(约0.36eV)、硫化铅(约0.37eV)、硒化铅(约0.27eV)、碲化铅(约0.29eV)及硅锗。
在一个或一个以上实施例中，连接区域134包括外延硅锗、由外延硅锗组成或基本上由外延硅锗组成。由于紧密的晶格匹配及与现有硅处理设备的相容性，硅锗适于与硅一起使用。硅锗可表示为SixGe1-x，其中x指示每一成分的合金分数。随着x变化，硅锗的带隙变化。硅锗的几种合金组合展现低于硅的带隙。在一个实例中，硅锗包含SixGe1-x，其中x介于0.2与0.8之间。在一个实例中，硅锗包含SixGe1-x，其中x介于0.4与0.6之间。在一个实例中，硅锗包含SixGe1-x，其中x为约0.5。
在其中连接区域134具有低于主体区域的带隙的带隙的实施例中，增加的栅极诱发的漏极泄漏可能位于连接区域134与主体区域110之间的接口136处。与其中仅主体区域110半导体材料邻近于源极选择栅极122而存在的配置相比，图2配置的栅极诱发的漏极泄漏有所增加。在方向137上的增加的栅极诱发的漏极泄漏提供到主体区域110中的更可靠电荷流以偏置所述主体区域。在若干存储器操作(例如擦除操作)中需要可靠的偏压，其中使用大电压差。
在未选择用于擦除操作的存储器单元串101中，可使用升压操作来偏置未选择串101的主体区域110以抑制未选择串的电荷存储结构被擦除。在升压操作中，至少部分地经由主体区域到栅极114上的所施加电压的电容性耦合而将电压施加到主体区域110。举例来说，可将10伏置于栅极114上，且一定量的所述偏压电压(举例来说，约7伏)经由耦合传送到主体区域110。
使用升压操作，期望在主体区域110内维持电荷。因此，在升压操作期间期望低栅极诱发的漏极泄漏。在图2中，主体区域110邻近于源极选择栅极122的边缘138由硅或具有高于连接区域134的带隙的另一半导体材料形成。与在擦除操作期间在接口136处沿方向137的栅极诱发的漏极泄漏相比，在升压操作期间在边缘138处沿方向139的栅极诱发的漏极泄漏较低。
使用如上文所描述的具有不同带隙的材料的配置在擦除操作期间提供主体区域110的可靠偏压，且还在升压操作期间提供主体区域110中的可靠电荷维持。
图3展示形成于衬底202上的存储器装置200。一(多个)电荷存储层212大致环绕经伸长主体区域210以形成对应于多个栅极214中的每一者的相应电荷结构(其还可大致环绕经伸长主体区域210及一(多个)电荷存储层212的相应横截面)。第一选择栅极220及第二选择栅极222展示为选择性地将经伸长主体区域210分别耦合到漏极区域232及源极区域230。电介质204可填充于组件(例如上文所描述的那些组件)之间的空间中。在所展示的实例中，源极区域230、经伸长主体区域210、漏极区域232、选择栅极220、222及栅极214共同形成存储器单元串201。
类似于上文所描述的实施例，源极线226及位线228展示为分别耦合到源极区域230及漏极区域232。在一个实施例中，插塞224用于将位线228耦合到漏极区域232。
图1及2图解说明具有仅位于主体区域110的源极端处的源极连接区域134的存储器装置100的实施例。图3图解说明存储器装置200，其包含将主体区域210耦合到源极区域230的源极连接区域234，及将主体区域210耦合到漏极区域232的漏极连接区域236。类似于图1及2的实例性配置中的操作，图3及4的存储器装置200提供在方向241及243上的第一栅极诱发的漏极泄漏，及在方向242及244上的第二栅极诱发的漏极泄漏，第二栅极诱发的漏极泄漏低于第一栅极诱发的漏极泄漏。
在选定实施例中，添加漏极连接区域236进一步增强存储器装置200，且在擦除操作期间提供对主体区域210的可靠偏置，且还在升压操作期间提供主体区域210中的可靠电荷维持。在存储器装置配置(例如存储器装置200的大致“U”形配置)中，形成邻近于漏极的第二连接区域是简单的，且可为合意的。其它配置(例如其中漏极埋入于主体区域下方)仅可使用邻近于源极区域230的单个连接区域，例如连接区域234。
图5展示栅极诱发的漏极泄漏的模拟线510，其中源极选择栅极仅邻近于硅主体区域(对于此模拟，带隙估计为1.08eV)。线512图解说明根据上文所描述的实施例的配置的栅极诱发的漏极泄漏，其中源极选择栅极还邻近于具有0.88eV的带隙的源极连接区域。线514图解说明根据上文所描述的实施例的配置的栅极诱发的漏极泄漏，其中源极选择栅极还邻近于具有0.68eV的带隙的源极连接区域。举例来说，如从图可见，添加具有低于硅的带隙的连接区域在擦除操作期间提供栅极诱发的漏极泄漏的显著增加。
图6中包含例如计算机的信息处置系统的实施例以展示本发明的高级装置应用的实施例。图6是并入有如上文所描述的根据本发明的实施例的存储器装置的信息处置系统600的框图。信息处置系统600仅是其中可使用本发明的解耦系统的电子系统的一个实施例。其它实例包含但不限于：平板计算机、相机、个人数据助理(PDA)、蜂窝式电话、MP3播放机、飞行器、卫星、军用车辆等。
在此实例中，信息处置系统600包括数据处理系统，其包含用以耦合所述系统的各种组件的系统总线602。系统总线602提供信息处置系统600的各种组件当中的通信链路且可实施为单个总线、总线的组合或以任何其它适合方式实施。
芯片组合件604耦合到系统总线602。芯片组合件604可包含任何电路或电路的操作相容组合。在一个实施例中，芯片组合件604包含可为任何类型的处理器606。如本文中所使用，“处理器”意指任何类型的计算电路，例如但不限于：微处理器、微控制器、图形处理器、数字信号处理器(DSP)或任何其它类型的处理器或处理电路。
在一个实施例中，存储器装置607包含于芯片组合件604中。在一个实施例中，存储器装置607包含根据上文所描述的实施例的NAND存储器装置。
在一个实施例中，芯片组合件604中包含除处理器芯片之外的额外逻辑芯片608。除处理器之外的逻辑芯片608的实例包含模/数转换器。逻辑芯片608上的其它电路(例如定制电路、特殊应用集成电路(ASIC)等)还包含于本发明的一个实施例中。
信息处置系统600还可包含外部存储器611，所述外部存储器又可包含适合于特定应用的一个或一个以上存储器元件，例如一个或一个以上硬盘驱动器612及/或处置可装卸式媒体613(例如光盘(CD)、快闪驱动机、数字视频盘(DVD)等等)的一个或一个以上驱动机。如上文实例中所描述而构造的半导体存储器裸片包含于信息处置系统600中。
信息处置系统600还可包含显示装置609(例如监视器)、额外外围组件610(例如扬声器等)及键盘及/或控制器614，所述控制器可包含鼠标、轨迹球、游戏控制器、语音辨识装置或准许系统用户将信息输入到信息处置系统600中及从信息处置系统600接收信息的任何其它装置。
虽然描述本发明的若干实施例，但上述清单并非打算为穷尽性的。尽管本文中已图解说明及描述特定实施例，但所属领域的技术人员将了解，旨在实现相同目的的任何布置均可替换所展示的特定实施例。此申请案打算涵盖本发明的任何改动或变化。应理解，上述说明打算为说明性的而非限制性的。所属领域的技术人员在研究上述说明后旋即将明了上述实施例的组合及其它实施例。

Claims (27)

1.一种存储器装置，其包括：
主体区域，其包括具有第一带隙的半导体；
耦合到所述主体区域的第一端的源极区域，及耦合到所述主体区域的第二端的漏极区域；
多个栅极，其沿所述主体区域的长度，所述多个栅极中的每一者通过至少相应电荷存储结构而与所述主体区域分离；
连接区域，其包括具有第二带隙的半导体，所述第二带隙低于所述第一带隙，所述连接区域将所述源极区域耦合到所述主体区域；及
源极选择栅极，其邻近于所述主体区域及所述连接区域。
2.根据权利要求1所述的存储器装置，其中所述主体区域为垂直定向。
3.根据权利要求1所述的存储器装置，其中所述主体区域为水平定向。
4.根据权利要求1所述的存储器装置，其中所述主体区域形成具有面向上的端的“U”形。
5.根据权利要求1所述的存储器装置，其中所述主体区域包括经掺杂硅。
6.根据权利要求5所述的存储器装置，其中所述主体区域包括p型硅。
7.根据权利要求1所述的存储器装置，其中所述连接区域包括选自由以下各项组成的群组的半导体：锗、锑化镓、氮化铟、砷化铟、硫化铅、硒化铅、碲化铅及硅锗。
8.根据权利要求1所述的存储器装置，其中所述连接区域直接耦合到所述源极区域且其中所述连接区域直接耦合到所述主体区域。
9.根据权利要求1所述的存储器装置，其中所述主体区域包括硅且所述连接区域包括硅锗。
10.根据权利要求9所述的存储器装置，其中所述硅锗区域包括外延硅锗。
11.根据权利要求10所述的存储器装置，其中所述外延硅锗为SixGe1-x，其中x为0.5。
12.根据权利要求1所述的存储器装置，其中所述连接区域包括源极连接区域，且其进一步包括：
漏极连接区域，其包括具有低于所述第一带隙的带隙的半导体，所述漏极连接区域将所述漏极区域耦合到所述主体区域；及
漏极选择栅极，其邻近于所述主体区域及所述漏极连接区域。
13.根据权利要求12所述的存储器装置，其中所述源极连接区域及所述漏极连接区域两者是由相同材料形成。
14.根据权利要求12所述的存储器装置，其中所述漏极连接区域包括硅锗。
15.根据权利要求1所述的存储器装置，其中与在包含所述主体区域的串的擦除操作期间所述主体区域中的栅极诱发的漏极泄漏电流相比，在包含所述主体区域的所述串的升压操作期间所述主体区域中的栅极诱发的漏极泄漏电流较低。
16.根据权利要求1所述的存储器装置，其中所述连接区域位于所述源极区域与所述主体区域之间。
17.一种存储器装置，其包括：
存储器单元串，其包含：
主体区域，其包括具有第一带隙的半导体，所述主体区域具有第一面向上的端及第二面向上的端；
漏极区域，其耦合到所述第一面向上的端；
源极区域，其耦合到所述第二面向上的端；
多个栅极，其沿所述主体区域的长度；
连接区域，其包括具有第二带隙的半导体，所述第二带隙低于所述第一带隙，
所述连接区域将所述源极区域耦合到所述主体区域；
源极选择栅极，其邻近于所述主体区域及所述连接区域；及
数据线，其耦合到所述漏极区域；及
源极线，其耦合到所述源极区域。
18.根据权利要求17所述的存储器装置，其中所述连接区域包括硅锗。
19.根据权利要求17所述的存储器装置，其中所述连接区域包括SixGe1-x，其中x为0.5。
20.根据权利要求17所述的存储器装置，其中所述连接区域包括外延硅锗。
21.根据权利要求17所述的存储器装置，其中所述主体区域包括经p掺杂硅。
22.根据权利要求17所述的存储器装置，其中所述源极区域与邻近存储器单元串共享。
23.根据权利要求17所述的存储器装置，其中所述存储器单元串为U形。
24.根据权利要求17所述的存储器装置，其中所述栅极中的每一者与邻近存储器单元串共享。
25.根据权利要求17所述的存储器装置，其中所述栅极中的每一者环绕所述主体区域的相应横截面。
26.根据权利要求17所述的存储器装置，其中所述主体区域包括伸长主体区域。
27.根据权利要求17所述的存储器装置，其中所述栅极的第一部分与第一邻近存储器单元串共享，且其中所述栅极的第二部分与第二邻近存储器单元串共享。
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US9953710B2 (en) 2018-04-24
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JP2014504810A (ja) 2014-02-24
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