CN103299484A - 各向异性导电膜 - Google Patents

各向异性导电膜 Download PDF

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CN103299484A
CN103299484A CN201280005956XA CN201280005956A CN103299484A CN 103299484 A CN103299484 A CN 103299484A CN 201280005956X A CN201280005956X A CN 201280005956XA CN 201280005956 A CN201280005956 A CN 201280005956A CN 103299484 A CN103299484 A CN 103299484A
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anisotropic conductive
conductive film
semiconductor chip
projection
melt viscosity
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CN103299484B (zh
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相崎亮太
田中芳人
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Dexerials Corp
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Sony Chemical and Information Device Corp
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Abstract

导电性粒子分散于绝缘性粘接剂中而成的各向异性导电膜使用复原率为10～46%的导电性粒子。此外，将各向异性导电膜的最低熔融粘度设为［η0］，将在比显示最低熔融粘度的温度T0低60℃的温度T1下的熔融粘度设为［η1］时，满足以下的式（1）和（2），1.0×102Pa?sec≤［η0］≤1.0×106Pa?sec （1），1＜［η1］/［η0］≤30 （2），优选进一步满足以下的式（3），5≤［η1］/［η0］≤15　（3）。

Description

各向异性导电膜
技术领域
本发明涉及导电性粒子分散于绝缘性粘接剂中而成的各向异性导电膜、利用其的连接结构体的制造方法。
背景技术
导电性粒子分散于绝缘性粘接剂中而成的各向异性导电膜在将半导体芯片安装于配线基板时使用，伴随配线基板的安装密度的增大，半导体芯片的凸块排列（                                                
Figure 621711DEST_PATH_IMAGE001
）也高密度化。作为这种半导体芯片的高密度的凸块排列的例子，可以列举出在半导体芯片的凸块形成面的边缘部以2列的交错状（
Figure 444174DEST_PATH_IMAGE002
）进行凸块排列。
为了将具有这样细距的交错排列（）的凸块的半导体芯片经由各向异性导电膜以使各凸块之间的导通电阻相同的方式切实地连接在配线基板上，要求使导电性粒子充分存在于压接区域，同时将过量的绝缘性粘接剂从压接区域排除。
以往，为了满足这样的要求，着眼于各向异性导电膜的最低熔融粘度［η0］与、在比显示最低熔融粘度的温度T0低30℃的温度T1下的熔融粘度［η1］的关系，提出了使最低熔融粘度［η0］为1.0×102～1.0×106Pa?sec，且使［η1］/［η0］的比为1（不包括1）～3的方案（专利文献1）。
现有技术文献
专利文献
专利文献1：日本特开2009-32657号公报。
发明内容
为了使半导体芯片的凸块排列更高密度化，实施在半导体芯片的凸块形成面的边缘部将凸块排列成3列的交错状。将专利文献1的技术适用于这样的3列交错凸块排列的半导体芯片时，与2列交错排列的凸块相比，绝缘性粘接剂的熔融物难以从压接区域排除，滞留于3列交错排列的长度方向的中央部附近，其结果是3列交错排列的长度方向的中央部附近的导电性粒子与长度方向的两侧的导电性粒子相比，变得难以压碎，在可以目视观察各向异性导电连接处的情况下，不能在各向异性导电连接处观察到导电性粒子的均匀的压痕的显现，结果存在各向异性导电连接处的导通电阻值变高的问题。
此外，作为配线基板的电极，适用在相对于周围形成的保护膜为凹进的位置上形成的电极垫（
Figure 470959DEST_PATH_IMAGE004
）的情况下，由于保护膜与凸块的距离比凸块与电极垫间的距离短，因而挟持于保护膜与凸块之间的导电性粒子成为隔离物（spacer），夹持于凸块与电极垫之间的导电性粒子在热压接时难以被压碎，在可以目视观察各向异性导电连接处的情况下，与前述3列交错排列的情况同样地，不能在各向异性导电连接处观察到导电性粒子的均匀的压痕的显现，存在各向异性导电连接处的导通电阻值变高的问题。
本发明是为了解决以上问题而进行的，其目的在于，使用最低熔融粘度［η0］为1.0×102～1.0×106Pa?sec的各向异性导电膜，将具有3列交错排列凸块的半导体芯片各向异性导电连接在配线基板的电极上时，对于3列交错排列的长度方向的中央部附近的导电性粒子，与长度方向的两侧的导电性粒子相比，不会难以压碎，换言之，可在各向异性导电连接处观察到导电性粒子的均匀的压痕的显现，不使各向异性导电连接处的导通电阻值增大。另外，本发明的目的还在于使用最低熔融粘度［η0］为1.0×102～1.0×106Pa?sec的各向异性导电膜，将半导体芯片向在相对于周围形成的保护膜为凹进的位置上形成的配线基板的电极垫进行各向异性导电连接时，挟持于凸块与电极垫之间的导电性粒子在热压接时不会难以压碎，换言之，可在各向异性导电连接处观察到导电性粒子的均匀的压痕的显现，不使各向异性导电连接处的导通电阻值增大。
本发明人等着眼于表示导电性粒子的塑性变形程度的复原率，发现复原率过大时，有导电性粒子难以压碎，导通电阻值增大的倾向，相反，复原率即使过小，也有导电性粒子难以侵入凸块或电极，导通电阻值增大的倾向。并且，以将导电性粒子的复原率设定在特定的范围内为前提时，着眼于各向异性导电膜的最低熔融粘度［η0］与、在比显示最低熔融粘度的温度T0低的温度T1下的熔融粘度［η1］的关系，发现通常，形成凸块容易挤入的各向异性导电膜的熔融粘度的温度与专利文献1的情况不同，是比显示最低熔融粘度的温度T0低60℃的温度， 进一步研究该温度下的熔融粘度与最低熔融粘度的比例，结果发现该比例为30以下时，可以实现上述目的，从而完成了本发明。
即，本发明提供一种各向异性导电膜，其为用于将半导体芯片的凸块与配线基板的电极进行各向异性导电连接的各向异性导电膜，该各向异性导电膜是导电性粒子分散于绝缘性粘接剂中而成的各向异性导电膜，其特征在于，
导电性粒子的复原率为10～46%，
将各向异性导电膜的最低熔融粘度设为［η0］，将在比显示最低熔融粘度的温度T0低60℃的温度T1下的熔融粘度设为［η1］时，满足以下的式（1）和（2）。  
1.0×102Pa?sec≤［η0］≤1.0×106Pa?sec　　　　   （1）
1＜［η1］/［η0］≤30　　　　　　　　　　　　　（2）。
这里，导电性粒子的复原率（%）是指，在将对粒径A的导电性粒子施加1g的负荷使其变形后，除去负荷时的导电性粒子的粒径设为B时，通过以下的式子定义的物性。
导电性粒子的复原率（%）=（B/A）×100。
此外，熔融粘度是指，使用旋转流变仪（例如TA　Instruments公司），在规定的测定条件（升温速度 10℃/分钟; 测定压力 5g恒定；使用测定板直径 8mm）下进行测定而得到的值。
此外，本发明提供通过将半导体芯片的凸块与配线基板的电极进行各向异性导电连接来制造连接结构体的方法，其中，
将上述的本发明的各向异性导电膜临时粘贴在配线基板的电极上，
将半导体芯片由其凸块侧临时设置在临时粘贴了的各向异性导电膜上，
通过利用加热焊接机（
Figure 202155DEST_PATH_IMAGE005
）对临时设置的半导体芯片进行加热加压，从而将半导体芯片的凸块与配线基板的电极进行各向异性导电连接，使各向异性导电膜热固化，
及提供通过该制造方法制造的连接结构体。
对于本发明的各向异性导电膜，由于使用显示规定的复原率的导电性粒子，并且将各向异性导电膜的最低熔融粘度设为［η0］，将在比显示最低熔融粘度的温度T0低60℃的温度T1下的熔融粘度设为［η1］时，满足前述式（1）和（2），因而将具有3列交错排列的凸块的半导体芯片与配线基板的电极进行各向异性导电连接时，对于3列交错排列的长度方向的中央部附近的导电性粒子，可以与长度方向的两侧的导电性粒子同样地在热压接时被压碎，在可以目视观察各向异性导电连接处的情况下，可以在各向异性导电连接处观察到导电性粒子的均匀的压痕的显现，结果可以不使各向异性导电连接处的导通电阻值增大。
此外，作为配线基板的电极，适用在相对于周围形成的保护膜为凹进的位置上形成的电极垫时，挟持于凸块与电极垫之间的导电性粒子在热压接时不会难以压碎，在可以目视观察各向异性导电连接处的情况下，与前述3列交错排列的情况同样地，可以在各向异性导电连接处观察到导电性粒子的均匀的压痕的显现，可以不使各向异性导电连接处的导通电阻值增大。
具体实施方式
本发明为一种各向异性导电膜，其为用于将半导体芯片的凸块与配线基板的电极进行各向异性导电连接的、导电性粒子分散于绝缘性粘接剂中而成的各向异性导电膜，其特征在于，
导电性粒子的复原率为10～46%，
将各向异性导电膜的最低熔融粘度设为［η0］，将在比显示最低熔融粘度的温度T0低60℃的温度T1下的熔融粘度设为［η1］时，满足以下的式（1）和（2）。  
1.0×102Pa?sec≤［η0］≤1.0×106Pa?sec　　　　   （1）
1＜［η1］/［η0］≤30　　　　　　　　　　　　　（2）。
本发明中，作为导电性粒子，使用复原率为10～46%、优选为15～35%的导电性粒子。复原率不足10%时，其本身容易压碎，相反难以侵入半导体芯片的凸块或配线基板的电极，因而有导通电阻值增大的倾向，复原率超过46%时，反弹力过强，难以压碎，仍有导通电阻值增大的倾向。
此外，本发明中，使［η1］/［η0］的比例为30以下，这是因为该比例超过30时，由于交错排列凸块的内外树脂的粘度差，导致无法进行充分的连接。此外，由于［η1］一定是比［η0］大的值，因而［η1］/［η0］的比为超过1的数值。从上述粘度差的观点出发，优选的比的范围为以下的式（3）的范围。  
5≤［η1］/［η0］≤15　　　　　　　　　　　　　 （3）。
本发明的各向异性导电膜的最低熔融粘度［η0］为1.0×102～1.0×106Pa?sec的原因在于，最低熔融粘度低于该范围时，容易产生气泡，高于该范围时，安装时需要高压。
此外，对于本发明的各向异性导电膜，显示最低熔融粘度的温度如果T0过低，则安装时凸块接触至配线时固化，无法进行充分的连接，如果过高，则安装时需要长时间，因而优选为90～120℃，更优选为90～100℃。
作为构成本发明的各向异性导电膜的导电性粒子，可以适当选择在以往的各向异性导电膜中使用的导电性粒子使用。可以列举出，例如金、镍、焊料等金属粒子、用Ni/Au薄膜将苯代三聚氰胺树脂覆膜而得到的金属被覆树脂粒子、用绝缘树脂薄膜在这些粒子的表面被覆而得到的绝缘被覆导电性粒子等。作为这些粒子的粒径，通常为1～10μm，优选为2～5μm。
作为构成本发明的各向异性导电膜的绝缘性粘接剂，也可以适当选择在以往的各向异性导电膜中使用的粘接剂使用。例如，绝缘性粘接剂可以适当含有苯氧基树脂等成膜性树脂、液态或固态环氧树脂等固化成分、胺系固化剂、咪唑系固化剂等固化剂、硅烷偶联剂、根据需要的甲苯等有机溶剂等、进而颜料、防锈剂等各种添加剂。
本发明的各向异性导电膜可以按照常法将以上的成分混合，加工成膜状来进行制造。
可以通过适当选择成膜性树脂或固化成分、固化剂等的种类、或它们的含量、导电性粒子的种类、粒径或含量、溶剂的种类或含量等，而调整本发明的各向异性导电膜的最低熔融粘度和［η1］/［η0］的比，使其在规定范围。特别优选通过配合有机填料进行调整。作为这样的有机填料，例示出丁二烯共聚物、丙烯酸共聚物、苯乙烯共聚物等绝缘性树脂填料。A-B型或者A-B-A型嵌段共聚物是对于聚合性树脂成分的相容性链段与非相容性链段形成了A-B型或者A-B-A型嵌段共聚物的物质。作为这样的嵌段共聚物，特别优选苯乙烯-丙烯酸嵌段共聚物、苯乙烯-丁二烯嵌段共聚物、苯乙烯-醋酸乙烯酯嵌段共聚物、苯乙烯-乙烯-丁烯嵌段共聚物、苯乙烯-乙烯-丙烯嵌段共聚物、苯乙烯-乙烯-苯乙烯嵌段共聚物、苯乙烯-异戊二烯嵌段共聚物等苯乙烯系嵌段共聚物。这些苯乙烯系嵌段共聚物中，从分散性与粘度平衡的观点出发，最优选苯乙烯的共聚组成比为20wt%以上的物质。需要说明的是，可以在这些苯乙烯系嵌段共聚物中，以任意的范围导入环氧基或羧基，此外，作为这种嵌段共聚物，可以使用市售品。
作为这样的绝缘性树脂填料的粒径，过小时，分散困难，过大时，对利用配线上的导电性粒子进行的连接的不良影响较大，因而优选为0.01～10μm，更优选为0.1～1μm。
以上说明的本发明的各向异性导电膜可以优选适用于将半导体芯片的凸块与配线基板的电极进行各向异性导电连接来制造连接结构体的方法。该制造方法的特征在于，将前述的本发明的各向异性导电膜临时粘贴在配线基板的电极上，将半导体芯片由其凸块侧临时设置于临时粘贴了的各向异性导电膜上，利用加热焊接机对临时设置的半导体芯片进行加热加压，从而将半导体芯片的凸块与配线基板的电极进行各向异性导电连接，使各向异性导电膜热固化。此外，通过该制造方法制造的连接结构体也是本发明的一部分。
作为半导体芯片，从可以充分发挥本发明的各向异性导电膜的特性的观点出发，优选使用具有2列或者3列的交错排列的凸块的半导体芯片。
需要说明的是，作为构成这样的连接结构体的配线基板，一直以来适用各向异性导电膜的配线基板在所能达到的范围内，可以列举出柔性配线基板、环氧玻璃配线基板、层叠配线基板、显示器用透明玻璃或者树脂配线基板等。
实施例
以下通过实施例具体说明本发明。
参考例1（导电性粒子的制备）
向调整了二乙烯基苯、苯乙烯、甲基丙烯酸丁酯的混合比的单体溶液中投入作为聚合引发剂的过氧化苯甲酰，一边将得到的混合液高速且均匀搅拌，一边加热，从而进行单体的聚合反应，由此获得微粒分散液。将微粒从该微粒分散液中过滤分离，进行减压干燥，由此获得作为微粒的凝集体的块状物（
Figure 195519DEST_PATH_IMAGE006
）。进一步地，通过粉碎该块状物，获得平均粒径为3.0μm的苯乙烯系树脂粒子。
通过浸渍法使钯催化剂担载于获得的平均粒径为3μm的苯乙烯系树脂粒子（5g）上。接着，使用由硫酸镍六水合物、次亚磷酸钠、柠檬酸钠、三乙醇胺和硝酸铊制备的非电解镀镍液（pH12、电镀液温度50℃）对该苯乙烯系树脂粒子进行非电解镀镍，获得作为导电性粒子的表面形成有镀镍层（金属层）的镍被覆树脂粒子。得到的导电性粒子的平均粒径为3～4μm的范围。这里，通过控制非电解镀镍时间，分别制备用于表1所示的复原率不同的各实施例和比较例中的导电性粒子。
参考例2（最低熔融粘度调整用的苯乙烯系嵌段共聚物的制备）
向具备温度计、氮导入管、搅拌机和冷凝器的玻璃制反应器中，加入水300质量份、部分皂化聚乙烯醇（ゴーセーノールKH-17、日本合成化学工业公司制）的1%水溶液15质量份以及羟基磷灰石的10%水分散液（スーパータイト10、日本化学工业社制）15质量份。在室温下使聚过氧化物类0.5质量份在前述水溶液中分散1小时后，加入醋酸乙烯酯30质量份，一边向反应器内导入氮，一边在搅拌下在60℃下进行2小时聚合（第一阶段聚合）。然后，冷却至室温，向反应器中加入苯乙烯70质量份，在室温下搅拌1小时。进一步地，一边向反应器中导入氮，一边在80℃下搅拌8小时，在90℃下进行30分钟聚合（第二阶段聚合）。然后，将反应混合物冷却至室温，获得作为沉淀物的聚合物。用5%盐酸130质量份洗涤得到的聚合物，接着用水洗涤，进行过滤分离。通过干燥所得到的聚合物，从而以85%的收率获得白色粒状的苯乙烯系嵌段共聚物。该嵌段共聚物中的苯乙烯与醋酸乙烯酯的共聚组成比为70：30。
实施例1～6、比较例1～2
通过使用行星式搅拌机将表1的成分（质量份）均匀地混合，从而制备涂料，将该涂料涂布于剥离膜，在80℃下预烘5分钟，由此制作各向异性导电膜。需要说明的是，导电性粒子的配合量是使粒子密度为50000个/mm2的量。对于得到的各向异性导电膜，如以下说明的那样，测定熔融粘度和导通电阻，进一步观察适用于各向异性导电连接时的压痕（
Figure DEST_PATH_IMAGE007
）。
＜熔融粘度测定＞
使用旋转流变仪（TA　Instruments公司），在升温速度10℃/分钟；测定压力　5g恒定；使用测定板直径 8mm的条件下测定各向异性导电膜的熔融粘度。得到的最低熔融粘度［η0］（Pa?sec）示于表1。此外，测定在比T0低60℃的温度T1下的熔融粘度［η1］（Pa?sec），计算［η1］/［η0］，得到的结果示于表1。
＜导通电阻测定＞
使各向异性导电膜夹持于边缘部具有3列交错配置了的金凸块的试验用半导体芯片（凸块大小1800μm2、凸块高度15μm、外侧凸块列与中央凸块列以及中央凸块列与内侧凸块列间的各自的距离20μm、各列内的凸块间的距离20μm）、与对应的玻璃基板之间，利用加热加压头以200℃、压力60Mpa进行5分钟的加热加压。根据常法测定此时的外侧凸块与中央凸块列的导通电阻（Ω），通过以下的基准进行评价。得到的结果示于表1。  
等级　　　基准
AA：　 导通电阻值不足3Ω
A：　　导通电阻值为3Ω以上且不足10Ω
B：　　导通电阻值为10Ω以上且不足30Ω
C：　　导通电阻值为30Ω以上。
＜压痕的观察＞
从供于导通电阻测定的热压接样品的玻璃基板侧，以10倍的倍率用显微镜观察各向异性导电膜的各向异性导电连接部中的3列交错排列凸块的长度方向的中央位置、凸块列的长度方向的全长L的0.1L和0.9L的位置这3处，通过以下基准对压痕的均匀性进行评价。得到的结果示于表1。  
等级　　基准
AA：　针对3个观察位置，分别观察10处，结果在任一观察位置中，都在9处以上观察到压痕的情况
A：　 针对3个观察位置，分别观察10处，结果在任一观察位置中，在7处或者8处观察到压痕的情况，除此之外，在9处以上观察到压痕的情况
B：　 针对3个观察位置，分别观察10处，结果在任一观察位置中，在5处或者6处观察到压痕的情况，除此之外，在9处以上观察到压痕的情况
C：　 针对3个观察位置，分别观察10处，结果在任一观察位置上可以观察到的压痕不足5处的情况。
【表1】
由表1可知，实施例1～6的各向异性导电膜的情况下，由于使用的导电性粒子的复原率在10～46%的范围内，最低熔融粘度［η0］也在1.0×102～1.0×106Pa?sec的范围内，并且［η1］/［η0］的比为30以下，因而3列交错配置了的外侧凸块与中央凸块的各自的导通电阻和压痕均匀性没有C评价。
与此相对，比较例1和2的各向异性导电膜的情况下，由于使用的导电性粒子的复原率超过46%，因而导通电阻为C评价，特别是在比较例2的情况下，压痕均匀性评价也为C评价。
产业上的可利用性
本发明的各向异性导电膜在将半导体芯片各向异性导电连接到配线基板上时有用。

Claims (5)

1.各向异性导电膜，其是用于将半导体芯片的凸块与配线基板的电极进行各向异性导电连接的各向异性导电膜，该各向异性导电膜通过使导电性粒子分散于绝缘性粘接剂中而成，其特征在于，
导电性粒子的复原率为10～46%，
将各向异性导电膜的最低熔融粘度设为［η0］，将在比显示最低熔融粘度的温度T0低60℃的温度T1下的熔融粘度设为［η1］时，满足以下的式（1）和（2），
1.0×102Pa?sec≤［η0］≤1.0×106Pa?sec　　　　   （1）
1＜［η1］/［η0］≤30　　　　　　　　　　　　　（2）。
2.根据权利要求1所述的各向异性导电膜，其满足式（3），
5≤［η1］/［η0］≤15　　　　　　　　　　      （3）。
3.制造方法，其为通过将半导体芯片的凸块与配线基板的电极进行各向异性导电连接来制造连接结构体的方法，其中，
将权利要求1所述的各向异性导电膜临时粘贴在配线基板的电极上，
将半导体芯片由其凸块侧临时设置于临时粘贴了的各向异性导电膜上，
通过利用加热焊接机对临时设置的半导体芯片进行加热加压，从而将半导体芯片的凸块与配线基板的电极进行各向异性导电连接，使各向异性导电膜热固化。
4.根据权利要求3所述的制造方法，其中，作为半导体芯片，使用具有2列或者3列交错排列的凸块的半导体芯片。
5.连接结构体，其通过权利要求3或4所述的制造方法制造。
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