CN103226982A - 具有半导体存储电路的半导体装置 - Google Patents
具有半导体存储电路的半导体装置 Download PDFInfo
- Publication number
- CN103226982A CN103226982A CN2013100144855A CN201310014485A CN103226982A CN 103226982 A CN103226982 A CN 103226982A CN 2013100144855 A CN2013100144855 A CN 2013100144855A CN 201310014485 A CN201310014485 A CN 201310014485A CN 103226982 A CN103226982 A CN 103226982A
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- circuit
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000001514 detection method Methods 0.000 claims abstract description 24
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 16
- 238000004891 communication Methods 0.000 abstract description 11
- 238000006243 chemical reaction Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 230000008676 import Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/46—Test trigger logic
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
Claims (4)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012017197 | 2012-01-30 | ||
JP2012-017197 | 2012-01-30 | ||
JP2012245672A JP5963647B2 (ja) | 2012-01-30 | 2012-11-07 | 半導体記憶回路を備えた半導体装置 |
JP2012-245672 | 2012-11-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103226982A true CN103226982A (zh) | 2013-07-31 |
CN103226982B CN103226982B (zh) | 2017-03-01 |
Family
ID=48837395
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310014485.5A Active CN103226982B (zh) | 2012-01-30 | 2013-01-15 | 具有半导体存储电路的半导体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8730747B2 (zh) |
JP (1) | JP5963647B2 (zh) |
KR (1) | KR101952967B1 (zh) |
CN (1) | CN103226982B (zh) |
TW (1) | TWI556251B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113810029A (zh) * | 2020-06-12 | 2021-12-17 | 圣邦微电子(北京)股份有限公司 | 一种检测数据相关性的电路 |
CN115017095A (zh) * | 2022-08-05 | 2022-09-06 | 微传智能科技(常州)有限公司 | 电流输出型ak协议轮速芯片通信系统及方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1386283A (zh) * | 2000-05-09 | 2002-12-18 | 皇家菲利浦电子有限公司 | 包含sram存储器的集成电路及其测试方法 |
CN1501407A (zh) * | 2002-11-14 | 2004-06-02 | ���µ�����ҵ��ʽ���� | 半导体存储装置 |
CN1728283A (zh) * | 2004-07-29 | 2006-02-01 | 海力士半导体有限公司 | 测试半导体存储设备的装置与方法 |
US20070090695A1 (en) * | 2005-10-20 | 2007-04-26 | Fujitsu Limited | Semiconductor device and method of testing the same |
CN101256824A (zh) * | 2007-03-01 | 2008-09-03 | 松下电器产业株式会社 | 半导体集成电路 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08105947A (ja) * | 1994-10-06 | 1996-04-23 | Canon Inc | Ic回路 |
JP3866444B2 (ja) * | 1998-04-22 | 2007-01-10 | 東芝マイクロエレクトロニクス株式会社 | 半導体装置及びその内部信号モニタ方法 |
JP3883087B2 (ja) * | 1998-11-09 | 2007-02-21 | 富士通株式会社 | 半導体記憶装置及び半導体メモリ回路 |
US6651196B1 (en) * | 1999-02-16 | 2003-11-18 | Fujitsu Limited | Semiconductor device having test mode entry circuit |
JP3420967B2 (ja) | 1999-03-17 | 2003-06-30 | 株式会社 沖マイクロデザイン | 半導体集積回路 |
JP2002175699A (ja) * | 2000-09-27 | 2002-06-21 | Toshiba Corp | 半導体装置及び半導体装置のモード設定方法 |
JP4182740B2 (ja) * | 2002-12-06 | 2008-11-19 | 沖電気工業株式会社 | マイクロコンピュータ |
US7443760B2 (en) * | 2005-09-29 | 2008-10-28 | Hynix Semiconductor Inc. | Multi-port memory device with serial input/output interface |
KR100931024B1 (ko) * | 2008-09-19 | 2009-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 테스트 모드 신호 생성 장치 및 그의생성 방법 |
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2012
- 2012-11-07 JP JP2012245672A patent/JP5963647B2/ja active Active
- 2012-12-20 TW TW101148772A patent/TWI556251B/zh active
-
2013
- 2013-01-15 CN CN201310014485.5A patent/CN103226982B/zh active Active
- 2013-01-16 KR KR1020130004769A patent/KR101952967B1/ko active IP Right Grant
- 2013-01-25 US US13/750,481 patent/US8730747B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1386283A (zh) * | 2000-05-09 | 2002-12-18 | 皇家菲利浦电子有限公司 | 包含sram存储器的集成电路及其测试方法 |
CN1501407A (zh) * | 2002-11-14 | 2004-06-02 | ���µ�����ҵ��ʽ���� | 半导体存储装置 |
CN1728283A (zh) * | 2004-07-29 | 2006-02-01 | 海力士半导体有限公司 | 测试半导体存储设备的装置与方法 |
US20070090695A1 (en) * | 2005-10-20 | 2007-04-26 | Fujitsu Limited | Semiconductor device and method of testing the same |
CN101256824A (zh) * | 2007-03-01 | 2008-09-03 | 松下电器产业株式会社 | 半导体集成电路 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113810029A (zh) * | 2020-06-12 | 2021-12-17 | 圣邦微电子(北京)股份有限公司 | 一种检测数据相关性的电路 |
CN115017095A (zh) * | 2022-08-05 | 2022-09-06 | 微传智能科技(常州)有限公司 | 电流输出型ak协议轮速芯片通信系统及方法 |
Also Published As
Publication number | Publication date |
---|---|
US8730747B2 (en) | 2014-05-20 |
JP2013178867A (ja) | 2013-09-09 |
US20130194878A1 (en) | 2013-08-01 |
TWI556251B (zh) | 2016-11-01 |
KR101952967B1 (ko) | 2019-02-27 |
CN103226982B (zh) | 2017-03-01 |
JP5963647B2 (ja) | 2016-08-03 |
TW201345152A (zh) | 2013-11-01 |
KR20130088055A (ko) | 2013-08-07 |
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Effective date of registration: 20160330 Address after: Chiba County, Japan Applicant after: DynaFine Semiconductor Co.,Ltd. Address before: Chiba County, Japan Applicant before: Seiko Instruments Inc. |
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CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Chiba County, Japan Patentee after: ABLIC Inc. Address before: Chiba County, Japan Patentee before: DynaFine Semiconductor Co.,Ltd. |
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CP02 | Change in the address of a patent holder |
Address after: Nagano Patentee after: ABLIC Inc. Address before: Chiba County, Japan Patentee before: ABLIC Inc. |