CN103219947A - 电压调节器 - Google Patents

电压调节器 Download PDF

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CN103219947A
CN103219947A CN2013100265972A CN201310026597A CN103219947A CN 103219947 A CN103219947 A CN 103219947A CN 2013100265972 A CN2013100265972 A CN 2013100265972A CN 201310026597 A CN201310026597 A CN 201310026597A CN 103219947 A CN103219947 A CN 103219947A
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voltage
transistor
nmos pass
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pass transistor
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CN103219947B (zh
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井村多加志
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Ablic Inc
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Seiko Instruments Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45166—Only one input of the dif amp being used for an input signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45478—Indexing scheme relating to differential amplifiers the CSC comprising a cascode mirror circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45681—Indexing scheme relating to differential amplifiers the LC comprising offset compensating means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45702—Indexing scheme relating to differential amplifiers the LC comprising two resistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Amplifiers (AREA)

Abstract

本发明的电压调节器具备将基准电压与对输出晶体管输出的电压进行分压的分压电压之差放大并输出，控制输出晶体管的栅极的第一级放大器及级联型放大电路，其中，第一级放大器具备作为输入晶体管的第一高耐压NMOS晶体管以及作为尾电流源的NMOS晶体管，并且级联型放大电路由作为级联晶体管的第二高耐压NMOS晶体管构成。从而提供能够改善偏移的影响并获得正确的输出电压的电压调节器。

Description

电压调节器
技术领域
本发明涉及改善偏移（offset）的影响的电压调节器。
背景技术
图2是示出现有的放大电路的电路图。
现有的放大电路构成为通常耐压NMOS晶体管301的漏极和高耐压NMOS晶体管302的源极连接，高耐压NMOS晶体管302的漏极与输出端子311连接。这样，能够较高地设定负载阻抗以便能够产生大输出电压振幅，能够提高放大电路整体的增益（例如，参照专利文献1）。
专利文献1：日本特开2005-311689号公报。
发明内容
然而，在现有的电压调节器中，当利用使用高耐压MOS的级联（cascode）放大电路构成放大器时，在第一级放大器产生偏移。
本发明提供能够改善放大器的偏移、获得正确的输出电压的电压调节器。
为了解决现有的课题，本发明设为以下的结构。
一种电压调节器，具备将基准电压与对输出晶体管输出的电压进行分压的分压电压之差放大并输出，控制输出晶体管的栅极的第一级放大器及级联型放大电路，其中，第一级放大器具备作为输入晶体管的第一高耐压NMOS晶体管以及作为尾电流源的NMOS晶体管，级联型放大电路具备作为级联晶体管的第二高耐压NMOS晶体管。
本发明的电压调节器能够改善在第一级放大器产生的偏移，能够不增大尾（tail）电流源的大小并确保驱动能力。
附图说明
图1是示出本实施方式的电压调节器的电路图。
图2是现有的使用高耐压MOS的级联放大电路的电路图。
附图标记说明
100 接地端子；101 电源端子；110 基准电压电路；131、311 输出端子；151 恒流电路。
具体实施方式
图1是本实施方式的电压调节器的电路图。
本实施方式的电压调节器由PMOS晶体管115、116、119、120，高耐压NMOS晶体管113、114、118，NMOS晶体管111、112、117，基准电压电路110，恒流电路151，电阻121、122，输出端子131，电源端子101以及接地端子100构成。
接着对连接进行说明。恒流电路151的一方与电源端子101连接，另一方与NMOS晶体管111的栅极及漏极连接。NMOS晶体管111的源极与接地端子100连接。NMOS晶体管112的栅极与NMOS晶体管111的栅极连接，漏极与高耐压NMOS晶体管113及114的源极连接，源极与接地端子100连接。NMOS晶体管117的栅极与NMOS晶体管111的栅极连接，漏极与高耐压NMOS晶体管118的源极连接，源极与接地端子100连接。高耐压NMOS晶体管113的栅极与基准电压电路110连接，漏极与PMOS晶体管115的栅极及漏极连接。基准电压电路110的另一方与接地端子100连接。高耐压NMOS晶体管114的栅极与电阻121和122的连接点连接，漏极与PMOS晶体管116的漏极连接。PMOS晶体管115的源极与电源端子101连接。PMOS晶体管116的栅极与PMOS晶体管115的栅极连接，源极与电源端子101连接。高耐压NMOS晶体管118的栅极与高耐压NMOS晶体管113的栅极连接，漏极与PMOS晶体管119的漏极连接。PMOS晶体管119的栅极与PMOS晶体管116的漏极连接，源极与电源端子101连接。PMOS晶体管120的栅极与PMOS晶体管119的漏极连接，漏极与输出端子131连接，源极与电源端子101连接。电阻121的另一方与输出端子131连接，电阻122的另一方与接地端子100连接。
接着，对本实施方式的电压调节器的动作进行说明。电阻121和122对作为输出端子131的电压的输出电压Vout进行分压，输出分压电压Vfb。高耐压NMOS晶体管113、114，PMOS晶体管115、116以及NMOS晶体管112设为第一级放大器的结构，高耐压NMOS晶体管118、PMOS晶体管119以及NMOS晶体管117设为第二级放大器的结构。PMOS晶体管120作为输出晶体管进行动作。对基准电压电路110的输出电压Vref和分压电压Vfb进行比较，控制PMOS晶体管120的栅极电压以使输出端子131的输出电压Vout为固定。当输出电压Vout比既定电压高时，分压电压Vfb高于基准电压Vref。于是，第二级放大器的输出信号（PMOS晶体管120的栅极电压）变高，PMOS晶体管120截止，输出电压Vout变低。这样，进行控制以使输出电压Vout为固定。另外，当输出电压Vout比既定电压低时，进行与上述相反的动作，输出电压Vout变高。这样，本实施方式的电压调节器进行控制以使输出电压Vout为固定。
高耐压NMOS晶体管118作为级联晶体管进行动作。与NMOS晶体管相比，高耐压NMOS晶体管为驱动能力较低、耐压较高的构造。高耐压NMOS晶体管118和NMOS晶体管117构成级联型放大电路，能够不增大大小并确保驱动能力。成为第一级放大器的输入晶体管的高耐压NMOS晶体管113和114与高耐压NMOS晶体管118设为相同构造，能够改善在第一级放大器的输入晶体管产生的偏移的影响。在第一级放大器的尾电流源使用了驱动能力较高、耐压较低的构造的NMOS晶体管112，因此能够确保驱动能力也缩减电路面积。
通过以上方式，本实施方式的电压调节器能够改善在第一级放大器产生的偏移，能够不增大尾电流源的大小并确保驱动能力。

Claims (1)

1. 一种电压调节器，其特征在于，具备：
第一级放大器，将基准电压与对输出晶体管输出的电压进行分压的分压电压之差放大并输出，并控制所述输出晶体管的栅极；以及
级联型放大电路，
其中，所述第一级放大器具备：
作为输入晶体管的第一高耐压NMOS晶体管，以及
作为尾电流源的NMOS晶体管，
并且所述级联型放大电路具备作为级联晶体管的第二高耐压NMOS晶体管。
CN201310026597.2A 2012-01-18 2013-01-18 电压调节器 Active CN103219947B (zh)

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US20130181777A1 (en) 2013-07-18
CN103219947B (zh) 2017-11-07
KR20130084991A (ko) 2013-07-26
US8766610B2 (en) 2014-07-01
JP5833938B2 (ja) 2015-12-16
TWI561955B (zh) 2016-12-11
KR101974657B1 (ko) 2019-05-02
TW201339794A (zh) 2013-10-01

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